Transcript Mountain Region - Arizona Engineering Capabilities

ASU MAT 591: Opportunities in Industry!
ASU MAT 591: Opportunities In
Industry!
Subject: On-board Processing
By
Eric Smith
Lockheed Martin- Management and Data Systems
1
ASU MAT 591: Opportunities in Industry!
Presentation Overview

Background
– Quick overview of SAR

High level technical overview
–
–
–
–


Architectural Model
Hardware
Software
Issues
Applications
Related topics
2
ASU MAT 591: Opportunities in Industry!
GFLOPS in Space!
Space-based Radar Notional Satellite
OBP Goal:
> 100 GFLOPS
< 1 KW
< 100 KG
3
ASU MAT 591: Opportunities in Industry!
BACKGROUND
4
ASU MAT 591: Opportunities in Industry!
Why On-Board Processing?
The need for imaging satellites capable of continuous
coverage and real-time output products require high
performance on-board processing

Sensor control
– Adaptive controls to improve sensor performance (e.g. ECCM /
beamforming, adaptive optics)

Timely delivery of intelligence / dynamic re-tasking
– Direct down link assures low latency and enables direct control by
a tactical commander
– Physical antenna size precludes ultra-wide bandwidth
communications link
– OBP required to reduce information bandwidth
5
ASU MAT 591: Opportunities in Industry!
OBP Applications

SAR- Synthetic Aperture Radar
– Requires significant computational resources to form SAR images

~3500 operations per pixel
6
ASU MAT 591: Opportunities in Industry!
Example SAR Imagery
7
ASU MAT 591: Opportunities in Industry!
Example SAR Imagery
8
ASU MAT 591: Opportunities in Industry!
OBP Applications

SMTI- Surface moving target indication
– Radar application similar to SAR which is used to distinguish moving
targets for from the fixed background scene
– Collect times are fractions of a second long
– Requires combination of DSP and linear algebra to create adaptive
algorithms needed to separate the movers for scene
Moving Target
Indicator

Metrology/Controls processing
– Determining the motion of a structure so as to correct for the induced
phase errors
– Integral part of a control system; very sensitive to latency

Others…
9
ASU MAT 591: Opportunities in Industry!
Architecture Overview
10
ASU MAT 591: Opportunities in Industry!
Factors Driving an OBP Architecture
Algorithm/Application Requirements
• Effective Flops – requirement
• Memory capacity and
bandwidth
Life Cycle Cost
• NRE and Recurring
• O&M and upgrades
OBP
Architecture
Environment
• Radiation
• Available Cooling
Mission Life
• Design Life
• Reliability
SV Constraints
Risk Factors
• Size
• Weight
• Operating Power
• Schedule
• Cost
11
ASU MAT 591: Opportunities in Industry!
OBP Architecture
Network Fabric
Mass
Data Storage
MEM Slice #1
LLP
From
Sensor
MUX Mod
MEM Slice #n
LLP
MUX
Fabric
LLP
LLP
Processing
Element #n
Output
Formatter
 Link Level Protocol (LLP)
 800 MBps
Bus Computer
Processing
Element #1
cPCI
To
Comm(s)
UART
Control Proc
Control Proc
NVMS
NVMS
PE’s and
Control Proc’s
12
ASU MAT 591: Opportunities in Industry!
OBP Architectural Concepts

Modular architecture with separate module types
– Network infrastructure
– Mass data storage
– Processing elements
 Sensor data processing elements
 Control/general purpose processing elements
– IO Subsystem

Processor configured as needed for the application
– Mix of module types is determined by requirements
 Performance
 Functionality
 Availability- N+1 versus 2N redundancy
13
ASU MAT 591: Opportunities in Industry!
Representative Performance Requirements

Performance Specifications
– Processing Elements
 24 Gflops per Processing Module (PM )
 56 watts
 1 Gbyte/PE
– MDS
 64 Gbits/slice
 30 watts/slice
– Network

 8x800MBps simultaneous input channels
 16 PE maximum
SBR Configuration Requirements
–
–
–
–
240 Gflops scalable to 384 Gflops for Back End Processor (BEP)
½ Tbit
1400watts (w/ margin)
Post-mitigation Single Event Upset (SEU) Rate
 0.06 bit errors / hour
– Total Ionization Dosage (TID) Tolerance
 greater than 75 Mev*cm2/mg
14
ASU MAT 591: Opportunities in Industry!
H/W Architectures
15
ASU MAT 591: Opportunities in Industry!
Approach
Continuum of Computational Alternatives
Performance
Flexibility
GP
Microprocessors
PowerPC, x86
Commercial
DSP
TI, Analog Device, TriMedia
FPGA
Xilinx, Atmel
ASPs
LSP, LSP-II
Full Custom
LL beamformer
•Benefit from high volume /commodity production
•Large recurring technology investment
•Well understood HOL programming model,
robust set of commercially supported tools
•Low level or HDL based programming
homegrown/custom tools required
•Relative poor domain specific performance
•Excellent domain specific performance
16
ASU MAT 591: Opportunities in Industry!
FLOP/Watt Performance Comparison
Rad
Maxwell
PPC 750 SCS750
7
23
1
Narrowband/General
Purpose Processing
10
GP + FPGA/RCC
GP + FPGA
Near Future
120
390
GP
+
LSPII
1430
Comm
425
PPC G4
118
100
1000
Peak MFlops (MOp) /Watt
for large FFT in 2002
SBR LEO Threshold
Wideband Processing
17
ASU MAT 591: Opportunities in Industry!
Processing Element Trade Data
CPU
1750A
Mongoose V
THOR
Rad6000
RTDSP
RHDSP24
RHP(Pentium)
TSC695E
RAD750
LM LSP2
Virtex-II FPGA
Fixed point
Clock
MHz
Processors Flown in Space
Power
Power
SEU
Watts
MF/W
Bit/Hr
TID
Krad
16
0.4
<1
10-13
1000
25
5
<1
<<
1000
-12
50
4
4
10
1000
-16
33
3.7
3
10
1000
25
1.36
21
>>
Rad-Tolerant Processors Being Developed
75
4
375
10-4
300
166
10
7.5
1000
-12
25
1
5
<10
300
-11
166
5
7
10
200
-3
300
8.3
725
10
30
-7
10
150
8
650
100
Commercial Processors
Clock
Power
CPU
MHz
Watts
UltraSPARC-II
248
26
Pentium 4
2400
65
PowerPC 750FX
1000
6
LM-LSP+
300
5
LM-LSP2
300
8.3
LET
MEV*cm 2/mg
60
83
284
>120
>>
45
40
>>
45
75
>120
MF/W at the
chip level
based on a
256K FFT
Power at the
chip level
Estimate
Power
MF/W
3
17
33
600
725
18
ASU MAT 591: Opportunities in Industry!
Background: FPGA

FPGA: Field Programmable Gate Array
– Logic device whose configuration can be set to meet the specific
application requirement

Two types


RAM based can be reprogrammed in the field after deployment
Anti-fuse based devices can only be programmed once
– Used for prototyping, low volume applications
– Features


Embedded RAM, Multiplier Arrays, and Hard IP such as RISC cores
Current generation have the equivalent of a couple million logic gates


Next generation will have 10s of million logic gates
Basis for Reconfigurable Computing Paradigm
19
ASU MAT 591: Opportunities in Industry!
Example FPGA: Xilinx Vertex-II
Conf
Logic
Block
Frames
(CLB)
20
ASU MAT 591: Opportunities in Industry!
Features of processing

DSP for image formation
– Complex arithmetic

Single precision floating-point or fixed point math
– Linear shift-invariant operators


FFT
FIR filtering
– Extremely high data/processing rates


100’s of GFLOPS
Linear algebra for motion compensation and SMTI
– Double precision
– Exception handling

Heuristic & non-linear processing for backend processing
– Includes “pixel polishing” and SMTI
21
ASU MAT 591: Opportunities in Industry!
Approach based on heritage systems
Enhanced Parallel Vector Supercomputer
Enhanced MPP Supercomputer
22
ASU MAT 591: Opportunities in Industry!
Reconfigurable Computing Paradigm

Utilizes FPGAs or FPGA-like devices that can be configured in
such a way that is “optimal” for a specific processing task
– The meaning of “optimal” depends on the criteria



Fastest time-to-market
Highest throughput for the least amount of energy
Goal is to program these devices using standard S/W
processes while achieving “optimal” performance
– E.G. ‘C’ to circuits using a GNU compiler
– Lots of on-going research with promising results


JHDL at BYU, Stream-C at LANL
FORGE tool by Xilinx
– LM uses a combined Top Down/ Bottoms-up Methodology to achieve
“optimal” performance based on highest FLOP/Watt criteria
23
ASU MAT 591: Opportunities in Industry!
Processing Element

FPGA Based
– Gate density/performance now permits system-on-chip complexity


Available with embedded RISC processors and other IP
I/O and chip package pin count limitations overcome by moving functions onto
a single chip
– Commercially supported tools and development environments
– Avoids high NRE costs for advanced semiconductor processes





$1M+ mask charge in 90nm process
Higher risk
Requires Large on-going investment in a non-core competency
Availability of vendors for low volumes uncertain (ROA thing)
Overall programming model comparable with heritage systems
– Differs at the low level programming step
24
ASU MAT 591: Opportunities in Industry!
Processing Element Module (PEM)
PE 1
40
10
PortA
Config/
SEU
BufA
10
40
I/O=
345
Power= 5 watts
115
DATA STORAGE
DDR SDRAM
1 GBYTE
12 Watts : 16 chip
PortA
Config/
SEU
BufA
Interface
/ TMR Supervisor
(Actel RTAX2000S)
RapidIO
(8-bit)
150MHz
BufB
BufC
110
110

BufD


PE 2
40
RapidIO
(8-bit)
PortB
PortC
110
110
110
110
QDR SRAM QDR SRAM QDR SRAM QDR SRAM 7.5 Gflops
11.6 watts
256Kx72
256Kx72
256Kx72
256Kx72
650 Mflop/w
.9 watts: 1 chip
.9 watts: 1 chip
.9 watts: 1 chip
.9 watts: 1 chip
22.5 Gigaflops
51.8 watts (peak)
367 Mflops/watt
40
Xilinx
XC2V6000
Xilinx
XC2V6000
PortB
PortC
150MHz
BufB
BufC
110
110
PE 3
10
PortA
Config/
SEU
BufA
Xilinx
XC2V6000
PortB
PortC
150MHz
BufB
BufC
•
3 sections per module
•
22.5 Gflop/s peak throughput
(sustained for large FFTs)
•
1 GByte shared memory
•
8 MByte local memory per
section
BufD
110
110
110
110
QDR SRAM QDR SRAM QDR SRAM QDR SRAM 7.5 Gflops
11.6 watts
256Kx72
256Kx72
256Kx72
256Kx72
650 Mflop/w
.9 watts: 1 chip
.9 watts: 1 chip
.9 watts: 1 chip
.9 watts: 1 chip
40
User enabled TMR based SEU
mitigation using RHBD FPGA
Maintains primitive /algorithm
compatibility
GP control from external RHDB
computer
110
110
BufD
110
110
110
110
QDR SRAM QDR SRAM QDR SRAM QDR SRAM 7.5 Gflops
11.6 watts
256Kx72
256Kx72
256Kx72
256Kx72
650 Mflop/w
.9 watts: 1 chip
.9 watts: 1 chip
.9 watts: 1 chip
.9 watts: 1 chip
POWER CONVERTER
70% efficient
(22.2 Watts dissipated @ 51.8 Watt load)
Acronyms
RHBD
TMR
Rad-hard by design
Triple modular redundancy
25
ASU MAT 591: Opportunities in Industry!
RCC Implementation Styles

Two styles used by Lockheed Martin
– Optimized “Primitives”

Circuits are developed and specifically optimized for each operation type



Collections of such circuits are implemented on a physical FPGA device



E.G Fast Fourier Transform
Circuits developed using a h/w description language such as Verilog or VHDL
Routing between these circuits implement an algorithm
The FPGA is reconfigured as needed with different primitives to implement the overall algorithm
Issues


Can be used where reconfiguration time is not an issue
May require a large number of primitive types
– Micro-coded Function Module Group



A few programmable state-machine based circuits are developed that can perform the
processing required for a class of operation types
Multiple copies of such circuits are implemented and programmed separately for each
task
Issues


Useful when configuration time is at issue
Typically less optimal
26
ASU MAT 591: Opportunities in Industry!
Example RCC Styles
Micro-coded FMG
Optimized Primitives
Function Module Group
Function Module Group
Function Module Group
Algorithm Partition Area
QDR_Ram QDR_Ram QDR_Ram
PC IF
A
PORT A
B
PORT B
C
PORT C
DFC
FFT
RFG
Interconnect
27
ASU MAT 591: Opportunities in Industry!
H/W Abstraction Layer


Exposes germane implementation details to application
developers
Standard API simplifies application development
– Fosters re-use
– Simplifies maintenance and spiral development

Provides a standard set of resources to the application partition
– Infrastructure treated as fixed IP



Memory interface including address controller
External interface
Embedded controller
28
ASU MAT 591: Opportunities in Industry!
H/W Abstraction Layer
To/From Control FPGA
External I/F
ACF
QDR
Memory
ACF
QDR
Memory
ACF
GP Controller
QDR
Memory
QDR
Memory
ACF
Algorithm Partition Area
(algorithm partitions go here)
Fixed IP
29
ASU MAT 591: Opportunities in Industry!
GP Controller
External I/F
ACF
QDR
Memory
ACF
QDR
Memory
ACF
QDR
Memory
ACF
GP Controller
QDR
Memory
Algorithm Partition Area
(algorithm partitions go here)
Fixed IP
MicroBlaze 32-bit RISC Core
•Performs initialization, algorithm level sequencing and control, exception handling
•Vendor supported tool suite and development H/W
•GNU, VXWorks
•82 D-MIPS @ 125 MHz on Virtex-II (-5)
•Instantiated Size (min): 900 cells (plus memory, peripherals)
30
ASU MAT 591: Opportunities in Industry!
FMG Approach

Consists of the resources needed to implement required
arithmetic operations
– Arithmetic units, local memory, and local control

Used in conjunction with the H/W abstraction layer to
implement primitives
– Overall primitive control encapsulated in the API

Primitive operation uses global resources that are part of the HAL
– Viewed by the application programmer as a library

High level control provided by on-board RISC controller
31
ASU MAT 591: Opportunities in Industry!
Generic FM Architecture Description
Initialization
& Control
Configuration Registers
Status
Microcode SM
Static & Dynamic
control
Condition
Codes

Implements data path part of
primitive functions
Data Path
Data Out
Local Memory
– Used in conjunction with HAL/GP
Data In

Calls initiated by GP in ‘C’
FMG
Initialization
32
ASU MAT 591: Opportunities in Industry!
Optimized Primitive: Radix-2 FFT
Part:XC2V6000-5FF1152
Part Utilization: 10% (overall)
Circumscribed Area Utilization: 20%
Flip flops
LUTs
Slices
BRAMs
18x18 Mpy
Fold
= 11%
= 7%
= 15%
= 6%
= 11%
Power = 2.4 watts
Speed (-5) = 5.824 ns = 171 MHz
Mpy
Add
Dly
Read Address Generator
Write Address Generator
Add
In
Mpy
Half Butterfly
Add
Timing & Control
Out
Output Multiplexer
Mpy
QDR_BankB
Add
Dly
Half Butterfly
Add
QDR_BankA
Mpy
Add
Twiddle Generator
33
ASU MAT 591: Opportunities in Industry!
FFT Logic Placement Comparison
Manual placement
Automatic placement
Fold
Mpy
Add
Dly
Read Address
Generator
Add
Write Address
Generator
In
Mpy
Add
Timing &
Control
Out
Mpy
QDR_BankB
Output
Multiplexer
Add
Twiddle
Generator
Dly
Add
QDR_BankA
Half
Butterfly
Half
Butterfly
Mpy
Add
Manual placement results in better overall device utilization,
increased performance, and is more conducive to re-use
34
ASU MAT 591: Opportunities in Industry!
Algorithm Implementation Process
35
ASU MAT 591: Opportunities in Industry!
Example Processing Dataflow
FEP: “Front End” Processing
E
S
A
Multi-Channel
Receiver
Filter RF
Subbands
Offset A-to-D
Converters
Delay and Equalize
ESA Ch.s
Form 4
GMTI Beams
OBP: “Back End” Processing
MDS
Convert Fast
Time to
Frequency
Compress
to Azimuth
Combine
Subbands
Correct
Subbands
Background
Sampling
Compress Full
- BW Pulses
Resample
Polar VPH
Multi_Algo
Weights
Calculations
Multi_Algo
Detectors &
CFARs
Compress
Subbands to Range
Suppress Clutter /
Filter Velocities
Multi-Algo NCI /
CPI Combiners
Turn Range to
Slow Time
Turn Azimuth
to Range
Target
Reports
36
ASU MAT 591: Opportunities in Industry!
Decomposition to primitives
Convert Fast
Time to
Frequency
Correct
Subbands
Resample
Polar VPH
• Data Format
• Fast time sample
Convert (DFC)
adjust
• Mo-comp phase • Fresnel quadratic
stabilization
removal
• Fast time to RF • Fresnel De-ripple
xform
Compress
to Azimuth
Background
Sampling
Compress
Subbands to
Range
Turn
Range to
Slow Time
• (bypassed
in WAS
mode)
Multi_Algo
Weights
Calculations
Suppress
Clutter / Filter
Velocities
Turn
Azimuth to
Range
S
• (Staggers
formation)
• Azimuth weighting
• Doppler vs. Rg
sample shift in AZ
Combine
Subbands
• Phase Training /
Culling
• Power Selected
• Eigen decomposition
Training
• Sample Matrix
• Compute
Inversion
covariances
• Adaptive channel
• Perform 2_D
balance
smoothing
Compress
Full - BW
Pulses
Multi_Algo
Detectors
& CFARs
• Apply weights
• (Combine staggers)
• Combine 4-to-3
beams
Multi-Algo NCI /
CPI Combiners
Target
Reports
S
• Incl “Burn Through Clutter
Discrimination
37
ASU MAT 591: Opportunities in Industry!
Algorithm Components
Chain:
Sequence of Primitives- Programmed in HOL (‘C’)
Primitive:
A signal processing function (kernel) on the scale of a
complete FFT or vector filtering function
Examples:
cc
RFG
FFT
IPF
SQRT
Reference
Function
Generator
Fast
Fourier
Transform
In-Plane
Filter
Square Root
Complex Multiply
Perform FFT on
Signal Vector
Filter the
Complex Signal
Take the Square
Root of Realvalued samples
38
ASU MAT 591: Opportunities in Industry!
Components of a Primitive
e.g. Vsma(v1, d1, x, v2, d2, d3, cnt)
void Vsma(V *v1, int d1, double x,
V *v2, int d2,
V *v3, int d3, int cnt)
{
API
// Init Address
*adr_src1_strt=
*adr_src1_inc=
*adr_src2_strt=
*adr_src2_inc=
RISC Controller
Generators
v1;
d1;
v2;
d2;
FMG
HAL
// Init FMG
*fmg_c1= x;
*mc_adr= Vsma;
*mc_start= go;
Configuration Registers
FMG
Microcode SM
Data Path
}
Configuration Registers
Device Device
Device
39
ASU MAT 591: Opportunities in Industry!
Primitive Development Process

Specify

– Derive requirements
– Develop test plan

–
–
–
–
Design
– Create API
 Create a high level model of the primitive
in “C”
– Perform functional decomposition
– Create data flow
Implement


Write HOL interface
Write microcode
Simulate
Verify
Acceptance Test
Document
– Update programmer’s guide

Signoff and Promote
– Update primitive library
40
ASU MAT 591: Opportunities in Industry!
Implementation Flow
2

B  

A  exp  j 2k  f  az  

2  


Algorithm Prototyping &
Implementation
•
•
•
Matlab©
Mathcad©
HOL
Algorithm Development
–Top-down
–Canonical S/W development
environment
–Supports mixed environment
API
Primitive
Specification
Functional Prototype
Primitive Development
•Workstation/PE
•Allows rapid prototyping
Primitive Library Development
(Off-Line)
Faster,
Harder,
more results….
– Bottom-up
 Microcoded data path
 Low-level initialization
41
ASU MAT 591: Opportunities in Industry!
Chain Development
Emulation executed on the workstation
RFG2A
RFG2B
Synthetic Target
-1
Phase History
Generator
c
c
c
FFT1
Deskew Phase
Change
+1
r
Range Ripple
Correction
FFT2
DFC
Data Format

Environment supports mixed implementation of FPGA and
workstation based functional prototype primitives
– During development, chains implemented as individual calls to the
PEM, possibly with FPGA reconfiguration between calls

Functional prototypes used as the specification for the
FPGA implementation
42
ASU MAT 591: Opportunities in Industry!
Development Testbench
PEM
Testbench
Stimulus Data /Operating
Parameters
Configuration Bit
Streams
Results
43
ASU MAT 591: Opportunities in Industry!
Issues related to OBP
44
ASU MAT 591: Opportunities in Industry!
Issues: Radiation

Two Basic Effects
– TID- Total Ionizing Dose





The amount of ionizing radiation that a device can tolerate before it fails
Cumulative effect that is highly dependent on the orbit and mission duration
Devices that are able to withstand > 200KRads are considered radiation
tolerant
Can be mitigated by shielding
Causes increased current flow possibly leading catastrophic device failure
– Single event effects (SEE)

Effects typically caused by high energy particles which temporarily interrupt
device operation

SEU-single event upsets
» Cause registers/memory to change state resulting in incorrect results being generated

SEFI- single event functional interrupts
» Causes the device to stop functioning until reset or power-cycled

SEEs rates are a function of the orbit, solar flare activity, and the device
characteristics

Unaffected by shielding; requires active mitigation techniques to overcome
45
ASU MAT 591: Opportunities in Industry!
Radiation Environment
LEO
– TID post-shield 2.83E+03 (no margin)
– SEU Effects
 Heavy Ions Flux: at 30MeV-cm2/mg = 500E-06
at 80MeV-cm2/mg = 150E-06
 Galactic
at 30MeV-cm2/mg = 500E-09
Cosmic Rays:
at 80MeV-cm2/mg = 150E-09
– Orbit: 600 Km circular, 94° inclination, 5 year

krads
10,000
Example Equatorial Orbit,5 Years, No SAA
1000
100
Commercial Component
Radiation Range
10
1
MEO
– TID post-shield 67.0E+03 (no margin)
– SEU Effects
 Heavy Ions Flux: at 30MeV-cm2/mg = 500E-06
at 80MeV-cm2/mg = 150E-06
 Galactic
at 30MeV-cm2/mg = 500E-09
Cosmic Rays:
at 80MeV-cm2/mg = 150E-09
– Orbit: 10,000 Km circular, 94° inclination, 5 year
1
2 3 4 5 6
7 8 9
Orbital Altitude (1000 kilometers)
10
XQ VR300 SEU Rate s
Dynamic Functio n Up s et Rate
10.0000
SEU's per day

1.0000
No Ups e t M itiga tio n
0.1000
0.0100
B e ne fit o f TM R
a nd S c rub
0.0010
0.0001
100
1,000
10,000
Orbital Altitude (km) (at 60 deg)
(CREME96 & AP 8ma x)
r e vi s e d 9/ 7/ 2000
46
ASU MAT 591: Opportunities in Industry!
Latch-up


Potentially catastrophic device failure mechanism that can be
brought on by prolonged exposure to a radiation environment
Parasitic BJTs within MOS transistors and the existence of path
for current flow can result in the creation of an “induced”
Darlington-pair transistor (2 gain).
*Digital Integrated Circuits, by Jan M. Rabaey, Prentice Hall ‘95
47
ASU MAT 591: Opportunities in Industry!
Raw Unmitigated 2V6000 Upset Rates
2V6000 Raw Device Unmitigated SEU Rates
Functional Block
Functional Element Breakdown
Slices
100% Device Element Utilization33792
POR SEFI
JCFG SEFI
SelectMap SEFI
Totals:
33792

% CLB
Logic
100.0%
100%
Block
Ram bits
2,654,208
CLB-FF
67,584
100%
100%
Upsets/device-day
Worst
GCR Max Worst Day Week Day
1.96E+01 8.90E+02
234.370
1.39E-05 1.46E-03
3.17E-04
7.19E-06 2.81E-04
7.61E-05
1.87E-05 1.79E-03
4.31E-04
19.568
890.125
234.370
1000km, 90 degree inclination orbit, CREME96
 GCR max – The solar-quiet ("no flare") model in CREME96 represents the ambient
environment, which prevails in the absence of solar energetic particle ("flare") events. This
environment, which varies slowly in intensity over the 22-year solar cycle, is the basic
environment in which all space systems must operate.
 Worst Week Day (WWD) – This model is based on SEP fluxes averaged over the 180 hours
(=7.5 days) beginning at 1300 UT on 19 October 1989. This week was the most severe SEP
environment observed in the last two solar maxima (roughly 1980.5-83.5 and 1989.0-92.0). It can
therefore be used as a "99% worst case" environment for systems designed to operate through
solar maximum.
 Worst Day (WD) – This model is based on SEP fluxes averaged over 18 hours beginning at
1300 UT on 20 October 1989. This period was the single largest flux enhancement in October
1989. It was caused by the arrival at Earth of a powerful interplanetary shock, which also
produced a large geomagnetic storm.
48
ASU MAT 591: Opportunities in Industry!
Raw 2V6000 Upset Rates
GCR Max Upsets/Dev-day vs Utilization
18.0000
16.0000
14.0000
12.0000
CLB Upsets
10.0000
BRAM Upsets
8.0000
Registers
6.0000
4.0000
2.0000
0.0000
1
8
15 22 29 36 43 50 57 64 71 78 85 92 99
% Utilization

Upsets in the CLBs dominate device upset rate
49
ASU MAT 591: Opportunities in Industry!
Mitigated Upset Rate
Mitigated Upset Rate/Device-day
Slices
% CLB
Logic
DDR SDRAM Controller
9018
26.69%
9228
Rapid I/O Logic
8706
25.76%
9009
R-S EDAC
2316
6.85%
192
0
DMA controller
1737
5.14%
1,336,704
2685
PCI I/F
945
2.80%
0
669
Block Ram bits
CLB-FF
Sensor I/F
864
2.56%
13,392
2142
Software
7695
22.77%
19,872
5226
Test
GCR Max
Worst Day
Worst Week
Day
1422
4.21%
1209
3.16E-01
1.43E+01
3.71E+00
Misc Logic
0
0.00%
0
0
0.00E+00
0.00E+00
0.00E+00
Voter Logic
100
0.30%
0
0
4.9E-02
2.2E+00
5.8E-01
POR SEFI
1.4E-05
1.5E-03
3.2E-04
JCFG SEFI
1.9E-05
1.8E-03
4.3E-04
SelectMap SEFI
7.2E-06
Totals:
32803
97.07%
58.22%
44.64%
Functional Error Reduction Factor
Totals

0.365
2.8E-04
16.456
7.6E-05
4.292
10
10
10
0.041
2.034
0.458
Also considering the 1 in 10 functional error rate factor.
– About 1 in 10 configuration errors results in a real functional error.

The mitigated upset rate .041 non-flare, 2.03 flare, per device/day
50
ASU MAT 591: Opportunities in Industry!
Approaches to SEU Mitigation

Hard By Design
– Use semiconductor technology and libraries that are inherently radiation
hard



Few manufacturers
Older technologies that don’t meet SWaP (and performance) requirements
TMR- Triple Mode Redundancy
– The “Gold” Standard
– Uses majority voting to determine the correct output from a logic block
– Expensive- Requires essentially 3x the amount of H/W to implement
each function

Signature Analysis
– Logic block stimulated with a known input; output checked to verify that
the correct response is generated
– Can be implemented with little overhead using CRC
– May be difficult to generate stimuli that provides good circuit coverage
51
ASU MAT 591: Opportunities in Industry!
Other Approaches to SEU Mitigation

Exploits characteristics of the algorithms to detect efforts
– Consider the discrete Fourier transform and efficient implementations
called fast Fourier transform
FFT
f(t)
F()
– What do you know about the energy content of a signal on either side of
the transform?
Parseval’s Theorem:




f (t )  f * (t ) dt   F ( )  F * ( ) d

52
ASU MAT 591: Opportunities in Industry!
Issues: Mission Success

Fault-tolerance / graceful degradation
– The ability to continue to operate in the presence of faults perhaps at
diminished capacity
– Achieved thru robust design and verified thru extensive analysis and
testing


Elimination of failure modes in which a single failed component could render
the entire system non-operational
Approaches
– Redundancy


N+m- Incremental redundant functional
A/B Side- duplicated subsystems that are cross-strapped
– Error Detection and Correction (EDAC)

Used extensively in memory and network subsystems
– Reprogramming / Reconfiguration
53
ASU MAT 591: Opportunities in Industry!
Fault-tolerance
Cross-strapping
N+m
•Employs redundancy throughout
•Memory and PE modules
•Data paths
•EDAC in memories and network
•Reprogramability / Reconfigurability
54
ASU MAT 591: Opportunities in Industry!
In-flight changes
OK
OBP
Test
Collection and
Processing
Failure
Config
File
Uplink
Change
Detection
OK
OBP
Self Test
Incorporate
Modification
TES
Change
Analysis and
Correction
Data or
Code +
Config File
Uplink
Test and
Integration
Support
Facility
EDU
Support
Facility
The process being used on an
operational ground based system is
directly applicable to the SBR program
55
ASU MAT 591: Opportunities in Industry!
Future Generation OBP
56
ASU MAT 591: Opportunities in Industry!
MEO Notional Design




Nominal 100m x 9m AESA feed
50 nominal phase center spacing
400 channels (1.5m x 1.5m panels)
5,000km (2,700 NM) - 15,000km (8,100
NM)
MEO SBR concept requires designers to re-think
their approach: distributed processor architecture
57
ASU MAT 591: Opportunities in Industry!
Architectural Concept
100m
Enhanced fault-tolerance
Sensor Input
SM
NIC
SM Ctl
PP
P
VPE
f1
f2
f3
DSP
Engine
DSP
Engine
DSP
Engine
LM
LM
N/W I/F
PPC405
Combination of DSP engine hard macrocell and
FPGA enable overall algorithm optimization
OCC
Versatile Processing Element (VPE)
Network of distributed processing elements
reduces cost and improves fault-tolerance
58