Transcript CPU Performance

SoC Architecture Course
Oct 2008 – Jan 2009, KTH
Zhonghai Lu / Axel Jantsch
[email protected]
Course Information
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Course responsible: Dr. Zhonghai Lu
Course examiner: Prof. Axel Jantsch
12 Lectures, 4 Tutorials, 3 Labs
Home page: www.ict.kth.se/courses/IL2207
Course Material
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Dally, Towles: Principles and Practices of Interconnection
Networks
Distributed Material
Slides
Advanced-level course, more demanding
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Lecture Overview
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L1: Introduction
L2: Buses and Arbitration (Dally: 22, 18)
L3: Shared Memory Multiprocessors
L4: Cache Coherency Protocols
L5: Memory Consistency
L6: Introduction to Network-on-Chip, Topologies (Dally: 1, 2, 3, 4, 5)
L7: Routing Algorithms and Mechanics (Dally: 8, 9, 10, 11)
L8: Flow Control (Dally: 12, 13)
L9: Deadlock and Livelock (Dally: 12, 13, 14)
L10: Router Architecture and Network Interface (Dally: 16, 17, 20)
L11: Quality of Service and Performance Analysis (Dally: 15)
L12: Course Summary and Trends
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Tutorial Overview
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T1: Bus, arbitration and cache coherency
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T2: Memory consistency and network topology
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After Lecture 7, on Nov. 12
By Dr. Lu
T3: Interconnection networks (routing, flow control, deadlock etc.)
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After Lecture 5, on Nov. 5
By Prof. Jantsch
After Lecture 8, on Nov. 19
By Dr. Lu
T4: Router architecture, QoS and performance analysis
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After Lecture 12, on Dec. 3.
By Prof. Jantsch
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Lab Overview
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Laboratory 1: Uniprocessor SoC Design with Altera
Laboratory 2: Multiprocessor SoC Design with Altera
Laboratory 3: Wormhole Networks
Students work in groups of max. 2
Good preparation is required.
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Course Requirements
To pass the course the student has to fulfill the following
requirements:
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Pass the final exam. The grade for the exam will
be the grade of the course.
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Final exam: Dec. 16, 2008, 9:00-13:00,
Room 432, 438, 439,530
** Register the exam in Daisy 2 weeks before the
exam date in order to guaranttee a seat *!
Attend tutorials
Complete all labs
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Observations in
System Design
Advances in Integration
Intel 4004
(1971)
Intel Pentium 4
(2000)
1.5 GHz
42 million transitors
108 KHz
2,300 transistors
If automobile speed had increased similarly over the same
period, we could now drive from Stockholm to Shanghai in
about 23 seconds.
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Advances in Integration - 2007
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Intel Terflop
Chip 2007
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http://techresear
ch.intel.com/arti
cles/TeraScale/1449.htm
Growing Design-Productivity Gap
Moore’s Law:
Design Productivity Crisis
Standard cell density and speed
10,000
100,000,000
Gates
Clock
1,000
100
Logic Transistor per Chip (M)
Equivalent Added Complexity
1,000
10,000
Logic Tr./Chip
100
Tr./S.M.
1,000
10
100
1
10
0.1
xx
xx
x
x
x
1
x
0.01
0.1
0.001
0.01
Productivity (K) Trans./Staff – Mo.
Density (Kgates/mm2)
ASIC clock (MHz)
Potential Design Complexity and Designer Productivity
10,000
Source: (SRC 1997)
Designs do not only get more complex, but also much more expensive!
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The Role of the Market!
Source: Smith 1997
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Moore’s Law drives the development
of System-in-Chip Architectures
RTL
function 1
Processor
RTL
function 2
Yesterday’s SOC
RTL
function 3
The growing number of
transistors on an SOC drives
the trend towards more RTL
blocks on the chip
Memory
RTL
I/O
Ctl RTL RTL RTL
Proc RTL RTL RTL
Mem
RTL RTL RTL
RTL RTL RTL
DSP RTL RTL RTL
Mem RTL RTL I/O
Today’s SOC
Source: Leibson (DAC2004)
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Verification Costs
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The percentage of the verification costs of the
total design costs is continuously increasing
(at present 50-70% for large designs)
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Platforms reduce Costs
SOC Flexibility = Per-Unit Cost Reduction
Source: Leibson 2004
(Model: 100K and 1M system volumes)
120
Low-end
still camera
100
Total per unit cost
100 000
High-end
still camera
1 000 000
80
60
40
20
Video camcorder
0
1
One Chip
2
3
4
5
6
7
System designs per chip design
Many System Designs
$10M design cost, $15 manf. cost, 5% premium for programmability
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Platform Example: Nexperia
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Nexperia Instance: Viper
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Arm based MPSoC Platform
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Texas Instruments
OMAP
A SOC Platform
based on
Peter Cumming: ”The TI OMAP
Platform Approach to SOC”
The OMAP platform
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OMAP products are combinations of hardware and
software allowing mutimedia capabilities to be included
in 2.5G and 3G wireless handsets and PDAs
Critical design paramters are: Performance, Power,
Cost and Time-to-Market
First Approach: ”Opportunistic Reuse”
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No planned reuse, but try to reuse whenever possible
Second Approach: ”Structured Approach”
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Systematic Reuse, SoC Platform
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What is a platform?
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OMAP defines a platform as
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”a packaged capability used in subsequent stages of the
development to reduce development costs”
Platforms have the following characteristics:
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Between silicon and systems many platforms may be
developed and used in subsequent stages of the
development
Platforms are valuable due to the notion of reuse (good for
economy)
They include hardware, software, assemblies and tools!
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Examples for platforms
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Transistor and ASIC libraries are the lowest
hardware platforms
Instruction Set Architecture and associated
Assembly Language Tools are the lowest
levels in Software
These well-understood levels are used by
other OMAP platforms
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OMAP: Hierarchy of Platforms
Application
Specific
Ref
Design
Appl.
Platform
SoC Platform
OMAP Products
OMAP Infrastructure
ASIC Library & Tools
Silicon Technology
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Reuse
OMAP uses platforms on different levels
This is a precondition for reuse
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SoC Platform
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The SoC platform consists of
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The Application Platform (the OMAP product)
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A library of hardware components
An architecture for their interconnection
Processor and Peripherals
Low-Level Software (Drivers)
Development Environment
The System Platform
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The platform includes the code that controls all aspects of the
system from device driver to system interface
TI has a reference design group in order to understand the new
demands for OMAP
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OMAP Products
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The OMAP product range consists of several
families of devices for different markets, e.g.
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Application processors for 3G: OMAP 1510 and
1610
Application processors for 2.5G: OMAP 710 and
730
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OMAP 1510
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OMAP 1510 is based on
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Enhanced ARM 925 core (RISC processor)
TI C55x core
DMA, SRAM, Busses, Peripherals
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Current OMAP platform for
Wireless Handset & PDA
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OMAP™ 3 architecture combines mobile
entertainment with high performance productivity
applications (Source: Texas Instruments)
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Strength of the OMAP concept
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The main strength of the OMAP concept is that several actors can
make extensive Reuse of development efforts at several levels of
the design process
Actors:
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Levels:
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Mobile Device Manufacturers
Software Developers
TI’s internal Development Teams
Common Hardware and Software Interfaces
Common Development Environment
Single Low-Level Software Framework (Code can be used for several
products)
Single SoC Platform
OMAPI is an interface standard for OMAP founded by TI and ST
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OAMP Architecture
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The OMAP architectute consisting of general
purpose processor and DSP has been
chosen because of the application area
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Need for Performance
Energy and Area Constraints
Two Main Tasks: User Interface and Signal
Processing
Flexibility and Reuse
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Requirements on Software
Platform
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Hardware architecture requires a matching
software approach
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Well-defined Set of Application Programming
Interfaces in the high-level OS running on the
general purpose processor
System Software that links General Purpose
Applications to DSP components
Well-defined Standard for DSP Components
(TMS320 Algorithm Standard or eXpressDSP)
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Summary
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The OMAP platform
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Covers a wide range of products allowing to
reuse Hardware and Software
Hardware Architecture adopted to Application
Area
Software Architecture using features of Hardware
Architecture
Efficient SOC Platform with Definitions for
Hardware and Software Reuse
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Emerging
Architectures
System-on-Chip Architectures
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A system-on-chip architecture integrates several
heterogeneous components on a single chip
Microcontroller
Communication
Structure
AnalogDigital
DSP
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July 20, 2015
Memory
FPGA
DigitalAnalog
Custom
Hardware
A key challenge is to design the communication between the
different entities of a SoC in order to minimize the
communication overhead
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System-on-Chip Architecture:
A bus-based SoC
Memory
Microprocessor
System on a chip
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Custom
Logic
SoC Architecture
DSP
I/O
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System-on-Chip Architecture:
Network-on-Chip
Switch
PE1
NI
NI
PE3
Channel
PE2
Resource
NI
NI
MEM
Network Interface
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The resources are connected to the network via
network interfaces
The topology of the network and the capability of the
switches and communication channels determines
the capacity of the network
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ASIC Technologies
What is an ASIC?
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ASIC = Application Specific Integrated Circuit
An ASIC is an integrated circuit for a specifc
application and (generally) produced in
relatively small volumes.
An ASIC-technology helps to shorten the
design time by providing a semi-fabricated
integrated circuit
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ASIC families
The term ASIC is often reserved for circuits that are fabricated
in a silicon foundry, while circuits that can be programmed at
the customer’s site are called Programmable Logic.
Programmable Logic
 Programmable Logic
Device (PLD)
 Field Programmable Gate
Array
ASIC
 Standard Cell
 Gate Array
The term full custom is reserved for circuits where all silicon
layers can be optimized. This implies a long design process
and thus full custom is mainly used for high-volume high-end
circuits.
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Standard Cell
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Standard cells are often referred
as Cell-Based Integrated Circuits
(CBIC)
All mask layers are customized
The standard cell library defines
logic elements of varying
complexity: SSI, MSI logic, data
path blocks, memories and
system-level blocks.
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Standard Cells
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Cells are configured in rows and have constant height and variable
width
Each cell is optimized for an efficient implementation
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Gate Array
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A gate array chip contains prefabricated
adjacent rows of PMOS and NMOS
transistors
The gate array is configured by the
interconnect structure
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Channeled Gate Array
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Only the interconnect is
customized
The interconnect uses
spaces between rows
of base cells
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Channelless Gate Array
(Sea of Gates)
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Only the interconnect is
customized
Cells are connected via
unused transistors
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Field Programmable Gate
Arrays
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None of the layers are
customized
Basic logic cells and
interconnect can be
programmed
Basic cells can be SRAM
based, Flash Memory
based or fuse-based
(one time programmable)
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Programmable Logic Device
• No customized mask
layers or logic cells
• A single large block of
interconnects
• Macrocells consist of
programmable array
logic followed by a flipflop or latch
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Comparison
FPGA, Gate Array, Standard Cell
FPGA
Initial Cost
Cost per part
Performance
Fabrication
Time
Low
High
Low
Short
High
Low
High
Long
Gate Array
Standard Cell
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Design Trade-Offs
Design Time
Full Custom
Standard Cell
Gate Array
Programmable
Logic
Microprocessor
Performance
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Challenges for
System Design
How to design a system-onchip?
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Implementation
 Efficient implementations require
to exploit the low-level features of
the target architecture
Challenge for
System Design!
July 20, 2015
Idea (Specification)
abstract
Design
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Specification
 Design productivity increases
with the level of abstraction
 The task of functional verification
is very difficult at low abstraction
levels
Abstraction Gap
detailed
Product (Implementation)
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SoC Design
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The continuous progress in silicon process technology allows
to increase more and more functionality on a single chip =>
Systems on a chip become reality
Market-driven forces:
 Shorter product design schedules and life spans
 Products have to confirm to standards
 The design has to be right from the start. An
implementation error means heavy loss of money or
product death
 Large designs are integrated into a single chip
The SoC design process must address these driving forces
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The Design Process
Design Step
Intermediate Model
Abstraction Gap
Abstraction Level
Design Specification
Implementation
Design Space
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Requirements on Design Flow
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Design Entry
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Well-defined abstract specification model
Efficient verification methodology
Design Refinement
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Well-defined models at all abstraction levels
Well-defined refinement steps
Verification at all levels
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Requirements on Design Flow
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Implementation Mapping
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Efficient platform architecture with well-defined
API
Mapping detailed implementation model to API
services
Tool Support
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Verification
Design Refinement
Implementation Mapping
Estimation of Properties
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Design Process
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A design specification has to be mapped on an
architecture
Design
Specification
Architecture
Specification
Design
Process
Design
Implementation
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Design Process
(Uniprocessor)
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A program is compiled to assembler code for a chosen
uniprocessor and operative system
Program
(Parallel Tasks)
Uniprocessor
+
Operating Syst.
Compilation
Executable
Code
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Design Process
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The design process for a SoC applications is a very
complex task
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Many components work in parallel and communicate with
each other
A task can be mapped on different components
The overhead for communication depends on how tasks
are located
The designer has to choose an appropriate SoC
architecture, since different architectures have different
strength and weaknesses
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Design Process
(System-On-Chip)
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A specification shall be mapped onto a SOCArchitecture with several heterogeneous components
Specification
(Parallel Tasks)
SoC Arch.
with several
components
Partitioning, Mapping,
Compilation
HW Descr.
Comp. A
July 20, 2015
HW Descr.
Comp. B
SoC Architecture
Code
Processor X
Code
Processor Y
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Platform-Based Design
The idea of a platform is to simplify the
design process
Programmers Model
Hardware Abstraction
Hardware Platform
Microcontroller
FPGA
Communication
Structure
AnalogDigital
DigitalAnalog
Custom
Hardware
DSP
July 20, 2015
Memory
SoC Architecture
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System-on-Chip Platform
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Layered Concept
allows to
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API
Services with Guarantees
Change the physical
architecture of the SoC
without affecting the
application
Add new services on top
of existing architecture
Changes in one layer
affect only the layer
itself and its interfaces
July 20, 2015
SoC Architecture
Transaction
Messages, Load/Store
Transport
Packets
Physical
Wires, Clocks
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Concurrency
Embedded Systems have to
cope with Parallelism
Sink
C
A
Embedded
System
B
Reactive
Environment
D
Source
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Provides an alternative to faster clock for performance
Applies at all levels of system design
Is essential within embedded system design, where the
system has to react to several inputs from the
environment
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System-on-Chip:
A Parallel Architectures
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A parallel computer is a collection of processing
elements that cooperate to solve large problems fast
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Resources
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Data access, Communication and Synchronization
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Processing capacity of the components
Distributed and/or global memory
Communication protocol
Communication capacity
Communication abstraction and primitives
Objectives
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Performance and Scalability
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Components in a Parallel SoC
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Microprocessor cores or DSP:s are cheap and
optimized for their application area
Customizable hardware can be used to guarantee a
high performance for a special task
Often each parallel task does not need a
tremendous processing power
It is important, how the parallel tasks can be
mapped onto the SoC so that the parallel nature of
the system can be fully exploited
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Communication Primitives
System on Chip
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There are two main paradigms
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Shared Memory
Message Passing
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Communication Primitives
System on Chip
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Shared memory is typical for bus-systems,
since naturally a memory is connected to the
bus that all processing entities can access
Memory
System on a chip
July 20, 2015
Microprocessor
Custom
Logic
(ASIC)
SoC Architecture
DSP
I/O
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Communication Primitives
Network on Chip
Switch
PE1
NI
NI
PE3
NI
MEM
Channel
PE2
NI
Network Interface
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Message passing looks very natural for networks-onchip, since a shared memory is usually not available
However, locality is important, since otherwise huge
amounts of data have to be sent over a network
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Message Passing
Message
P1
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P2
Processes send messages between processes
A message has a sender and and receiver(s)
Primitives are Send and Receive
Programming does not include a shared memory
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Programming Model for
Message Passing
A
C
Process
Receive Message
(Wait for message)
Send
Message
D
B
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Natural Model for NoCs: Communicating Finite State
Machines
Communication is done by message passing
(languages like SDL are suitable)
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Implementation of a Message
Passing Programming Model
 A programming model based on message
passing can still be implemented by a
shared memory architecture
 Each layer has to use the primitives that are
provided by their lower layer neighbour
Source Code
uses High-Level Comm. Primitives
Compiled Program
Operating System
uses Low-Level Comm. Primitives
uses Hardware Drivers
Mem
P1
P2
here Shared Memory Comm.
(can also be NoC)
Hardware
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Summary
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System-on-Chips are heterogeneous and
parallel
A good communication is the key to an
efficient parallel architecture
In the course we will mainly focus on
comunnication architectures
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July 20, 2015
Buses
Network-on-chip
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