Transcript Document

FE8113 ”High Speed
Data Converters”
Part 2: Digital background
calibration
Stewart Clark, ”Broken english spoken perfectly”
Papers 7 and 8
K.El-Sanakry, M.Sawan: “A New Digital Background Calibration Technique for
Pipelined ADC”, Proceedings of the 2004 International Symposium on Circuits
and Systems, 2004. ISCAS '04, Vol. 1, 23-26 May 2004, pp I-5 - I-8
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop
Residue Amplification”, IEEE Journal of Solid-State Circuits, Vol. 38, No.
12, December 2003, pp2040-2050
K.El-Sanakry, M.Sawan: “A New Digital Background Calibration Technique for Pipelined ADC”
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Outline:
 Compensation
of finite opamp dc gain
”By transforming the ADC to parallell ADCs and
measuring the gain ratios between different
configurations ...”
K.El-Sanakry, M.Sawan: “A New Digital Background Calibration Technique for Pipelined ADC”
Radix 2 and Radix <2 MDACs
K.El-Sanakry, M.Sawan: “A New Digital Background Calibration Technique for Pipelined ADC”
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If ratios G1,radix2/G2.radix2 and G1,radix<2/G2,radix<2 are known, x and A can
be computed
Calculation of finite dc gain & parasitics
K.El-Sanakry, M.Sawan: “A New Digital Background Calibration Technique for Pipelined ADC”
Calibration system, swaps between two gain configurations
It should be noted that
config 1 and config 2 refers
to different n on previous
slide, not different radix
M=2
Can be drawn as a time interleaved ADC
Calibration method
K.El-Sanakry, M.Sawan: “A New Digital Background Calibration Technique for Pipelined ADC”
TIADC Theory: Gain mismatch between two paths leads to inband
image at kfs/2 +- fin
The spectrum of digitized output Vgd of Vg is given by
Time-Interleaved Theory
K.El-Sanakry, M.Sawan: “A New Digital Background Calibration Technique for Pipelined ADC”
Choppes digitized output, multiplies with a small constant and integrate to
get an estimate of g1/g2. This ratio is used to modify g2 so the image
frequency dissapears. When the system has converged g1/g2 =
G1,radix2/G2,radix2
Repeated with different configuration to get G1,radix<2/G2,radix<2 Calibration System
K.El-Sanakry, M.Sawan: “A New Digital Background Calibration Technique for Pipelined ADC”
MADC Implementation
K.El-Sanakry, M.Sawan: “A New Digital Background Calibration Technique for Pipelined ADC”
Without Calib
With Calib
Unit
SNR
42
60.8
dB
ENOB
6.9
9.8
bits
SFDR
46
76
dB
Simulation results
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
Outline: A digital background calibration technique as
an enabling element to replace precision amplifiers
by simple powerefficient open-loop stages. At
Nyquist input frequencies, the measured signal-tonoise ratio is 67 dB and the total harmonic distortion
is 74 dB. The IC consumes 290 mW at 3 V and
occupies 7.9 mm2.
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
Based on: W. Yang, D. Kelly, I. Mehr,M. T. Sayuk, and L. Singer, “A 3-V 340mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input,”
IEEE J. Solid-State Circuits, vol. 36, pp. 1931–1936, Dec. 2001.
Architecture
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
Conventional closed loop
architecture is replaced
with an open loop
transconductance driving
a resistance
Conventional vs Open Loop
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
Assuming square law transistors and memoryless nonlinearities
VOV is gate overdrive, Δβ/β is current mismatch between transistors
Non-linearity model
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
With Vx-pp = 250mV, choose
VOV > 250mV to get low
second and fifth order
distortion. 3rd order distortion
is unavoidable and is
compensated for digitally.
Shown below is the equivalent
model
Offset in amplifier
Cubic distortion
Offset in SADC
Gain error in amplifier
Error model
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
Offset in SADC and DAC: extra redundancy in second stage
Gain error corrected using previously described techniques;
A. Karanicolas et al., “A 15-b 1-MSample/s digitally self-calibrated
pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, pp. 1207–1215,
Dec. 1993.
The new technique is the approach to cubic distortion correction
Through inversion of the of the
overall cubic polynomial with
gain compression (a3 < 0 )
Nonlinearity correction
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
Since the backend ADC quantize Vres1 the nonlinearity can be
corrected by operating on the backend code. This assumes that the
backend error, εb, is small.
Components of εb:
•
Linear and nonlinear or code dependent errors: must be kept small
by design
•
Static input-referred offset: comparator redundancy and digital
correction arithmetic
•
Quantization noise: two redundant bits
Backend ADC requirements
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
Switches between distinct overlapping residue functions. Digital
linearity correction operates on both residues (p2). Measure h1 and
h2 , if h1 = h2 then we have perfect adjustment of residues into
straight lines. If h1 > h2 we have incomplete nonlinearity error
cancellation.
Nonlinearity detection
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
Uses signal statistics to
determine h1 and h2. Requires
well behaved probability density
function. Generates cumulative
histograms for digital backend
conversion results
Nonlinearity estimation
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
Correction architecture
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
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Sub-DAC must be linear, nonlinearity only
present in gain stage
Needs a busy signal around which the distance
estimates (h1 and h2) is measured. Inactivity can
be detected, thus miscalibration can be avoided.
Activity spanning 1/16th of the fullscale range is
sufficient for calibration
Tradoff between accuracy and tracking speed of
LMS method
Calibration Limitations
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
Cascode devices used to improve PSRR
Pi-load used to decouple choice of common mode output level from differential gain requirements
Replica tail biasing used to improve CMRR
GmR replica bias reduce sensitivity to ambient temperature changes
1 Stage implementation
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
Murmann03
Yang01
Measured performence