CS 2204 Fall 2005
Download
Report
Transcript CS 2204 Fall 2005
CS 2204
Lab 7
Digital Logic
and
State Machine Design
As you wait for the lab to start :
Is your laptop up-to-date ?
Experiment 4
Spring 2014
Experiment 4 Lab 7 Outline
Presentation
Digital product development overview
Block partitioning
Implementing blocks
Using A Brief Look at Semiconductor Technology
From transistors to chips to multi-core microprocessor and walls
Analysis of the term project
Block 5 of the term project (using Term Project pages 30 - 38)
Analysis of Block 6 of the term project (using Term Project pages 38 - 48)
Implementing a machine player
A machine playing strategy
Individual work
Experiment 4
Develop the Rightmost Largest Display circuit, Macro 2, M2, of the
Ppm term project
Develop a new machine player that uses the Rightmost Largest Display
circuit
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 2
Developing a digital product
A new chip
Which gates/FFs and how many is determined by
The application (major operations)
Available components of the technology chosen
Besides speed, cost, power, etc. : Design goals
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 3
Developing a new chip
1) Development Cycle on Computers
DESIGN
TEST
MODIFY
Major error : Redesign
Major error : Redesign or terminate the project due to TTM
2) Development Cycle with FPGA chips
Mount
Test
Modify
Major error : Redesign or terminate the project due to TTM
3) Development Cycle on prototype chip
Fabricate
Test
Which components and how many ?
TEST : Apply input combinations, test
vectors, and simulate
During testing If you see MODIFYING
hardware to optimize it is possible, do
that after you correct logic and timing
errors. Then, test again to see if your
minimization has logic/timing errors
Mount : FPGAs are mounted on
bread/boards, wired and programmed
Test : apply test vectors to FPGAs
Modify : either FPGA mounting/wiring
is changed or a simple design change is
made on computers, simulated, then
FPGAs are programmed and tested
Fabricate chip by sending a GDSII file
to a fabrication facility : tape out
Apply test vectors to the chip
Chip
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 4
Development Cycle on Computers
Chip
1) Development
Cycle on Computers
From page 3 of the
Digital Product
Development Handout
DESIGN
TEST
MODIFY
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 5
Development Cycle on Computers
DESIGN a (sub) block
Chip
1) Input/Output Relationship of the (sub)block
DESIGN
TEST
MODIFY
Determine if it is a simple (sub)block
a)
A simple (sub)block
a)
A complex (sub)block
► If it is a combinational circuit with less than 5 inputs, obtain its truth
table, then move on to Implementation (2)
► If it is a sequential circuit where the sum of number of FFs and
inputs is less than 5, obtain its state diagram, then move on to
Implementation (2)
► Obtain the operation table or the operation diagram of the (sub)block,
then move on to Implementation (2)
2) Implementation of the (sub)block
Try to implement (sub)block by using steps on next three slides
•
•
If it can be implemented immediately, move to the TEST step
If it cannot be implemented immediately, partition it according to
the product goals and then move to (1) to implement the new
(sub)blocks
TEST
MODIFY
Try to use registers, counters,
shift registers even if it is a
simple sequential circuit
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 6
Development Cycle on Computers
Chip
DESIGN a (sub) block
2) Implementation of the (sub)block
i.
Zero, one or a few gates & FFs implement the (sub)block ?
•
If yes, draw the schematic and move to the TEST step
•
If yes, draw the schematic and move to the TEST step
If yes, draw the schematic, program the macros and move to the
TEST step
ii. One or more nonprogrammable Xilinx Design Blocks, XDBs or
Xilinx non-programmable macros (not gates nor FFs)
implement the (sub)block ? A few gates and FFs here and
there ?
CS2204
DESIGN
TEST
MODIFY
iii. One or more Programmable Xilinx macros implement the
(sub)block which is an unusual (sub)block ? A few gates and
FFs here and there ?
iv. Simple enough to be designed quickly using Switching Theory
(less than 5 inputs or less than 5 FFs+inputs) so a few gates
and/or FFs needed ?
•
If yes, draw the schematic and move to the TEST step
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 7
Development Cycle on Computers
DESIGN a (sub) block
2) Implementation of the (sub)block
v.
CS2204
Chip
The (sub)block can be licensed ?
•
If yes, borrow it, place it and move to the TEST step
•
Then we partition the (sub)block based on product goals
vi. If no to all the above questions, that means it is
impossible to implement the circuit immediately
► Application (major operations) : a (sub)block for each major
operation
► Design goals : speed, cost, power, size,…
Speed, cost, power,… depend on the technology
DESIGN
TEST
MODIFY
•
•
► Available components : components of the technology
See next few slides about partitioning
Then go back to Step 1 to design new (sub)blocks
During partitioning, think ahead and try to have most of the
new subblocks to be implemented by high density components
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 8
Development Cycle on Computers
DESIGN a (sub) block
2) Implementation of the (sub)block
Partition it into pieces based on major operations,
besides the design goals and the technology
•
•
•
DESIGN
TEST
MODIFY
Chip
One block for each major operation
These major operations are often additions, MUXings,
comparisons, decodings, encodings, DeMuxing,
registering, counting, etc.
► These operations are already implemented by available
components : ADDers, Multiplexers, Comparators,
Decoders, Encoders, DeMuxes, Registers, Counters, shift
registers, etc.
► This happens frequently for real-life applications
Sometimes there can be an Unusual Major Operation (an
unusual (sub)block)
► If it has < 11 inputs, maybe there is no need to partition !
► It can be implemented by using programmable components :
Memory components
ROMs, RAMs used as look-up tables
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 9
Development Cycle on Computers
DESIGN a (sub) block
2) Implementation of the (sub)block
Implement
Macro 2, M2
in Block 6
Chip
Partition it into pieces based on major operations, besides the
design goals and the technology
How can we
design
Macro 2, M2
in Block 6 ?
DESIGN
TEST
MODIFY
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 10
Development Cycle on Computers
DESIGN a (sub) block
Chip
2) Implementation of the (sub)block
DESIGN
TEST
MODIFY
Partition it into pieces based on major operations,
besides the design goals and the technology
•
Macro 2 has 16 inputs, 2 outputs and is also combinational
Macro 2
DISP
16
•
2 1 0
2
Input/output relationship : It outputs the position
number of the rightmost largest display in unsigned
binary
C 2 7 1 11
3
LRGDISPPOS
9 9 3 5 10
3
2 1 0
A F 4 F 00
3
2 1 0
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 11
Development Cycle on Computers
DESIGN a (sub) block
2) Implementation of the (sub)block
Chip
Partition it into pieces based on major operations, besides
the design goals and the technology
• How can we design Macro 2 ?
• Try to implement it :
i.
ii.
DESIGN
TEST
MODIFY
Zero, one or a few gates implement the macro ? NO !
One or more nonprogrammable Xilinx Design macros implement
the (sub)block ? NO !
iii. One or more programmable Xilinx Design macros implement the
(sub)block ? NO since it has 16 inputs !
iv. Simple enough to be designed quickly using Switching Theory ?
NO !
v. The (sub)block can be licensed ? We cannot do this !
vi. If no to all the above questions, that means it is impossible to
implement the circuit immediately !
It is an unusual operation with more than 11 inputs !
Then, we have to partition it based on its major operations
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 12
Development Cycle on Computers
DESIGN a (sub) block
Chip
2) Implementation of the (sub)block
How can we design Macro 2 ?
We have to partition it based on its major operations
Compare displays
Generate the number of the rightmost largest display
DISP
16
DESIGN
TEST
MODIFY
Compare
Displays
Generate
Number
LRGDISPPOS
2
Compare Displays has 16 inputs and determines the largest display
A few gates implement the macro ? NO !
Any Xilinx high density non/programmable component that
implements it ? NO !
It is an unusual operation with more than 11 inputs !
We need to partition it
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 13
Development Cycle on Computers
DESIGN a (sub) block
2)
Implementation of the (sub)block
4
PD1
4
PD2
4
PD3
4
Chip
Compare two sets of displays and select 2 larger displays
Compare the 2 larger displays
A
PD0
DESIGN
TEST
MODIFY
How can we partition Compare Displays ?
B
A
B
Compare
Displays 0 & 1 &
Select
Compare
Displays 2 & 3 &
Select
A<B
A
4
B
Compare
Larger
Displays
A<B
4
A<B
Compare Displays 0 & 1 &Select has 8 inputs and compares and selects the
larger of two displays
Few gates or Xilinx high density non/programmable component that implements it ?
NO ! It is an unusual operation with 8 inputs !
We decide to partition it because we realize a few nonprogrammable Xilinx components would
implement it immediately (so that we would not program 256 locations) !
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 14
Development Cycle on Computers
Chip
DESIGN a (sub) block
2)
Implementation of the (sub)block
How can we partition Compare Displays 0 & 1 & Select ?
Compare the two displays
Select the larger one
A
PD0
4
PD1
4
B
Compare
Displays
0&1
A<B
PD0
PD1
0
4
1
4
Select
Select
Larger
Display
4
Compare Displays 0 & 1 has 8 inputs and compares two displays
DESIGN
TEST
MODIFY
Few gates or Xilinx high density non/programmable component that implements it ?
YES ! It is a 4-bit unsigned binary compare operation !
We use a Xilinx 4-bit Unsigned Binary Comparator : COMPM4
Select Larger Display has 9 inputs and selects one of two 4-bit inputs
Few gates or Xilinx high density non/programmable component that implements it ?
YES ! It is a 4-bit 2-to-1 multiplexing operation !
We use a Xilinx 2-to-1 MUX : u74_157
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 15
Development Cycle on Computers
DESIGN a (sub) block
2)
Implementation of the (sub)block
How can we design Generate Number ?
•
It has 3 inputs and is combinational
A<B
a
Displays 0 & 1
A<B
b
Displays 2 & 3
A<B
c
Compare 2 Larger Displays
DESIGN
TEST
MODIFY
Generate
Number
LRGDISPPOS
2
Input/output relationship : We can obtain a truth table since it has
three inputs, by using the fact that it outputs the number of the
rightmost largest display in Unsigned Binary based on the three inputs
•
•
Chip
We notice that LRGDISPPOS1 is equal to a : No need for a component !
We also notice that LRGDISPPOS0 minterm list is the same as the 2-to-1
MUX minterm list !
Try to implement it
•
Any Xilinx high density non/programmable component that implements
LRGDISPPOS0 ?
YES ! A Xilinx 2-to-1 MUX : M2_1 to implement LRGDISPPOS0 !
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 16
Development Cycle on Computers
TEST a (sub) block
Catch logic and timing errors
Due to design or modification mistakes
Perform functional and timing simulations by applying test
vectors
Chip
Pick the right test vectors and the right order of them
•
Note down these combinations and output values to use them during later
testing steps
Does the test show that the (sub)block satisfies the product
goals ?
Input/output relationship, design goals, technology ?
If yes, go back to Step 1 to design another (sub)block
If all (sub)blocks are implemented and tested, then the Development
Cycle on Computers is over
If no, figure out the problem and then move to the MODIFY
step
If yes, check if there is a (sub)block to design
Test (sub)blocks separately
Combine (sub)blocks one at a time
DESIGN
TEST
MODIFY
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 17
Development Cycle on Computers
MODIFY a (sub) block
Correct logic and timing errors
Chip
If it requires a simple change, perform it
DESIGN
TEST
MODIFY
• After the change go back to the TEST step to make sure
the change is correct
If not a simple change, move one or more levels up to do
a repartition or redesign
• Repartition : One level up, two levels up,,,
• Redesign : All the way up (Project termination ?)
Optimize the circuit (which means additional
modifications) after you think your circuit does
not have logic and timing errors
After the optimization, move to the TEST step to make
sure the optimization does not introduce new logic and
timing errors
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 18
Developing a digital product
A new PCB
Which chips and how many is determined by
The application (major operations)
Available chips of the technology chosen
Besides speed, cost, power, etc. : Design goals
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 19
Developing a new PCB
1) Development Cycle on Computers
DESIGN
TEST
MODIFY
Major error : Redesign
Major error : Redesign or terminate the project due to TTM
2) Dev. Cycle with off-the-shelf chips
Mount
Test
Modify
Major error : Redesign or terminate the project due to TTM
3) Dev. Cycle on prototype PCB
Fabricate
Test
Modify
Which components and how many ?
TEST : Simulating by applying input
combinations, test vectors, may not be
possible. It may be coarse grain simulation
During testing if you see MODIFYING
hardware to optimize it is possible, do that
after you correct logic and timing errors.
Then, test again to see if your minimization
has logic/timing errors
Mount : Chips are mounted on
bread/boards and wired
Test : apply test vectors to the chips
Modify : chip mounting/wiring is changed
and tested or a simple design change is
made on computers, simulated, then chip
mounting/wiring is changed and tested
Fabricate PCB at a fabrication facility,
mount chips and other components
PCB
Apply test vectors to the PCB
Modify means chip mounting/wiring is
changed and tested
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 20
Development Cycle on Computers
PCB
1) Development
Cycle on Computers
From page 3 of the
Digital Product
Development Handout
DESIGN
TEST
MODIFY
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 21
Development Cycle on Computers
DESIGN a (sub) block
PCB
1) Input/Output Relationship of the (sub)block
DESIGN
TEST
MODIFY
Determine if it is a simple (sub)block
a)
A simple (sub)block
a)
A complex (sub)block
► If it is a combinational circuit with less than 5 inputs, obtain its truth
table, then move on to Implementation (2)
► If it is a sequential circuit where the sum of number of FFs and
inputs is less than 5, obtain its state diagram, then move on to
Implementation (2)
► Obtain the operation table or the operation diagram of the (sub)block,
then move on to Implementation (2)
2) Implementation of the (sub)block
Try to implement (sub)block by using steps on next three slides
•
•
If it can be implemented immediately, move to the TEST step
If it cannot be implemented immediately, partition it according to
the product goals and then move to (1) to implement the new
(sub)blocks
TEST
MODIFY
Try to use registers, counters,
shift registers even if it is a
simple sequential circuit
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 22
Development Cycle on Computers
PCB
DESIGN a (sub) block
2) Implementation of the (sub)block
i.
Zero, one or a few gates & FFs on zero, one or few SSI chips
implement the (sub)block ?
•
CS2204
If yes, draw the schematic and move to the TEST step
ii. One or more high density non-programmable
(ULSI/VLSI/LSI/MSI) chips implement the (sub)block ? A
few SSI chips with gates and FFs here and there ?
•
If yes, draw the schematic and move to the TEST step
iii. One or more Programmable (PLA/PAL/GAL/ROM/RAM/FPGA)
chips implement the (sub)block which is an unusual (sub)block ?
A few SSI chips with gates and FFs here and there ?
DESIGN
TEST
MODIFY
If yes, draw the schematic, program the macros and move to the
TEST step
iv. Simple enough to be designed quickly using Switching Theory
(less than 5 inputs or less than 5 FFs+inputs) so a few SSI
chips with gates and/orFFs needed ?
•
If yes, draw the schematic and move to the TEST step
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 23
Development Cycle on Computers
DESIGN a (sub) block
PCB
2) Implementation of the (sub)block
v.
CS2204
The circuit can be designed as a new chip ?
•
•
•
A risky process since we are designing a PCB
Time can be saved by licensing portions of the chip
If yes, borrow it, place it, design the chip and move to the TEST
step
vi. If no to all the above questions, that means it is impossible to
implement the circuit immediately
•
DESIGN
TEST
MODIFY
Then we partition the (sub)block based on product goals
► Application (major operations) : a (sub)block for each major operation
► Design goals : speed, cost, power, size,…
Speed, cost, power,… depend on the technology
► Available components : components of the technology
•
Then go back to Step 1 to design new (sub)blocks
During partitioning, think ahead and try to have most of
the new subblocks to be implemented by high density chips
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 24
Development Cycle on Computers
DESIGN a (sub) block
2) Implementation of the (sub)block
PCB
Partition it into pieces based on major operations, besides the
design goals and the technology
•
•
DESIGN
TEST
MODIFY
•
One block for each major operation
These major operations are often additions, MUXings,
comparisons, decodings, encodings, DeMuxing, registering,
counting, etc.
► These operations are already implemented by available
chips : ADDers, Multiplexers, Comparators, Decoders,
Encoders, DeMuxes, Registers, Counters, shift registers,
etc.
► This happens frequently for real-life applications
Sometimes there can be an Unusual Major Operation (an unusual
(sub)block)
► If it has < 11 inputs, maybe there is no need to partition !
► It can be implemented by using programmable components : Memory
components
ROMs, RAMs used as look-up tables
► If it has 11 to 20 inputs, implement it by using programmable chips
PLAs, PALs, GALs, FPGAs
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 25
Development Cycle on Computers
TEST a (sub) block
Catch logic and timing errors
Due to design or modification mistakes
Perform functional and timing simulations by applying test vectors
PCB
Pick the right test vectors and the right order of them
•
Note down these combinations and output values to use them during later
testing steps
Does the test show that the (sub)block satisfies the product
goals ?
Input/output relationship, design goals, technology ?
If yes, go back to Step 1 to design another (sub)block
If all (sub)blocks are implemented and tested, then the Development
Cycle on Computers is over
If no, figure out the problem and then move to the MODIFY step
If yes, check if there is a (sub)block to design
Test (sub)blocks separately
Combine (sub)blocks one at a time
DESIGN
TEST
MODIFY
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 26
Development Cycle on Computers
MODIFY a (sub) block
Correct logic and timing errors
PCB
If it requires a simple change, perform it
DESIGN
TEST
MODIFY
• After the change go back to the TEST step to make sure
the change is correct
If not a simple change, move one or more levels up to do
a repartition or redesign
• Repartition : One level up, two levels up,,,
• Redesign : All the way up (Project termination ?)
Optimize the circuit (which means additional
modifications) after you think your circuit does
not have logic and timing errors
After the optimization, move to the TEST step to make
sure the optimization does not introduce logic and timing
errors
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 27
Silicon Technology and Moore’s Law
Number of transistors on a chip doubles every two years
Because transistors are becoming smaller !
We will continue to shrink size of transistors !
We will continue to double the number of transistors
Vacuum tube
J. Bardeen, W. Brattain, William Shockley invented
first transistor at Bell Labs in 1947
J. Bardeen, William Shockley and W. Brattain,
received Nobel Prize in Physics in 1956
Transistors were mastered
in a decade replacing
vacuum tubes
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 28
Silicon Technology and Moore’s Law
Number of transistors on a chip doubles every two years
J. Bardeen, William Shockley and W. Brattain, invented
first transistor at Bell Labs in 1947
William Shockley formed Shockley Semiconductor
in Mountain View (Silicon Valley) in 1955
Transistors were mastered
in a decade replacing
vacuum tubes
Transistors were implemented by germanium, a semiconductor
Transistors are now implemented by silicon, another semiconductor
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 29
Silicon Technology and Moore’s Law
Number of transistors on a chip doubles every two years
William Shockley hired eight (8) bright
scientists to work with him in 1956
From left to right:
Gordon Moore,
C. Sheldon Roberts,
Eugene Kleiner,
Robert Noyce,
Victor Grinich,
Julius Blank,
Jean Hoerni,
Jay Last (1960)
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 30
Silicon Technology and Moore’s Law
Number of transistors on a chip doubles every two years
William Shockley‘s desire to work on diodes, not on bipolar transistors
and his style resulted in the resignation of the eight people in 1957
They formed a company called Fairchild Semiconductor in 1957
They set out to develop silicon planar transistors, basis for chips
Then, Silicon valley got its name and took off
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 31
Silicon Technology and Moore’s Law
Number of transistors on a chip doubles every two years
Jack Kilby
invented the
first chip at
Texas
Instruments
in 1958
He received a patent for the
first germanium-based chip
coined as miniaturized
electronic circuits in 1959
Jack Kilby received Nobel
prize in Physics in 2000
Robert Noyce developed
first silicon chip at Fairchild
Semiconductor in 1959
He received a patent for
the first silicon based chip
coined as silicon based
integrated circuit in 1959
Gordon Moore, founded
Intel with Robert Noyce
Gordon Moore, came
up with Moore’s Law
in 1965
Eugene Kleiner, a Poly graduate and
founder of one of the most successful
venture capital firms that funded
companies such as Intel, Amazon, Google,…
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 32
Microprocessors, Clock Frequencies, Power Consumption
Until 2005, microprocessors had one core and speed was improved by
shrinking size of transistors and increasing clock frequency !
The processor speed was increasing 50% a year !
But, memory speed has been increasing 10 % a year !
Power Wall !
Memory
(DRAMs)
Bus
Interface
In 2004 engineers could not
cool Intel Pentium@4GHz with
a fan even if it was CMOS
A core
Buses
Pentium4
Processor
L1, L2
Caches
In spring 2005 Intel and AMD introduced their first multi-core
microprocessor
But, IBM introduced the first multi-core microprocessor in 2001 and
then Sun Microsystems in 2002
Buses
Bus
Interface
Memory
(DRAMs)
Core
Core
Core
L1, L2, L3
Caches
Core
Multi-core
microprocessor
CMOS chips
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 33
Microprocessors, Clock Frequencies, Power Consumption
Power Density was Increasing Exponentially !
1000
Power was doubling every 4
years even for CMOS chips
Rocket
Nozzle
Watts/cm 2
Nuclear Reactor
100
Pentium® 4
Nanotubes will
cool chips
by circulating water
Pentium® III
Pentium® II
Hot plate
10
Pentium® Pro
Pentium®
i386
i486
1
1.5m
1m
0.7m
0.5m
0.35m
0.25m
0.18m
0.13m
0.1m
0.07m
Process Length
Courtesy : “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies” – Fred
Pollack, Intel Corp. Micro32 conference key note - 1999. Courtesy Avi Mendelson, Intel.
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 34
Multi-core Microprocessors
Intel Phi microprocessor (2012) : 62 cores 1 TFLOPS
1997 : Intel supercomputer with 9298 microprocessors (cores)
1 TFLOPS (1 Tera FLOPS)
1 TFLOPS = 1 x 1012 FLOPS
1,000,000,000,000 floating-point operations a second, FLOPS
1,000,000,000,000 real-number calculations a second
Number of cores per chip likely to double every two years
Microprocessor speed is NOT increasing 50% a year any more !
Microprocessor speed is increasing 30% a year
Memory is becoming a bottleneck
• More cores create more pressure on the memory
• The memory speed has been increasing 10% a year
• Memory wall !
Multiple cores are not used efficiently !
• Parallel Programming must improve
• Parallel Programming Wall !
Buses
Bus
Interface
Memory
(DRAMs)
Core
Core
Core
L1, L2, L3
Caches
Core
A multi-core
microprocessor
with 4 cores
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 35
Next 8-10 Years
Double number of cores every two years
Make sure to handle
errors due to
Alpha particles/
Neutrons
Defective transistors
Make sure to handle
Memory Wall
Power Wall
Intel Phi in 22nm process contains 62
cores and 5 billion transistors
Make sure to improve
Parallel Programming
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 36
Next 8-10 Years
Reconfigurable chips ?
FPGA chips
are on Mars !
FPGAs are becoming cost competitive with microprocessors
FPGAs are becoming speed competitive with custom chips
Latest FPGAs also have microprocessor cores to run software as well
FPGAs are now used for applications where speed and
programmability matter
Xilinx Virtex-II Pro
XC2VP4 FPGA die
From : Wei Wang,
University of Albany
IBM PowerPC 405 core
to run software
Hardware programmable
areas to perform
operations in hardware
CMOS chips
Xilinx Virtex-7 H580T
First 3-D heterogeneous FPGA chip
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 37
What are we looking for ?
Self-healing, adaptive, self managing,
trustworthy, dependable hardware and software
Efficient parallel processing
Hardware and software reliability
New computational models
New programming languages
So that we have
Many interconnected varying-size computing elements
using each other’s results autonomously
Ubiquitous computing with little human intervention
• Cloud computing to nano computing
Personal agents
Intelligent spaces
• Nano medicine
Smart drugs
Smart diagnosis
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 38
Analysis of the Term Project
Polytechnic Playing Machine, Ppm
The term project is human vs. machine
The black-box view
From the input devices
13
19
Ppm
To the output devices
Figure 1. The Ppm black box view.
From page 2 of the Term Project Handout
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 39
From page 8 of the Term Project Handout
LD0-LD2 on the
FPGA board
show the
current state
Ppm
Input/output
relationship
Ppm
operation
diagram
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 40
The Ppm Digital System Partitioning
From page 9 of the Term Project Handout
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 41
Points Calculation Block, Block 5
Has 47 inputs and 19 outputs
Calculates new points for the current player
Has only combinational circuits
47
Block 5
19
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 42
The Ppm Data Unit
Adjacency
Block 5, Points Calculation Block
Regular
Reward
Points
From page 31 of the
Term Project Handout
The game
is over
New
Player
Points
47
Block 5
19
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 43
The Ppm Data Unit
Block 5, Points Calculation Block
47
Block 5
19
Calculates the new points for the current player
There are several different ways to partition it, one of them
is based on the following major operations :
Determine the adjacency of the position played
• Adjacency Subblock : NSD
Determine the regular reward points of the position played
• Regular Reward Calculation Subblock : RWD
Determine new player points by adding the regular reward
points and the code reward points to the current player points
• Points Subblock : NPT, Ptovf
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 44
Block 5, Points Calculation Block
Adjacency
The partitioning
Regular
Reward
Points
New
Player
Points
The game
is over
47
Block 5
CS 2204 Spring 2014 Experiment 4 Lab 7
19
Page 45
Block 5, Points Calculation Block Development
Points Calculation Block partitioning
Adjacency
NSD
Adjacency
Subblock
Reward
Calculation
Subblock
Regular
Reward
Points
RWD
Points
Subblock
New Player Points
NPT
Total Reward Points
TOTRWD
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 46
Block 5, Points Calculation Block Development
Adjacency Subblock partitioning
Comparators
MUXes
1-bit ADDer
NSD
Adjacency
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 47
Block 5, Points Calculation Block Development
Regular Reward Calculation Subblock implementation
MUXes
RWD
2
NSD
4
BRWD
Regular Reward
Calculation Subblock
Core
8
Regular
Reward
Points
RWD
Figure 23. The Regular Reward Calculation Subblock.
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 48
Block 5, Points Calculation Block Development
Points Subblock partitioning
8-bit ADDers
MUXes
PT
NPT
TOTRWD
Ptovf
P1PT
P2PT
Selplyr
8
8
Select Player Points Subsubblock
8
PT
RWD
8
Core
The game is over
CODERWD
8
PT
8
Points Addition Subsubblock
Core
8
Ptovf
NPT
Figure 24. The Points Subblock partitioning.
CS 2204 Spring 2014 Experiment 4 Lab 7
New
Player
Points
Page 49
Machine Play Block, Block 6
How is it designed ?
Machine player gathers information and then decides
It must have inputs to gather information
• The number of inputs depends on the strategy
• But, a few inputs are required for some strategies
It must have outputs to be able to play the game
• The number of outputs depends on the strategy
• But, a few outputs are required for any strategy
?
Block 6
?
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 50
Machine Play Block, Block 6
How is it designed ?
Machine player gathers information and then decides
It must have a subblock to gather information
• Information gathering is a major operation
It must have a subblock to decide how to play
• Decision making is another major operation
Any other subblock (major operation) ?
?
Block 6
?
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 51
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
Machine player stays at least one clock period in state 4 to
gather information and decide
It stays more than one clock period if gathering information is
done sequentially
Because the information needed is not available all at once and so
must be collected one by one
Collecting information in parallel requires a lot of hardware !
•
The loop-back arrow indicates that more than once clock period is spent
in state 4
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 52
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
Machine player stays at least one clock period in state 4 to
gather information and decide
It stays more than one clock period if gathering information is
done sequentially
It collects the information in a number of clock periods and then in
one more clock period it plays
The course web site machine player is like that
•
It collects information for 8 clock periods and decides to play/skip in the
9th clock period !
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 53
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
The course web site machine player collects information for 8
clock periods and decides to play/skip in the 9th clock period !
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 54
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
Machine player stays at least one clock period in state 4 to
gather information and decide
It stays more than one clock period if gathering information is
done sequentially
We need a controlling major operation to determine the sequence of
information gathering and then deciding !
•
•
A controller subblock is needed in addition to the information gathering
and decision making blocks !
Since the machine player is a complex sequential circuit with a controller
then Block 6 is a tiny digital system itself
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 55
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
Machine player stays at least one clock period in state 4 to
gather information and decide
A controller subblock is needed in addition to the information
gathering and decision making blocks !
Since the machine player is a complex sequential circuit with a
controller then Block 6 is a tiny digital system itself
Block 6
Information
Gathering
Decision
Making
Sequencing
Data Unit
Control Unit
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 56
Machine Play Block, Block 6
The implementation at the course web site
70
Block 6
15
CS 2204 Spring 2014 Experiment 4 Lab 7
From page 40 of the Term Project Handout
Page 57
Machine Play Block, Block 6
The implementation at the course web site
Decision making
M2
Information gathering
Sequencing
M4
M3
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 58
Machine Play Block, Block 6
The implementation at the course web site
The inputs
P1PT is Player 1 points
P2PT is Player 2 points
RWD is the regular reward points
RD is the random digit
DISP is the four displays
NSD is the adjacency
R1D is the next random digit
BRWD is the digit played
CODERWD is the code reward points
PSEL indicates on which position
the current player played
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 59
Machine Play Block, Block 6
Means at least one of them must be used
The implementation at the course web site
The inputs
Means must be used
P2sturn is 1 when it is Player 2 to play
Stp2pt stores Player 2 points,
here used to increment a
counter to check if Player 2
has played 3 times or less
Clearp2ffs stores 0 on
registers, counters and
FFs after Player 2 plays
Clear stores 0 on registers,
counters and FFs after reset
Sysclk is the system clock at 6 Hz
P2clk is the Player2 clock at 48 Hz
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 60
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
It stays more than one clock period if gathering information is
done sequentially
The required inputs if it stays more than one clock period
Other inputs are needed to gather information
P2sturn
.
.
.
Block 6
Clearp2ffs
P2clk
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 61
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
Machine player stays at least one clock period in state 4 to
gather information and decide
If the information needed is available all at once, then the
machine player stays one clock period in state 4
It collects the information and decides to play/skip in one clock
period !
•
The loop-back arrow is not needed then !
Today’s machine player is a very simple one and so takes only one
clock period !
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 62
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
Machine player stays at least one clock period in state 4 to
gather information and decide
If the information needed is available all at once, then the
machine player stays one clock period in state 4
We do not need a controlling major operation to determine the
sequence of information gathering and then deciding !
•
•
A controller block is not needed in addition to the information gathering
and decision making blocks !
The machine player is a combinational circuit that gathers information
and decides how to play
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 63
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
Machine player stays at least one clock period in state 4 to
gather information and decide
If the information needed is available all at once, then the
machine player stays one clock period in state 4
Since the machine player is a combinational circuit, there are only
two subblocks in Block 6
Block 6
Information
Gathering
Decision
Making
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 64
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
The machine player stays one clock period in state 4
There is no required input if it stays one clock period
But, other inputs are needed to gather information
.
.
.
.
Block 6
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 65
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
How can the machine player indicate how it plays after
collecting information and deciding (taking one or more clock
periods) ?
It needs to have outputs to indicate its decision
If it decides to play the random digit
•
•
•
Output lines to indicate which position : P2SEL
An output line to indicate whether it is an addition or direct play : P2add
An output line to indicate that it is playing, not skipping : P2played
•
An output line to indicate it is skipping : P2skip
If it decides to skip
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 66
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
How can the machine player indicate how it plays after collecting
information and deciding (taking one or more clock periods) ?
It needs to have outputs to indicate its decision
The required outputs whether it stays one clock period or longer
•
Other outputs may be needed for the strategy, but not recommended
4
P2SEL
P2add
Block 6
P2played
.
.
P2skip
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 67
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
It needs to have outputs to indicate its decision
The required outputs whether it stays one clock period or longer
4
P2SEL
P2add
Block 6
P2played
.
.
P2skip
P2SEL has a 1 corresponding to the
position played when the machine
player plays the random digit
P2add is 1 if the machine player
adds the random digit to a display
P2played is 1 if the machine player
plays the random digit on a display
P2skip is 1 if the machine
player skips the plays
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 68
Machine Play Block, Block 6
The implementation at the course web site
The outputs
70
Block 6
15
The 7 required outputs to be
generated no matter what the
playing strategy is
P2CODE outputs the code
digits that are discovered
by the machine player
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 69
Machine Play Block, Block 6
The implementation at the course web site
The outputs
70
Block 6
15
P2CODE outputs the code digits
that are discovered by the
machine player
If the strategy does not check
for code digits, P2CODE outputs
must be connected zero to avoid
unnecessary warnings
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 70
Machine Play Block, Block 6
Let’s design a machine player slightly more complex than last
week’s machine player
To design it we must have a playing strategy !
We develop a machine player strategy then !
There is a zero display ?
N
Y
Play on the
(rightmost)
zero position
directly
(Action 1)
Play on the
(rightmost)
largest
position with
an addition
(Action 0)
?
A simple playing strategy !
Block 6
?
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 71
Machine Play Block, Block 6
Let’s design a machine player slightly more complex than last
week’s machine player
To design it we must have a playing strategy !
Let’s analyze the strategy
•
•
•
•
It always plays (it does not skip at all)
If there is a zero display, it plays on the zero display position directly
Otherwise (no zero display), it plays on the largest display position with an
addition
If two or more positions are equally playable, it plays on the rightmost of
these positions
There is a zero display ?
?
Block 6
N
?
Play on the
(rightmost)
largest
position with
an addition
(Action 0)
Y
Play on the
(rightmost)
zero position
directly
(Action 1)
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 72
Machine Play Block, Block 6
To design it we must have a playing strategy !
We develop a machine player strategy then !
There is a zero display ?
N
Play on the
(rightmost)
largest
position with
an addition
(Action 0)
Y
Play on the
(rightmost)
zero position
directly
(Action 1)
We need to collect only the display values : DISP
We input 16 bits : DISP 15 – DISP0
?
Block 6
?
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 73
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
Machine player stays at least one clock period in state 4 to
gather information and decide
If the information needed is available all at once, then the
machine player stays one clock period in state 4
The DISP lines are available all at once, so no need to have more than
one clock period
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 74
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
The DISP information is available all at once, and so the
machine player stays one clock period in state 4
We do not need a controlling major operation to determine the
sequence of information gathering and then deciding !
The machine player is a combinational circuit that gathers
information and decides how to play
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 75
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
The DISP information is available all at once, and so the
machine player stays one clock period in state 4
Block 6
Since the machine player is a combinational circuit, there are only
two subblocks in Block 6
Information
Gathering
Decision
Making
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 76
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
The machine player stays one clock period in state 4
DISP
It needs 16 DISP lines to be input
16
Block 6
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 77
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
How can the machine player indicate how it plays after
collecting information and deciding ?
It needs to have outputs to indicate its decision
The required outputs
•
•
•
•
P2SEL
P2add
P2played
P2skip
4
P2SEL
P2add
Block 6
P2played
.
.
CS 2204 Spring 2014 Experiment 4 Lab 7
P2skip
Page 78
Machine Play Block, Block 6
The machine player is active in state 4 to think and play/skip
The black box view of the machine player
4
DISP
16
Block 6
P2SEL
P2add
P2played
P2skip
We must also output 8 P2CODE
lines to avoid unnecessary warnings
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 79
Machine Play Block, Block 6
The design of the machine player that is completely
combinational
The partitioning of the machine player block
4
DISP
16
Information
Gathering
P2SEL
P2add
Decision
Making
P2played
P2skip
8
P2CODE
Block 6
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 80
Machine Play Block, Block 6
The design of the machine player that is completely
combinational
The Information Gathering Subblock
M2
16
DISP
M3
Information
Gathering
Already designed
2
LRGDISPPOS
Aposzero
2
ZERODISP
Already designed
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 81
Machine Play Block, Block 6
The design of the machine player that is completely
combinational
The Information Gathering Subblock
DISP
DISP
16
16
M2
M3
2
LRGDISPPOS
Aposzero
2
ZERODISP
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 82
Machine Play Block, Block 6
The design of the machine player that is completely
combinational
The Decision Making Subblock
LRGDISPPOS
2
P2SEL
P2add
Decision
Making
Aposzero
ZERODISP
4
2
P2played
P2skip
8
P2CODE
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 83
Machine Play Block, Block 6
Generating P2skip output
It never skips
P2skip is always 0
P2skip = 0
P2skip
0
LRGDISPPOS
2
P2SEL
P2add
Decision
Making
Aposzero
ZERODISP
4
2
P2played
P2skip
8
P2CODE
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 84
Machine Play Block, Block 6
Generating P2played output
It always plays
P2played is always 1
P2played = 1
1
LRGDISPPOS
P2played
2
P2SEL
P2add
Decision
Making
Aposzero
ZERODISP
4
2
P2played
P2skip
8
P2CODE
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 85
Machine Play Block, Block 6
Generating P2add output
It plays directly if there is a zero display
Otherwise, it plays with an addition
P2add is 1 when Aposzero is 0
P2add = Aposzero
Aposzero
LRGDISPPOS
P2add
2
P2SEL
P2add
Decision
Making
Aposzero
ZERODISP
4
2
P2played
P2skip
8
P2CODE
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 86
Machine Play Block, Block 6
Generating P2SEL outputs
P2SEL outputs depend on if there is a zero display
There are two choices for P2SEL lines
•
•
We need to select between these two choices
•
If there is a zero display, it plays on the rightmost zero display
position
If there is no zero display, it plays on the rightmost largest
display position
We need to use a MUX to select !
In general, if there are multiple actions that play the random
digit (Action 0, Action 1, etc.) then, the Decision Making
Subblock must have a MUX !
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 87
Machine Play Block, Block 6
Generating P2SEL outputs
P2SEL outputs depend on if there is a zero display
There are two choices for P2SEL lines
•
•
If there is a zero display, it plays on the rightmost zero display position
If there is no zero display, it plays on the rightmost largest display
•
We need to use a MUX to select !
We need to select between these two choices
We need a 2-bit 2-to-1 MUX !
ZERODISP1
ZERODISP0
LRGDISPPOS1
LRGDISPPOS0
Aposzero
B1
B0
A1
A0
2-bit
2-to-1
MUX
Y1
Y0
P2POSSEL1
P2POSSEL0
Sel
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 88
Machine Play Block, Block 6
Generating P2SEL outputs
P2SEL outputs depend on if there is a zero display
There are two choices for P2SEL lines
We need to select between two choices
•
We need to use a MUX to select !
•
The MUX outputs P2POSSEL lines
•
We need a 2-to-4 decoder !
We need a 2-bit 2-to-1 MUX !
We need to convert the 2-bit P2POSSEL lines to 4 P2SEL lines
Y3
P2POSSEL1
P2POSSEL0
I1
I0
Y2
2-to-4
Decoder
Y1
Y0
P2SEL3
P2SEL2
P2SEL1
P2SEL0
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 89
Machine Play Block, Block 6
Generating P2CODE outputs
P2CODE outputs are always zero
LRGDISPPOS
P2CODE7
0
P2CODE6
0
P2CODE5
0
P2CODE4
0
P2CODE3
0
P2CODE2
0
P2CODE1
0
P2CODE0
4
2
P2SEL
P2add
Decision
Making
Aposzero
ZERODISP
0
2
P2played
P2skip
8
P2CODE
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 90
Machine Play Block, Block 6
The design of the machine player that is completely combinational
The Decision Making Subblock
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 91
Machine Play Block, Block 6
The design of the machine player that is completely combinational
Information Gathering
Decision Making
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 92
Machine Playing Strategies
Teams have to come up with a primary playing
strategy before they can design their machine player
A playing strategy is shown as a graph and consists of
Conditions shown as ovals
• Game situations
Actions shown as rectangles
• Playing the random digit on a display
• Skipping the plays
The graph is NOT with respect to time
The graph is with respect to game situations !
Teams must also have to come up with a secondary
strategy to resolve game situations where the
primary playing strategy results in multiple playable
positions
• Can you calculate the IQ of the two machine players at the course web site ?
• What is your procedure and justification to calculate it ?
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 93
Playing Strategy of Player 1 of Ppmmvsm
Its Implementation
Play on the
(rightmost)
largest
regular
reward
position
(directly if
equal)
(Action 0)
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 94
A Machine Player Strategy
Its Implementation
Largest regular reward = 0 ?
N
Play on the
(rightmost)
largest
regular
reward
position
(directly
if equal)
(Action 0)
CS 2204 Spring 2014 Experiment 4 Lab 7
y
Skip
Page 95
A Machine Player Strategy
Are all displays zero and
the random digit is 0 ?
Displays RD P1PT
The play
440C
4
37 4 4 4 C
E233
1
145 F 2 3 3
FDDF
FDDF
0
19
0000
0
224 Skip
Largest regular reward = 0 ?
N
Y
Player 1 does not have
(64)10 or more points &
there is a position with a
zero and RD is not zero
N
Play on the
(rightmost)
largest
regular
reward
position
(directly
if equal)
(Action 0)
Skip
Y
Play on the
(rightmost)
zero
position
directly
(if equal)
(Action 1)
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 96
A Machine Player Strategy
Its Implementation
Largest regular reward = 0 ?
N
Y
Player 2 does not have (64)10 or more points &
there is a position with a zero and RD is not zero
N
Play on the
(rightmost)
largest
regular
reward
position
(directly
if equal)
(Action 0)
Skip
Y
Play on the
(rightmost)
zero
position
directly
(if equal)
(Action 1)
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 97
Playing Strategy of Term Project
Its Implementation
Decision making
Information gathering
Sequencing
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 98
Assignment by next lab
Make sure that you have completed Experiment 1,
Experiment 2 and Experiment 3
Your experiment will be collected and graded
The last day to submit Experiment 3 as a team is
March 14, 2014
The last day to submit Experiment 4 as a team is
March 28, 2014
It will be graded and returned by the following lab
Submit your Experiment 4 during a lab session !
Not during Open Lab Hours !
CS 2204 Spring 2014 Experiment 4 Lab 7
Page 99
Make sure you have the LABS account and see the S drive
Make sure you have installed WebPACK 12.4 on your laptop
Make sure you create a CS2204 folder on both
Read slides at the end to learn about the software, Project Manager,
Schematic design and other related topics
Do not leave the lab before your partners finish
► Help your partners
QUESTIONS ?
Continue
reading the
Term
Project
handout
Digital
Logic
and
State Machine Design
Think about
the machine
player
strategy
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 100
Today’s Individual Xilinx Work
We will continue to study (analyze) the term
project
We will develop the Rightmost largest display
circuit of the Ppm term project in Block 6, based
on our classroom discussions on it : Experiment 4
We will replace Macro 2 (M2) in Block 6 with our own
circuits
We will develop a machine player with one condition and
two actions
Help our partners complete today’s project
We will continue reading the Term Project
handout
Also read slides at the end
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 101
Today’s Individual Xilinx Lab Work
1. Open the ppm project in the exp3 folder
a) Open the Project Manager and then open
the Ppm project in the exp3 folder
b) Look at the six Ppm schematics
c) Enter the team information to the schematics if
it has not been entered
Save the schematic if the team information is entered
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 102
Today’s Individual Xilinx Lab Work
1.
Open the ppm project in the exp3 folder
d)
Make sure Experiment 1, Experiment 2 and Experiment 3 are completed
That is you have the following in Schematic 3 and a circuit in Schematic 6 on the next slide :
Experiment 1
And the next slide
Experiment 2
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 103
Today’s Individual Xilinx Lab Work
1.
Open the ppm project in the exp3 folder
d)
Make sure Experiment 1, Experiment 2 and Experiment 3 are completed
That is you have the following on Schematic 6 and a circuit on Schematic 3o n the previous slide :
Experiment 3
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 104
Today’s Individual Xilinx Lab Work
1.
Make sure Experiment 1, Experiment 2 and Experiment 3 are
completed
That is on the screen you have the following :
Experiment 1
Experiment 3
Experiment 2
Make sure your circuits follow the
Term Project Check List handout
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 105
Today’s Individual Xilinx Lab Work
1.
Open the ppm project in the exp3 folder
d)
Make sure Experiment 1, Experiment 2 and Experiment 3 are completed
If they are not complete finish the designs by studying
•
•
•
•
Lab 4 presentation for Experiment 1
Lab 5 presentation for Experiment 2
Lab 6 presentation for Experiment 3
So that eventually Block 3 and Block 6 look like as follows :
Experiment 1
Experiment 2
Experiment 3
Make sure your circuits
follow the Term Project
Check List handout
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 106
Today’s Individual Xilinx Lab Work
2. Submit the Experiment 3 project after deciding
whose project is the best to submit
Decide whose project on the team will be submitted
Block 3 and Block 6 must look like as follows :
Experiment 1
Experiment 2
Experiment 3
Make sure your circuits
follow the Term Project
Check List handout
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 107
Today’s Individual Xilinx Lab Work
2. Submit the Experiment 3 project after deciding
whose project is the best to submit
Fill out a Term Project Check List handout before signaling
to the TA
Block 3 and Block 6 must look like as follows :
Experiment 1
Experiment 2
Experiment 3
Make sure your circuits
follow the Term Project
Check List handout
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 108
Today’s Individual Xilinx Lab Work
3. Open the Ppm project in termproject
4. Look at the six Ppm schematics
5. Switch to schematic 6
6. Zoom into the mid left area, containing Macro 2
(M2)
7. Analyze the macro to determine how it is
used
This is a custom macro designed by the professor
It has two outputs that indicate the number of the rightmost
largest display position : LRGDISPOS
See Block 6 on next two slides
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 109
Today’s Individual Xilinx Lab Work
Ppm Schematic 6 of termproject
Macro 2
M2
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 110
Today’s Individual Xilinx Lab Work
Ppm Schematic 6
The rightmost largest position
is indicated by LRGDISPOS
If all positions are the
same, LRGDISPPOS is 00
If all positions are zero,
LRGDISPPOS is 00
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 111
Today’s Individual Xilinx Lab Work
8. Analyze the macro to determine how it is used
See the correspondence between the classroom
discussion and M2 inputs and outputs
Search for the inputs and outputs of the macro
Determine which components generate the inputs
•
DISP0, DISP1, DISP2, DISP3,…, DISP15
Determine which components use outputs
•
LRGDISPPOS1 and LRGDISPPOS0
•
•
•
•
Select the Nets mode
Select With Name
Enter Disp15 and then press Enter
The software will automatically switch to the first schematic
that has the wire and show the wire in yellow
To search for a wire click on Edit -> Find… or press Ctrl+F to
find the wire with a name
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 112
Today’s Individual Xilinx Lab Work
8. Analyze the macro to determine how it is used
Do a Hierarchy Push and notice that its implementation
cannot be shown by Xilinx
A window will pop up indicating that its internal structure
cannot be shown
Click on No to close the window
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 113
Today’s Individual Xilinx Lab Work
8.
Analyze the macro to determine how it is used
The macro is needed by the machine player strategy
If yes, it plays
on the rightmost
largest position
directly to lower
human player’s
reward points
It checks if
the random
digit is not
zero and the
largest regular
reward is less
than eight
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 114
Today’s Individual Xilinx Lab Work
8.
Analyze the macro to determine how it is used
The macro is needed by the machine player strategy
1) The random digit is not zero ?
and
2) The largest regular reward
points is less than 8 ?
If yes
It plays on the
rightmost
largest position
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 115
Today’s Individual Xilinx Lab Work
8.
Analyze the macro to determine how it is used
The macro is needed by the machine player strategy
In order to
determine which
position is the
rightmost
largest position,
it checks
LRGDISPPOS
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 116
Today’s Individual Xilinx Lab Work
9. By using Microsoft and Xilinx ISE create
exp4 from the exp3
Remember that we must create a new project
from an earlier one by using Microsoft and Xilinx
ISE
We will experiment with the Ppm schematics
10. Open the Ppm project in exp4
11. Look at the six Ppm schematics
If it has not been entered, place your team info
on the schematics
Save the schematic if you enter the team information
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 117
Today’s Individual Xilinx Lab Work
12. Draw the schematic of the macro on the left side in
schematic 6 by using classroom discussions and your design
You will implement the LRGDISPPOS1 and LRGDISPPOS0 outputs by
using as many Xilinx design blocks as possible and as few gates as
possible
First draw the complete schematic on a sheet of paper by using your
class notes
Compare your schematic with your partners’ and make sure the
schematic is correct before you start the design on your computer
Draw the schematic on your computer based on your design on the
sheet
•
•
•
You will use the Add Symbol button on the leftmost side (or Ctrl+M) to
get the component list
You will use the Add Wire button on the leftmost side (or Ctrl+W) to
draw wires
To rotate components right press ctrl-r
Note, wires cannot be rotated
But, by pulling from one end of a wire, it can be rotated !
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 118
Today’s Individual Xilinx Lab Work
12.
Draw the schematic of the macro on the left side in schematic 6 by
using classroom discussions and your design
Move up the M3 circuits developed last week to create space
Move the M3 circuits and the Subblock divider line to the left to create
additional space that will be needed for the Decision Making Subblock
Do not change the Decision Making Subblock circuit from last week yet !
Implement
Macro 2,
M2, in this
area
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 119
Today’s Individual Xilinx Lab Work
12. Draw the schematic of the macro on the left side in
schematic 6 by using classroom discussions and your
design
You will implement the LRGDISPPOS1 and
LRGDISPPOS0 outputs by using as many Xilinx
design blocks as possible and as few gates as
possible
Note that what is discussed in this presentation, i.e. block
partitioning mentioned on slides 4 through 18 must be
followed where we try to use as many available Xilinx
components as possible
M2 uses three Xilinx comparators and three Xilinx multiplexers
Note also that what is learned in designing M3 can be used for
M2
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 120
Today’s Individual Xilinx Lab Work
12. Draw the schematic of the macro on the left side in
schematic 6 by using classroom discussions and your design
Macro 2, M2
in Block 6
First draw the complete schematic on a sheet of paper by using your
class notes
How can we
design
Macro 2, M2
in Block 6 ?
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 121
Today’s Individual Xilinx Lab Work
12. Draw the schematic of the macro on the left side in
schematic 6 by using classroom discussions and your
design
First draw the complete schematic on a sheet of paper by
using your class notes
•
Macro 2 has 16 inputs, 2 outputs and is also combinational
DISP
16
•
2 1 0
LRGDISPPOS
2
Input/output relationship : It outputs the position number of the
rightmost largest display
C 2 7 1 11
3
Macro 2
9 9 3 5 10
3
2 1 0
A F 4 F 00
3
2 1 0
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 122
Today’s Individual Xilinx Lab Work
12. Draw the schematic of the macro on the left side in
schematic 6 by using classroom discussions and your design
First draw the complete schematic on a sheet of paper by using
your class notes
How can we design Macro 2 ?
Try to implement it
• Try to implement it :
i.
ii.
iii.
iv.
v.
vi.
A few gates implement the macro ? NO !
One or more nonprogrammable Xilinx Design macros implement the macro
? NO !
One or more programmable Xilinx Design macros implement the macro ?
NO since it has 16 inputs !
Simple enough to be designed quickly using Switching Theory ? NO !
The macro can be licensed ? We cannot do this !
If no to all the above questions, that means it is impossible to implement
the circuit immediately !
It is an unusual operation with more than 11 inputs !
Then, we have to partition it based on its major operations
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 123
Today’s Individual Xilinx Lab Work
12. Draw the schematic of the macro on the
left side in schematic 6 by using classroom
discussions and your design
First draw the complete schematic on a sheet of
paper by using your class notes
How can we design Macro 2 ?
We have to partition it based on its major operations
Compare displays
Generate the number of the right largest display
DISP
16
Compare Generate
Displays Number
LRGDISPPOS
2
Compare Displays has 16 inputs and determines the largest display
Few gates or a Xilinx high density non/programmable component
implements it ?
NO ! It is an unusual operation with more than 11 inputs !
We need to partition it
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 124
Today’s Individual Xilinx Lab Work
12.
Draw the schematic of the macro on the left side in schematic 6 by
using classroom discussions and your design
First draw the complete schematic on a sheet of paper by using your class
notes
How can we partition Compare Displays ?
Compare two sets of displays and select 2 larger displays
Compare the 2 larger displays
A
PD0
4
PD1
4
PD2
4
PD3
4
B
A
B
Compare
Displays 0 & 1 &
Select
Compare
Displays 2 & 3 &
Select
A<B
A
4
B
Compare
Larger
Displays
A<B
4
A<B
Compare Displays 0 & 1 &Select has 8 inputs and compares and selects the larger of two
displays
Few gates or a Xilinx high density non/programmable component that implements it ?
NO ! It is an unusual operation with 8 inputs !
We decide to partition it because we realize a few nonprogrammable Xilinx components would
implement it immediately (so that we would not program 256 locations) !
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 125
Today’s Individual Xilinx Lab Work
12.
Draw the schematic of the macro on the left side in schematic 6 by using
classroom discussions and your design
First draw the complete schematic on a sheet of paper by using your class notes
How can we partition Compare Displays 0 & 1 & Select?
Compare the two displays
Select the larger one
A
PD0
4
PD1
4
B
Compare
Displays
0&1
A<B
PD0
PD1
0
4
1
4
Select
Select
Larger
Display
4
Compare Displays 0 & 1 has 8 inputs and compares two displays
Few gates or a Xilinx high density non/programmable component that implements it ?
YES ! It is a 4-bit unsigned binary compare operation !
We use a Xilinx 4-bit Unsigned Binary Comparator : COMPM4
Select Larger Display has 9 inputs and selects one of two 4-bit inputs
Few gates or a Xilinx high density non/programmable component that implements it ?
YES ! It is a 4-bit 2-to-1 multiplexing operation !
We use a Xilinx 2-to-1 MUX : u74_157
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 126
Today’s Individual Xilinx Lab Work
12.
Draw the schematic of the macro on the left side in schematic 6 by
using classroom discussions and your design
First draw the complete schematic on a sheet of paper by using your class
notes
How can we design Generate Number ?
•
It has 3 inputs and is combinational
A<B
a
Displays 0 & 1
A<B
b
Displays 2 & 3
A<B
c
Compare 2 Larger Displays
LRGDISPPOS
2
Input/output relationship : We can obtain a truth table since it has three
inputs, by using the fact that it outputs the number of the largest display in
Unsigned Binary based on the three inputs
•
•
Generate
Number
We notice that LRGDISPPOS1 is equal to a : No need for a component !
We also notice that LRGDISPPOS0 minterm list is the same as the 2-to-1 MUX
minterm list !
Try to implement it
•
Few gates or a Xilinx high density non/programmable component that implements
LRGDISPPOS0 ?
YES ! A Xilinx 2-to-1 MUX : M2_1 to implement LRGDISPPOS0 !
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 127
Today’s Individual Xilinx Lab Work
12. Draw the schematic of the macro on the
left side in schematic 6 by using classroom
discussions and your design
You will implement the LRGDISPPOS1 and
LRGDISPPOS0 outputs by using as many Xilinx
design blocks as possible and as few gates as
possible
First draw the complete schematic on a sheet of paper
by using your class notes and Xilinx component figures
Compare your schematic with your partners and make
sure the schematic is correct before you start the
design on your computer
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 128
Today’s Individual Xilinx Lab Work
12. Draw the schematic of the macro on the left side in
schematic 6 by using classroom discussions and your design
First draw the complete schematic on a sheet of paper by
using your class notes
Then, draw the schematic based on your design on the
sheet
•
•
•
You will use the Add Symbol button on the leftmost side
(or Ctrl+M) to get the component list
You will use the Add Wire button on the leftmost side
(or Ctrl+W) to draw wires
To rotate components right press ctrl-r
Note, wires cannot be rotated
But, by pulling from one end of a wire, it can be rotated !
Label the wires (inputs and outputs) based on your
analysis in part (9)
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 129
Today’s Individual Xilinx Lab Work
12. Draw the schematic of the macro on the left side in
schematic 6 by using classroom discussions and your design
Label the components
•
•
•
•
•
•
We have to have a consistent way of labeling components
We have to label the components in one subblock and
then label the components in another subblock, sweeping
the subblocks from left to right and top to bottom
Therefore, we need to label the Information Gathering
Subblock components and then label the components in
the Decision Making Subblock
Relabel the 2-to-4 decoder as U305 and the inverter as
U306 in the Decision Making Subblock so that we will not
have duplicated labels
Label the components of M2 starting at U298
The last label of M2 implementation will be U303
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 130
Today’s Individual Xilinx Lab Work
12. Draw the schematic of the macro on the left side in
schematic 6 by using classroom discussions and your design
Label the components
•
Determine that there is no component label above the
highest label of Experiment 4 as of now which is U306 !
How can I search for a component in the schematics ?
•
•
•
•
To search for components click on Edit -> Find… or press Ctrl+F
to find the component with a label
Select the Instance mode
Select With Name
Enter a label number and then press Enter
Save the schematic
See modified Block 6 on the next slide
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 131
Today’s Individual Xilinx Lab Work
12. Draw the schematic of the macro on the left side in
schematic 6 by using classroom discussions and your design
Macro 2, M2,
implemented
The Decision Making Subblock
is the same as Experiment 3
for the time being !
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 132
Today’s Individual Xilinx Lab Work
13. Do a schematic check on the new design
The schematic check is to see if there
are simple errors to catch on all
schematics
Select Tools Check Schematic
• The Console panel will indicate that there
are no errors but six warnings
See the next slide
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 133
Today’s Individual Xilinx Lab Work
13. Do a schematic check on the new design
The schematic check is to see if there are simple errors
to catch on all schematics
Read the bottom portion of the Console panel for warnings and
correct them if there are any
We see that there are 6 warnings that is one extra warning
compared with Experiment 3
The new warning compared with Experiment 3 is LRGDISPPOS0 which
is not used yet since we have not modified the Decision Making
Subblock
Since we will use LRGDISPOS0 when the Decision Making Subblock is
modified, the warning is acceptable !
We will ignore the new warning and decide there is nothing to correct
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 134
Today’s Individual Xilinx Lab Work
13. Do a schematic check on the new design
The schematic check is to see if there are simple errors
to catch on all schematics
You might wonder how the project works if wires are not connected to
outputs nor inputs
• The Xilinx software integrates all the schematics during its
implementation
• If the wire names are the same, it would not matter where the
wires are placed, the software connects them internally
Schematic checks do not catch all the errors
That is why after the Schematic checks we have to
perform
Functional simulations
Xilinx IMPLEMENTATIONs
Timing simulations
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 135
Today’s Individual Xilinx Lab Work
14. Perform functional simulations on this macro in
schematic 6 to verify that it is working
Note that to do functional simulations, you must perform a
synthesis
You will see that there are 142 warnings, many of them new
due to copying this project from exp3
ReRun the synthesis so that you eliminate most of the new
warnings
There will be 72 warnings after the second synthesis
Note that at the end of Experiment 3 we had 68 synthesis
warnings
Three of the 4 new warnings are due to the three comparator
outputs not used in Macro 2 (U298, U299, U302)
The other new warning is due to LRGDISPOS0 that is not used
yet by the Decision Making Subblock
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 136
Today’s Individual Xilinx Lab Work
14.
Perform functional simulations on this macro in schematic 6 to verify
that it is working
You will confirm the input/output relationship of the macro
Select the wires as follows :
•
•
DISP as inputs
LRGDISPPOS1 and LRGDISPPOS0 as the two output lines
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 137
Today’s Individual Xilinx Lab Work
14. Perform functional simulations on this macro
in schematic 6 to verify that it is working
Use your operation table that was studied in the
classroom
You can start with the following values to simulate
See the next slide
•
•
•
•
•
•
DISP = FFEE LRGDISPPOS1 , LRGDISPPOS0 = ?
DISP = 1CAF LRGDISPPOS1 , LRGDISPPOS0 = ?
DISP = CCCC LRGDISPPOS1 , LRGDISPPOS0 = ?
DISP = 0100 LRGDISPPOS1 , LRGDISPPOS0 = ?
DISP = 9277 LRGDISPPOS1 , LRGDISPPOS0 = ?
Use other input combinations to test well
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 138
Today’s Individual Xilinx Lab Work
14.
Perform functional simulations on this macro in schematic 6 to verify
that it is working
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 139
Today’s Individual Xilinx Lab Work
14. Perform functional simulations on this macro in
schematic 6 to verify that it is working
Come up with other input combinations to test the macro
further
If you catch errors correct them on schematic 6
Before completing this step, make sure the circuit in
schematic 6 is beautified and the schematic is saved again
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 140
Today’s Individual Xilinx Lab Work
15. Modify the Decision Making Subblock to complete
the implementation of the new machine playing
strategy as explained on slides 71 to 92
Modify the Decision Making Subblock schematic
Draw the new schematic by following slides 83 to 92
•
•
•
Delete the inverter needed for P2skip and draw the new circuit
for P2skip by using slide 84
Delete the buffer needed for P2played and draw the new
circuit for P2played by using slide 85
Delete the GND component needed for P2add and draw the new
circuit for P2add by using slide 86
Label the inverter needed for the P2add output as U306
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 141
Today’s Individual Xilinx Lab Work
15. Modify the Decision Making Subblock to complete
the implementation of the new machine playing
strategy as explained on slides 71 to 92
Modify the Decision Making Subblock schematic
Draw the new schematic by following slides 83 to 92
•
•
Delete the input wires of the 2-to-4 decoder and draw new
wires so that they can be named as P2POSSEL0 and P2POSSEL1
Do not change the label of the 2-to-4 decoder which is U305
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 142
Today’s Individual Xilinx Lab Work
15. Modify the Decision Making Subblock to complete
the implementation of the new machine playing
strategy as explained on slides 71 to 92
Modify the Decision Making Subblock schematic
Draw the new schematic by following slides 83 to 92
•
•
•
•
•
Label the components
•
Use a u74_157 4-bit 2-to-1 MUX as a 2-bit 2-to-1 MUX to
generate the P2POSEL0 and P2POSE1 outputs
Remember that you implemented this MUX in Experiment 1 !
Make sure that the G input is connected a GND
The unneeded inputs are also connected GND !
Label the MUX as U304
The component labels in Block 6 are from U289 through U306
Beautify your circuits
Save the schematic
See modified Block 6 on the next slide
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 143
Today’s Individual Xilinx Lab Work
15.
Modify the Decision Making Subblock to complete the
implementation of the new machine playing strategy as explained on
slides 71 to 92
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 144
Today’s Individual Xilinx Lab Work
15. Modify the Decision Making Subblock to complete
the implementation of the new machine playing
strategy as explained on slides 71 to 92
Develop the new Block 6 schematic
Perform a schematic check
•
•
•
•
There will be 0 errors and 5 warnings
The 5 warnings are the same as Experiment 3
The LRGDISPPOS0 warning has been eliminated since it is used
in the Decision Making Subblock
Since all these five warnings are acceptable there is nothing to
correct
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 145
Today’s Individual Xilinx Lab Work
15. Modify the Decision Making Subblock to complete
the implementation of the new machine playing
strategy as explained on slides 71 to 92
Develop the new Block 6 schematic
Perform logic simulations
•
•
•
In order to do logic simulations, perform a synthesis
The number of synthesis warnings is 58
Comparing with Experiment 3 which had 68 warnings, we see
that
The 12 warnings associated with ADDers U148, U149 and
U150 in Block 4 are removed
The 3 warnings associated with ADDer U288 in Block 3
are removed
But, 5 warnings associated with the new Comparators and the MUX
in Block 6 are added to the Experiment 4 warnings list
Perform logic simulations to observe that the machine player
follows the playing strategy
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 146
Today’s Individual Xilinx Lab Work
16. Perform a Xilinx IMPLEMENTATION
•
Xilinx IMPLEMENTATION is required after a schematic
is changed
•
•
•
When we indicate IMPLEMENTATION we mean Synthesis,
Implement Design and Generate Programming File steps we
see on the Project Navigator window
Since we changed schematic 6 we have to do a Xilinx
IMPLEMENTATION
Xilinx IMPLEMENTATIONS are needed for three reasons
Catching more errors not discovered via schematic checks
and functional simulations as the software analyzes the
schematics
Catching even more errors by doing timing simulations
possible after the Xilinx IMPLEMENTATION
Creating a new bit file
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 147
Today’s Individual Xilinx Lab Work
16.
Perform a Xilinx IMPLEMENTATION
•
Xilinx IMPLEMENTATION maps the schematics to the
FPGA resources (CLBs and wires)
•
If the mapping is complete then there are no errors but
there can be warnings
• Mapping allows real components to be considered, hence
timing simulations
Xilinx IMPLEMENTATION consists of 3 major steps
•
•
Synthesis to translate the schematic to a netlist file after
converting the schematic to a VHDL file
Implement Design which consists of
• Translate, Map, Place & Route
Generate Programming File to generate the bit file
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 148
Today’s Individual Xilinx Lab Work
16. Perform a Xilinx IMPLEMENTATION
Click on Design Summary (out of date) to be able to see the
number of errors and warnings
Right click on Generate Programming File and select Rerun All
We will do the Synthesis, Implement Design and Generate Programming File
steps altogether
•
Even though we already did the synthesis, we will do it again to get
practice on this as we will do it many times
Wait until the IMPLEMENTATION completes
•
If it does not complete, it stops at one of the steps
We have to read the errors on the Design Summary panel
Once completed, there are no marks next to any one of the steps
just performed
See the Project Navigator window on the next slide
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 149
Today’s Individual Xilinx Lab Work
16. Perform a Xilinx IMPLEMENTATION
Perform a Xilinx IMPLEMENTATION
The Xilinx IMPLEMENTATION results in 60 warnings
•
•
•
The number of synthesis warnings is 58
The number of Place & Route warnings is 2
The slice utilization is 4%
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 150
Today’s Individual Xilinx Lab Work
16. Perform a Xilinx IMPLEMENTATION
For the current IMPLEMENTATION we will get
•
0 Errors
60 Warnings
4% Slice utilization
Read the warnings by clicking on 60 Warnings on the
Design Summary window
We often check Design Summary for the warnings and the
FPGA utilization
Most warnings we check are in the Synthesis section
The FPGA utilization is lower than expected if there are
errors or warnings that must be corrected
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 151
Today’s Individual Xilinx Lab Work
17. Perform timing simulations to observe the delays
Make sure that the machine player follows the playing
strategy
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 152
Today’s Individual Xilinx Lab Work
18. Download the Ppm project to the FPGA chip
and play the game and to verify that the
schematic works correctly
In order to test the circuit fast you can input
random digits directly to the machine player
After you play, when the state is 3, leave one of
switches SW7 – SW4 on to signal you will input the
random digit
Use switches SW3 – SW0 to select a random digit
value
Press push button BTN2 so the machine player starts
with the random digit you input
Turn off the signaling switch (one of SW7 – SW4)
before you press push button BTN3 to play
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 153
Today’s Individual Xilinx Lab Work
18. Download the Ppm project to the FPGA chip and play the game
and to verify that the schematic works correctly
In order to test the circuit the two conditions in the playing
strategy must be true
1.
2.
RD is not zero
The regular reward points is less than 8
3.
4.
5.
6.
7.
Player 2 cannot win the game with the current play
A code digit cannot be played
It is not the beginning of the game
Player 2 is ahead
There is no adjacency
•
In addition
Therefore, when testing the circuit make sure to do the following
a)
b)
In order for Player 2 to be ahead, you, as a human player, will skip the play
several times in the beginning
You will input non-zero random digits so that
There is no adjacency
The regular reward points is less than 8
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 154
Today’s Individual Xilinx Lab Work
18. Download the Ppm project to the FPGA chip
and play the game and to verify that the
schematic works correctly
If it does not work, inspect your circuit in Block
6 and correct the circuit
If you are sure your Experiment 4 circuit is
correct then
Copy your experiment 4 folder from the S drive to
your laptop
Make sure you refresh your memory about the
game rules and how to play the game
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 155
Today’s Individual Xilinx Lab Work
19. Ensure that all circuits related to
Experiment 1, Experiment 2 and
Experiment 3 are complete
Including
Component labels
Well drawn circuits
20. Help your partners complete today’s
project
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 156
Today’s Individual Xilinx Lab Work
21.
Submit your exp4 project once everyone
completes the design
If all the team members have finished the new machine
player design, they will decide whose project will be
submitted
Students will fill out a Term Project Check List handout
so that feedback can be given to them by the grading
TAs
Students will signal to a TA who will copy their project
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 157
Today’s Individual Xilinx Lab Work
22. Continue Reading the Term Project handout
Study and play the other two types of the Ppm
game to think more about the our machine
player’s strategy
Human vs. human : ppmhvsh
Machine vs. machine : ppmmvsm
•
Think about the playing strategy of the machine player that will
be designed
Also read slides at the end to learn about the
software, Project Manager, Schematic design and
other related topics
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 158
Understand Critical Wires
RD : 4 bits
The random digit
R1D : 4 bits
Next random digit
R2D : 4 bits
The random digit after next random digit
DISP : 16 bits
They represent the four position displays
In Hex
DISP15-DISP12 : The leftmost position display, PD3
DISP11-DISP8 : position display PD2, etc
NPDISP : 16 bits
The result of RD to each display digit
In Hex
NPDISP15-NPDISP12 : The leftmost position, PD3, value + RD
NPDISP11-NPDISP8 : Position display PD2 value + RD
NPSELDISP : 4 bits
Selects one of NPDISP display values
In Hex
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 159
Understand Critical Wires
BRWD : 4 bits
Basic reward
In Hex
The digit played and also minimum points earned
It is selected from RD or NPSELDISP
Based on how the player played : Directly or with an addition
Brwdeqz : 1 bit
BRWD is zero when it is 1
PDPRD : 4 bits
Display overflow bits after addition
Pdprd : 1 bit
The display overflow bit of the position played
Selplyr : 1 bit
The current player
If it is 0, it is the human player, otherwise, it is the machine
player
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 160
Understand Critical Wires
P1SEL : 4 bits
The position played by the human player
P2SEL : 4 bits
The position played by the machine player
PSEL : 4 bits
Position Select bits of current player
ENCPSEL : 2 bits
The number of the position played
EQ : 4 bits
The equality of the four displays to the digit played
NSD : 2 bits
The number of similar digits, i.e. the adjacency information of the
position played
RWD : 8 bits
The regular reward points calculated based on adjacencies
In Unsigned Binary
CODERWD : 8 bits
The code reward points calculated based on the code digits
In Unsigned Binary
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 161
Understand Critical Wires
P1PT : 8 bits
Player 1 points
In Hex
P2PT : 8 bits
Player 2 points
In Hex
PT : 8 bits
The points of the current player
In Hex
NPT : 8 bits
New player points for the current player
In Hex
Ptovf : 1 bit
The points overflow
if it is 1, the new player points is above (255)10
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 162
Understand Critical Wires
P1add : 1 bit
Player 1 adds when it is 1
P2add : 1 bit
Player 2 adds when it is 1
Add : 1 bit
The current player adds when it is 1
P1skip : 1 bit
Player 1 skips when it is 1
P2skip : 1 bit
Player 2 skips when it is 1
P1played : 1 bit
Player 1 has played when it is 1
P2played : 1 bit
Player 2 has played when it is 1
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 163
Understand Critical Wires
DISPSEL : 2 bit
Selects one of four values for displays
00 Selects position displays (displays that RD is played on)
01 Selects player points
10 Selects next two random digits
11 Selects discovered code digits
Add : 1 bit
Shows that the current player has selected to add
Stp1pt : 1 bit
Store Player 1 points
Stp2pt : 1 bit
Store Player 2 points
Grd : 1 bit
Signals to generate a new random digit
The random digit counter output is stored as P2RD while P2RD and
P1RD are shifted to generate the new P1RD and RD
Bpds : 1 bit
Blink one or all displays slowly
Bpdf : 1 bit
Blocks a display fast after a display overflow
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 164
Understand Critical Wires
Clear : 1 bit
Clear FFs, registers, counters, etc. during reset in Block 2, Block 4
and Block 6 so that it can play again
Clearp2ffs : 1 bit
Clears Player 2 FFs, counters and registers
Clff : 1 bit
Clears FFs in Block 2 so that the next player can play if there is no
overflow
S1 : 1 bit
State 1 where when it is 1, the Ppm is in state 1
P2sturn : 1 bit
Signals that Player 2 has the turn
It is 1 when the Ppm is in state 4
Sysclk : 1 bit
System clock of the operation diagram at 6 Hz
P2clk : 1 bit
The clock signal of Player 2 at 48 Hz
Rdclk : 1 bit
The random digit counter clock at 192 Hz
CS 2204 Spring 2014 Experiment 4 Lab 7 Page 165