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Cascading Dynamic Gates
 Dynamic gates rely on temporary capacitive storage,
while static gates have DC restoration.
 Except the above design issues, there is one major
catch that complicates the design of dynamic circuits:
straight-forward cascading of dynamic gates to create
multi-level logic does NOT work.
© Digital Integrated Circuits2nd
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Cascading Dynamic Gates
V
Clk
Mp Clk
Out1
Mp
Out2
In
In
Clk
Me Clk
Clk
Me
Out1
VTn
V
Out2
t
1) The arises because the outputs of each gate – thus the inputs of
the next gate – are all precharged to 1, which may cause
inadvertent discharge in the beginning of evaluation cycle.
2) Setting all inputs (to next gates) to 0 during precharge address
that concern. So, only 0  1 transitions allowed at inputs !
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Domino Logic – NMOS dynamic gate
with static inverter
Bleeder
device
Clk
In1
In2
In3
Clk
Mp
11
10
PDN
Me
Out1
Clk
Mp Mkp
Out2
00
01
In4
In5
Clk
PDN
Me
Additional advantage of introducing an inverter
(low impedance of gate, smaller delay)
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Why Domino? – like falling dominos
Clk
Ini
Inj
PDN
Ini
Inj
PDN
Ini
Inj
PDN
Ini
PDN
Inj
Clk
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Properties of Domino Logic

Only non-inverting logic can be implemented
 Since each dynamic gate has a static inverter

Very high speed
 Only H-L delay exists (L-H transition equal to 0)
 Input capacitance reduced – smaller logical effort
(since each fanout needs to connect to NMOS
only compared to static CMOS logic)
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Designing with Domino Logic
VDD
VDD
VDD
Clk
Mp
Clk
Mp
Out1
Mr
Out2
In1
In2
In3
PDN
PDN
In4
Can be eliminated?
Clk
Me
Clk
Me
All Inputs = 0
during precharge
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Footless Domino
VDD
Clk
VDD
Mp
Clk
Mp
Out1
0
0
Clk
Mp
Out2
1
0
In1
1
VDD
Outn
1
0
In2
1
0
In3
1
0
1
Inn
1
0
1) Without evaluation devices, when the first gate goes to
precharge, the second gate has to wait for In2 to get to 0
since it fights against the precharge, which takes two
inverter delays. More delay for later gates.
2) This also causes short circuit power consumption
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Differential (Dual Rail) Domino
Mp Mkp
Clk
Out = AB
1
Mkp
0
Clk
Mp
1
A
!A
0
Out = AB
!B
B
Clk
Me
Solves the problem of non-inverting logic,
similar concept as DCVSL
It is actually used in a few commercial microprocessors (like DEC
Alpha E series processors)!
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V DD
M1
V DD
M2
Out
A
A
B
B
Out
PDN1
PDN2
V SS
V SS
Both the logic and its inverse are simultaneously implemented
Differential Cascode Voltage Switch Logic (DCVSL)
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np-CMOS
Clk
Mp
11
10
In1
In2
PDN
Clk
Me
In4
PUN
Out1
In5
00
01
In3
Clk
Me
To other Clk
N-blocks
Out2
(to PDN)
Mp
To other
P-blocks
Only 0  1 transitions allowed at inputs of PDN
Only 1  0 transitions allowed at inputs of PUN
PDN can follow PUN and vice versa
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np-CMOS
 One dis-advantage is that P-blocks are slower than Nblocks due to low current driving strengths of PMOS
(equalizing the delay imply more area)
 May cause larger power consumption due to
differential logic
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Summary of logic styles
 We have discussed Static complementary, Ratioed,
Pass transistor and Dynamic logic styles
 Which one to use strongly depends on the following
factors: ease of design, robustness, area, power and
speed.
 No single style optimize all these metrics
 Current trend is towards an increased use of
complementary static CMOS logic style (somewhat due to
the use of design automation tools at logic design level
which requires that the logic be robust and complexity
problem). Also, static CMOS is more amenable to voltage
scaling.
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Future trends
 To use multiple threshold transistors, low threshold for
performance critical circuits and high-threshold for
leakage control.
 To dynamically adjust the threshold of transistor by
adaptively controlling the body effect.
 Voltage islands: different voltage at different blocks.
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Layout techniques
for complex gates
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Layout preference
 For layout density, it is desirable to realize NMOS and
PMOS transistors as an unbroken row of devices with
abutting source-drain connections and with gate
connections of NMOS and PMOS aligned.
 For this, it requires only a single strip of diffusion in
both wells.
 To achieve the goal, a careful ordering of input
terminals is necessary.
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Stick Diagrams for layout
Contains no dimensions
Represents relative positions of transistors
VDD
VDD
Inverter
NAND2
Out
Out
In
GND
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GND
A B
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Two Versions of C • (A + B)
A
C
B
A
B
C
VDD
VDD
X
GND
X
GND
Two strips of diffusion
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Layout planning using Euler Path
 A systematic approach has been developed to derive
the permutation of input terminals so that complex
functions can be realized by un-interrupted diffusion strips
that minimize the area.
 The approach has two steps, construction of logic
graph and identification of Euler paths.
 The logic graph of a logic function is a graph of which
the vertices are the signals of the network and the edges
are the transistors.
 An Euler path is defined as a path through all nodes in
the graph such that each edge is only visited once.
 The Euler paths for PDN and PUN must be the same in
order to use a single poly for each input signal
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Stick Diagrams
Logic Graph
A
j
X
C
C
B
X = C • (A + B)
C
i
A
i
X
B
VDD
j
B
A
B
C
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PUN
GND
A
PDN
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Consistent Euler Path
X
C
i
X
B
VDD
j
GND
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A
A B C
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OAI22 Logic Graph
A
C
B
D
X
D
X = (A+B)•(C+D)
C
D
A
B
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C
VDD
X
B
A
B
C
D
PUN
A
GND
PDN
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Example: x = ab+cd
x
x
c
b
VDD
x
a
c
b
VD D
x
a
d
GND
d
GND
(a) Logic graphs for (ab+cd)
(b) Euler Paths {a b c d}
VD D
x
GND
a
b
c
d
© Digital Integrated Circuits2nd (c) stick diagram for ordering {a b c d}
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Notes
 The above layout technique is for single finger
transistors.
 When it comes to one strip of diffusion but with each
transistor having multiple fingers, layout further
complicate and you may still be able to do so.
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Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Designing Sequential
Logic Circuits
Revised from Digital Integrated Circuits, © Jan M. Rabaey el
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Sequential Logic
Inputs
Outputs
COMBINATIONAL
LOGIC
Current State
Registers
Q
Next state
D
CLK
2 storage mechanisms
• positive feedback
• charge-based
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Naming Conventions
 In
our text:
 a latch is level sensitive
 a register is edge sensitive
 There
are many different naming
conventions
 For instance, many books call edgetriggered elements flip-flops
 This leads to confusion however
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Memory elements
 At high level , memory is classified as background memory
and foreground memory.
 Memory that is embedded into logic is foreground memory.
 Large amounts of centralized memory core is background
memory, which achieves higher area density through efficient
use of array structures.
 Here, we focus on foreground memory elements here.
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Latch versus Register

Latch
stores data when
clock is high or low

D Q
D Q
Clk
Clk
Clk
Clk
D
D
Q
Q
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Register
stores data when
clock rises or falls
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Latches
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Latch-Based Design
• N latch is transparent
when f = 0
• P latch is transparent
when f = 1
f
N
Latch
Logic
P
Latch
Logic
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Timing Definitions
CLK
t
tsu
D
D
thold
DATA
STABLE
Q
CLK
t
tc 2
Q
Register
q
DATA
STABLE
t
Tsetup: setup time is the time that data input D must be valid before
clock transition
Thold: hold time is the time that data input D must remain valid after
the clock edge
Tc2q: propagation delay of copying D to Q output
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Characterizing Timing
tD 2
D
Q
Clk
tC 2
D
Q
Q
Clk
Q
tC 2
Q
Latch
Register
C2Q with respect to clock, D2Q to input signal
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Maximum Clock Frequency
FF’s
f
tc2q + tp,comb + tsetup <= T
Clock period T must
accommodate the
longest possible delay
LOGIC
tp,comb
Also another constraint: tcd,reg + tcd,logic > =thold
tcd: contamination delay = minimum delay
This constraint ensures the input data of the sequential circuits is
held long enough after the clock edge and not modified too soon
by the new coming-in data
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Positive Feedback: Bi-Stability
Vi2
V o1
V i1
V o2
A
V i 2 = V o1
C
B
V i 1 = V o2
When the gain of inverter in transient region is larger than 1,
A & B are the only stable operating points, C is metastable.
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Meta-Stability
Gain should be larger than 1 in the transition region
Hence, cross coupling of two inverters results in a bistable
circuit, that is a circuit with two stable states. The circuit
serves as a memory, storing either a 1 or 0 (A or B)
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Bistable circuit
 In absence of triggering, a bistable circuit remains in a
single state (static memory as long as power is on). Another
common name for a bistable circuit is flip-flop
 A FF is only useful when there is a mean to bring it from
one state to the other one.
 Two approaches can achieve that:
 cutting the feedback loop, once the feedback loop is
open, a new value can be written. This is called
multiplexer based.
 Overpowering the feedback loop, by applying a trigger
signal at the input of the FF, a new value is forced into the
circuit by overpowering the previous stored value.
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Mux-Based Latches
Negative latch
(transparent when CLK= 0)
1
D
CLK
Q  Clk  Q  Clk  In
Q
0
Q
0
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Positive latch
(transparent when CLK= 1)
D
1
CLK
Q  Clk  Q  Clk  In
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