Transcript Lecture 2: CMOS and Manufacturing Process

Verilog HDL
in Low Level Design
From Logic gate level
To Transistor level design
By Theerayod Wiangtong
Electronic Department,
Mahanakorn University of
Technology
Outline



MOS revisit
Static CMOS combinational circuit
ASIC (Layout) design tools
MOS Structure
MOS Review

Transistor gate, source, drain all
have capacitance



I = C (DV/Dt) -> Dt = (C/I) DV
Capacitance and current determine
speed
MOS symbol
MOS Capacitor


Gate and body form MOS capacitor
Operating modes



Accumulation
Depletion
Inversion
polysilicon gate
silicon dioxide insulator
Vg < 0
+
-
p-type body
(a)
0 < V g < Vt
+
-
depletion region
(b)
V g > Vt
+
-
(c)
inversion region
depletion region
Terminal Voltages
Vg




+
Mode of operation depends on Vg, Vd, Vs
+
Vgs
Vgd
 Vgs = Vg – Vs
Vs
Vd
 Vgd = Vg – Vd
+
Vds
 Vds = Vd – Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminals
 By convention, source is terminal at lower voltage
 Hence Vds  0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
 Cutoff
 Linear
 Saturation
nMOS Cutoff


No channel
Ids = 0
Vgs = 0
+
-
g
+
-
s
d
n+
n+
p-type body
b
Vgd
nMOS Linear


Channel forms
Current flows from d
to s



Vgs > Vt
+
-
e- from s to d
Ids increases with Vds
Similar to linear
resistor
g
+
-
s
d
n+
n+
Vgd = Vgs
Vds = 0
p-type body
b
Vgs > Vt
+
-
g
s
+
d
n+
n+
p-type body
b
Vgs > Vgd > Vt
Ids
0 < Vds < Vgs-Vt
nMOS Saturation




Channel pinches off
Ids independent of Vds
We say current saturates
Similar to current source
Vgs > Vt
+
-
g
+
-
Vgd < Vt
d Ids
s
n+
n+
p-type body
b
Vds > Vgs-Vt
nMOS I-V Summary

I ds
Shockley 1st order transistor models




 



0
 V  V  V ds  V
 gs
 ds
t
2



2
V
gs
 Vt 
2
V gs  V t
cutoff
V ds  V dsat
linear
V ds  V dsat
saturatio n
Example
We will be using a 0.6 mm process
for your project





From AMI Semiconductor
tox = 100 Å
m = 350 cm2/V*s
Vt = 0.7 V
Ids (mA)

Plot Ids vs. Vds


2.5
Vgs = 5
2
1.5
Vgs = 4
1
Vgs = 3
0.5
Vgs = 0, 1, 2, 3, 4, 5
Use W/L = 4/2 l
  m C ox
0
0
Vgs = 2
Vgs = 1
1
2
3
4
5
Vds
 3.9  8.85  10
  350  
8
L
100  10

W
 14
W 
W
m A /V
  120

L
L


2
pMOS I-V


All dopings and voltages are
inverted for pMOS
Mobility mp is determined by holes



Typically 2-3x lower than that of
electrons mn
120 cm2/V*s in AMI 0.6 mm process
Thus pMOS must be wider to
provide same current

In this class, assume mn / mp = 2
Current-Voltage Relations
Long-Channel Device
Second Order Effect
ID versus VDS
-4
6
-4
x 10
VGS= 2.5 V
x 10
2.5
VGS= 2.5 V
5
2
Resistive Saturation
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
1
VGS= 1.5 V
0.5
VGS= 1.0 V
VGS= 1.5 V
1
0
0
VGS= 2.0 V
1.5
ID (A)
4
VGS= 1.0 V
0.5
1
1.5
2
2.5
0
0
VDS(V)
Long Channel
3: CMOS Transistor
Theory
0.5
1
1.5
VDS(V)
Short Channel
Slide 14
2
2.5
CMOS Inverter
N Well
VDD
VDD
PMOS
2l
Contacts
PMOS
In
Out
In
Out
Metal 1
Polysilicon
NMOS
NMOS
GND
4: DC and Transient
Response
Slide 15
Two Inverters
Share power and ground
Abut cells
VDD
4: DC and Transient
Response
Connect in Metal
Slide 16
CMOS Inverter as Switch
V DD
V DD
tpHL = f(R on.CL)
Rp
= 0.69 RonCL
V out
V out
CL
CL
Rn
V in 5 0
V in 5 V DD
(a) Low-to-high
(b) High-to-low
4: DC and Transient
Response
Slide 17
DC Response


DC Response: Vout vs. Vin for a gate
Ex: Inverter






When Vin = 0
->
Vout = VDD
When Vin = VDD ->
Vout = 0
In between, Vout depends on
VDD
transistor size and current
By KCL, must settle such that
Idsp
Vin
Vout
Idsn = |Idsp|
Idsn
We could solve equations
But graphical solution gives more insight
Transistor Operation


Current depends on region of
transistor behavior
For what Vin and Vout are nMOS and
pMOS in



Cutoff?
Linear?
Saturation?
DC Transfer Curve

Transcribe points onto Vin vs. Vout
plot
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
Vin2
Vin1
Vout
VDD
VDD
A
B
Vout
C
D
0
Vtn
VDD/2
Vin
E
VDD+Vtp
VDD
Operating Regions

Region
Revisit transistor operating regions
nMOS
pMOS
A
Cutoff
Linear
B
Saturation
Linear
C
Saturation
Saturation
D
Linear
Saturation
E
Linear
Cutoff
VDD
A
B
Vout
C
D
0
Vtn
VDD/2
Vin
E
VDD+Vtp
VDD
Beta Ratio



If p / n  1, switching point will
move from VDD/2
Called skewed gate
Other gates: collapse into
equivalent inverter V
DD
p
 10
n
Vout
2
1
0.5
p
 0.1
n
0
Vin
VDD
Noise Margins

How much noise can a gate input
see before it does not recognize the
input?
Output Characteristics
Logical High
Output Range
VDD
Input Characteristics
NMH
VIH
VIL
NML
Logical Low
Output Range
Logical High
Input Range
VOH
VOL
GND
Indeterminate
Region
Logical Low
Input Range
Logic Levels

To maximize noise margins, select
logic V levels at
out
VDD
 p/ n > 1
Vin
Vout
Vin
0
VDD
Logic Levels

To maximize noise margins, select
logic levels at

unity gain point of DC transfer
V
characteristic
out
Unity Gain Points
Slope = -1
VDD
VOH
 p/ n > 1
Vin
VOL
Vout
Vin
0
Vtn
VIL VIH VDD- VDD
|Vtp|
Delay Definitions

tpdr: rising propagation delay


tpdf: falling propagation delay


From input to rising output crossing VDD/2
tcdf: falling contamination delay


From output crossing 0.8 VDD to 0.2 VDD
tcdr: rising contamination delay


From output crossing 0.2 VDD to 0.8 VDD
tf: fall time


tpd = (tpdr + tpdf)/2
tr: rise time


From input to falling output crossing VDD/2
tpd: average propagation delay


From input to rising output crossing VDD/2
From input to falling output crossing VDD/2
tcd: average contamination delay

tpd = (tcdr + tcdf)/2
Delay Definitions
Delay Definitions
Delay Definitions
Simulated Inverter Delay


Solving differential
equations by hand is
too hard
SPICE simulator solves
the equations
numerically


Uses more accurate I-V
models too!
But simulations take
time to write
2.0
1.5
1.0
(V)
Vin
tpdf = 66ps
tpdr = 83ps
Vout
0.5
0.0
0.0
200p
400p
600p
t(s)
800p
1n
Outline



MOS revisit
Static CMOS combinational
circuit
ASIC (Layout) design tools
Static CMOS Circuit
1. At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vssvia a low-resistive path.
2. The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
3. This is in contrast to the
dynamiccircuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
Static Complementary CMOS
VDD
In1
In2
PUN
InN
In1
In2
InN
PMOS only
F(In1,In2,…InN)
PDN
NMOS only
PUN and PDN are dual logic networks
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by
its gate signal
NMOS switch closes when switch control input is
high
A
B
X
Y
Y = X if A an d B
A
X
B
Y
Y = X if A O R B
N M O S T ransi stors pas s a “strong” 0 b ut a “w eak” 1
PMOS Transistors
in Series/Parallel Connection
P M O S sw itch clo ses w h en sw itch con trol in p u t is lo w
A
B
X
Y
Y = X if A A N D B = A + B
A
X
B
Y
Y = X if A O R B = A B
PM O S Tr ans is tor s pas s a “s tr ong” 1 but a “w eak ” 0
Threshold Drops
VDD
PUN
VDD
S
D
VDD
D
0  VDD
VGS
S
CL
VDD  0
PDN
D
VDD
S
CL
0  VDD - VTn
CL
VGS
VDD  |VTp|
S
D
CL
Complementary CMOS Logic Style
Example Gate: NAND
Example Gate: NOR
Complex CMOS Gate
B
A
C
D
OUT = D + A • (B + C)
A
D
B
C
Standard Cells
N Well
VDD
Cell height 12 metal tracks
Metal track is approx. 3l + 3l
Pitch =
repetitive distance between
objects
Cell height is “12 pitch”
2l
In
Cell boundary
Out
GND
Rails ~10l
Standard Cells
VDD
2-input NAND gate
VDD
B
A
B
Out
A
GND
Stick Diagrams
Contains no dimensions
Represents relative positions of transistors
VDD
VDD
Inverter
NAND2
Out
Out
In
GND
GND
A B
Two Stick Layouts of !(C • (A + B))
A
C
B
A
B
C
VDD
VDD
X
X
GND
GND
uninterrupted diffusion strip
Connection label layout
VDD, VSS and Output Labels
Interconnected
CMOS Properties






Full rail-to-rail swing; high noise margins
Logic levels not dependent upon the relative
device sizes; ratioless
Always a path to Vdd or Gnd in steady state;
low output impedance
Extremely high input resistance; nearly zero
steady-state input current
No direct path steady state between power
and ground; no static power dissipation
Propagation delay function of load capacitance
and resistance of transistors
Switch Delay Model
Req
A
A
Rp
A
Rp
Rp
B
Rn
Rp
CL
Cint
A
Rn
A
Cint
A
NAND2
Rp
A
B
Rn
B
INV
CL
Rn
Rn
A
B
CL
NOR2
Input Pattern Effects on Delay
Rp
A
Rp

B
Rn
CL

Delay is dependent
on the pattern of
inputs
Low to high transition

B
both inputs go low

Rn

Cint
one input goes low

A

delay is 0.69 Rp/2 CL
delay is 0.69 Rp CL
High to low transition

both inputs go high

delay is 0.69 2Rn CL
Outline



MOS revisit
Static CMOS combinational circuit
ASIC (Layout) design tools
Layout




Chips are specified with set of masks
Minimum dimensions of masks
determine transistor size (and hence
speed, cost, and power)
Feature size improves 30% every 3
years or so
Normalize for feature size when
describing design rules
Transistor Layout
Tra n sisto r
3
5
2
1
CMOS Process Layers
Layer
Color
Well (p,n)
Yellow
Active Area (n+,p+)
Green
Select (p+,n+)
Green
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Contact To Poly
Black
Contact To Diffusion
Black
Via
Black
Representation
Intra-Layer Design Rules
S am e P otential
0
or
6
W ell
D ifferent P otential
2
9
P olysilicon
2
10
3
C on tact
or Via
H ole
3
2
S elect
3
M etal1
A ctive
2
2
3
4
Metal2
3
CMOS Inverter Layout
In
G ND
VDD
A
A’
O ut
(a) L ayout
A
A’
n
p- substrate
n
+
( b) C ross -S ection along A -A ’
p
+
F ield
O xide
Detailed Mask Views

n well
Six masks


Polysilicon

n+ Diffusion


p+ Diffusion

Contact
Metal
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Traditional Design tools
New Design tools
HDL
(Verilog)
Cadence Design Tools Example
QUESTIONS?
THANK YOU
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