Transcript Piranha: A Scalable Architecture Based on Single

Piranha: A Scalable Architecture Based
on Single-Chip Multiprocessing
Luiz A. Barroso et al. (Compaq Computer Corporation)
Presented by:
Nick Kirchem
Feb 13, 2004
Target and Motivation
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Commercial applications (databases, OLTP)
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Most important market for high performance servers
Data dependent computation (low ILP)
Little gained by complex multiple issue out-of-order
processors
Complexity of current processors
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Long design times
High development costs
Better use of transistors?
Project Goals
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Design a Chip Multiprocessing (CMP) System
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Integrate 8 simple processor cores on a single chip
Exploit thread-level parallelism instead of ILP
High performance, Low Cost
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Achieve superior performance on commercial
workloads
Small team, modest investment, short design time
Architecture Overview
Architecture Elements
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Simple Processors (500 MHz, In-Order)
No I/O capability on chip (separate I/O nodes)
Up to 1024 nodes in a system
Individual L1 Caches (64KB, 2-way set-assoc)
One Logical L2 Cache, interleaved, 1MB
Intra-Chip Switch
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Unidirectional crossbar
Transaction based, atomic transfers
Bandwidth ~3x memory bandwidth
Intra-Chip Cache Coherence
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MESI protocol
No Inclusion (1 MB aggregate L1, 1MB L2)
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But, L2 holds copy of L1 tags and state
(no snooping required at L1)
L1 filled directly from memory (L2 = victim cache)
Coherence handled by L2 controllers
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Can service request directly, forward to owner L1,
forward to protocol engine, obtain from Memory
Inter-Node Coherence
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Protocol Engines (microprogrammable controllers)
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Directory Storage
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Home: exports local memory
Remote: imports remote memory
Compute ECC at coarse granularity, use extra bits for directory
info  no memory space overhead
Directory granularity = 1 node (not individual processor)
Interconnect: I/O queues, router (point-to-point, 4 links)
No NAKs – avoid deadlock by sufficient buffering, and
guarantee forwarded requests can be serviced
Performance Evaluation
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OLTP and DSS workloads: TPC-B/D, Oracle database
SimOS-Alpha environment
Compared:
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Single Chip Evaluation
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Piranha (P8) @ 500 MHz and Full-Custom (P8F) @ 1.25 GHz
Next-generation Microprocessor (OOO) 1 GHz
OOO outperforms P1 (individual proc) by 2.3x
P8 outperforms OOO by 3x
Speedup of P8 over P1 = 7x
Multi-chip Configurations
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Four chips (only 4 CPUs per chip ?!)
Results show that Piranha scales better than OOO
Questions/Concerns
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Would the Piranha design be worthwhile if
there were a well-designed SMT processor
(with 4 or 8 threads)?
Reliability better or worse with multiple chips
per processor?
Power consumption?