Transcript Moore’s law and the Industry-University Eco

Probabilistic Logic in
CMOS (PCMOS)‡
Krishna V. Palemϯ
Kenneth and Audrey Kennedy Professor
Rice University
Director, Institute for Sustainable Nanoelectronics (ISNE)
Nanyang Technological University(NTU), Singapore
PCMOS Fabrication and Measurement Collaborators:
Pinar Korkmaz*, Kiat-Seng Yeo §, Zhi-Hui Kong §
* Intel Corporation, §School of Electrical and Electronic Engineering, Nanyang Technological University
‡ This work was supported in part by DARPA under seedling Contract F30602-02-2-0124 and an award from Intel Corporation to
Georgia Institute of Technology and by ISNE at NTU, Singapore
Ϯ This author was supported in part by the Moore distinguished faculty fellow program at the California Institute of Technology (2008)
and by the VISEN center at Rice University
* The work of this author was done as part of her PhD research at the Georgia Institute of Technology.
Outline
 Device variations and perturbations
 Current-day (deterministic) logics are no longer adequate
─
Designing computing systems using current day design methodologies based on
traditional logics are no longer possible
 The role of probability
 Expressiveness and succinctness
─
─
Probabilistic Boolean Logic(PBL)
Probabilistic CMOS(PCMOS) Technology
 The value of probabilistic design
 Exploit property of PCMOS
 In conjunction with value of information
─
Trade “quality” for “cost”
 Future directions
2
Impact
 A novel Probabilistic Boolean Logic(PBL)
 Validation of PBL through 0.18 μm CHRT(Chartered Semiconductor)
technology fabrication.
 Using PBL to implement a ultra-low energy Hyper-Encryption system
in CHRT
 205
times more efficient through the energy-performance product metric
over a conventional design
 Probabilistic arithmetic for ultra low energy signal processing
 A FIR used in H-264 realized with half the energy and negligible
performance degradation
─
Simulated using HSPICE and software models
3
Outline
 Device variations and perturbations
 Current-day (deterministic) logics are no longer adequate
─
Designing computing systems using current day design methodologies based on
traditional logics are no longer possible
4
The Impediments to Moore’s Law
 Decreasing feature size
 Shrinking design margins
 Static variations
 Channel length, width
 Threshold voltage
 Interconnect (depth of focus)
 Dopant fluctuation
Gate Length Variations*
Variations*
5
*Courtesy Dr Keith Bowman, Intel Corporation
Dynamic Variations as Impediments to Moore’s Law
Supply voltage variations*
Thermal noise (amplified)
Temperature variations
Other dynamic variations*
6
*Courtesy Dr Keith Bowman, Intel Corporation
Abstraction in Design
 Abstractions have been used to design and automate the design of
complex systems
Transistors
Truth tables
Logic circuits
Boolean
Formulae
Gates
y  (a  b).c
Technology
Structural Abstraction
7
Input
Output
0
1
1
0
Behavioral
Abstraction
An Ideal CMOS Inverter
 Corner case for an ideal deterministic inverter
 If Vin < Vdd/2, Vout = Vdd
Corner case as a “rule of thumb”
 If Vin > Vdd/2, Vout = 0
•Is invariant as the output is observed over time
•Strictly depends on the input
“Digital 0”
Vdd
Vin
“Digital 1”
Vout
0
An Ideal Inverter
8
Vdd
2
Vdd
Vout
Effect of Dynamic Variations on the “Rule of Thumb”
Transistors
Truth tables
Logic circuits
Vdd
Boolean
Formulae
Gates
y  (a  b).c
Vin
Input
Output
0
1
1
0
Structural Abstraction
Technology
Behavioral
Abstraction
If Vin < Vdd/2, Vout = Vdd
If Vin > Vdd/2, Vout = 0
Rule of Thumb
In the presence of dynamic variations
Transistors
Truth tables
Noise
Logic circuits
Vdd
+
Vin
Boolean
Formulae
Gates
?
?
?
y  (a  b).c
What is the rule of thumb in this case ?
9
?
Input
Output
0
1
1
0
Effect of Dynamic Variations on the “Rule of Thumb”(Contd.)
 What is the rule of thumb ?
Noise from the Dynamic variations
T1
T2
T3
Therefore, a single rule of thumb with
two cases does not capture essential
information
+
Vin
Noise Voltage
Vdd
Need to list many rules of thumb due to
“uncertainty” in the behavior of noise
At T1, If Vin + 0.40 <Vdd/2, Vout = Vdd
If Vin + 0.40 >Vdd/2, Vout = 0
Dropping many of these
cases can lead to loss of
essential information
At T2, If Vin + 0.52 <Vdd/2, Vout = Vdd
If Vin + 0.52 >Vdd/2, Vout = 0
At T3, If Vin + 0.60 <Vdd/2, Vout = Vdd
If Vin + 0.60 >Vdd/2, Vout = 0
Inefficient/Incorrect design
10
How do we model this uncertain behavior?
At T1, If Vin + 0.40 <Vdd/2, Vout = Vdd
Specification
independent of the
If Vin + 0.40of
>VPBL
dd/2, Vout = 0
Supply voltage
variations.
Influenced
onlyperturbation
by the statistics
particular
physical
•Captured
ofthrough
noise the
At T2, If V
in + 0.52 <Vdd/2, Vout = Vdd
If Vinprobabilistic
+ 0.52 >Vdd/2,parameter
Vout = 0
Thermal noise
At T3, If Vin + 0.60 <Vdd/2, Vout = Vdd
If Vin + 0.60 >Vdd/2, Vout = 0
Temperature
Variations
Model noise succinctly as a
probabilistic parameter
Rule of thumb that allows a probabilistic parameter is a
path to succinctness, which is a central part of achieving
efficiency for human designers
Transistors
Noise
Vdd
+
Vin
Probabilistic
Gates
X
Truth tables
Probabilistic
Boolean Logic
circuits
X
Probabilistic
Boolean
Formulae
X
Structural Abstraction
11
y  (a  b).c
?
Input
Output
0
1
1
0
Outline
 Device variations and perturbations
 Current-day (deterministic) logics are no longer adequate
─
Designing computing systems using current day design methodologies based on
traditional logics are no longer possible
 The role of probability
 Expressiveness and succinctness
─
Probabilistic Boolean Logic(PBL)
Lakshmi N. B. Chakrapani and Krishna V. Palem, "A Probabilistic Boolean Logic and its Meaning",
Rice University, Department of Computer Science Technical Report, No. TR08-05, June 2008.
Lakshmi N. B. Chakrapani, “Probabilistic Boolean Logic, Arithmetic and Architectures”,PhD Thesis,
Georgia Institute of Technology, August 2008.
12
Probabilistic Boolean Logic
x
x
 x
x
x
 x?
 Boolean Logic captures “rules of thumb” on input and output behaviors
(functionality)
 Probability captures “uncertainty”
 Operators are “correct” with a probability p

Input
Output
x Λp y
x
y
0
1
0
0
p
1-p
0
1
p
1-p
1
0
p
1-p
1
1
1-p
p
Operators are subscripted with p
 “Incorrect” with probability (1-p)
Λp (0≤p≤1)
 Thermal noise, power supply noise and other dynamic perturbations
 Does not depend on the source of perturbation
 Only on statistics of the source which determines p
13
The meaning of Probabilistic Boolean Logic
 Each probabilistic Boolean formula
 Is associated with a set of classical(deterministic) Boolean formulae
 The probability that F behaves like one of these Boolean formula
0
1
Formula F
0
1
Behaves like this 2 out of
3 times.
0
1
2/3
Probabilistic Conjunction
And like this 1 out of
3 times.
0
1
Associated set of Boolean formulae
14
Considering More Complex Formulae
 For two probabilistic Boolean formulae F and G
 If the underlying family of deterministic Boolean formulae F and G and their
probabilities are equivalent
─
F is equivalent to G
Consider the circuit representation of a probabilistic Boolean formula
Probabilistic De-Morgan’s Law
3/4
2/3

7/12
Formula F
Formula G
The obvious simplification
AND
NOT
P(OUT)
Correct
Correct
2/3* 3/4
Wrong
Wrong
1/3*1/4
OR
P(OUT)
Correct
7/12
Wrong
5/12
1/2
Correct
Wrong
2/3*1/4
7/12
1/12
1/12
1/6
5/12
Wrong
Correct
1/3*3/4
1/4
15
Properties of PBL
Probabilistic Distributivity
p1
X
y
z
a
z
x
≡ z
y
p2
Identities Preserved
c
b
Theorem: Probabilistic Boolean Logic is not distributive
Probabilistic Associativity
( (x1Vp x2) Vp ( x3Vp x4 ) )
( ( (x1Vp x2) Vp x3) Vp x4 )
Vp
Vp
Vp
x4
≡
Vp
x1
Vp
x3
x2
x1
Vp
x2
x3
x4
Theorem: Probabilistic Boolean Logic is not associative
16
Outline
 Device variations and perturbations
 Current-day (deterministic) logics are no longer adequate
─
Designing computing systems using current day design methodologies based on
traditional logics are no longer possible
 The role of probability
 Expressiveness and succinctness
─
─
Probabilistic Boolean Logic(PBL)
Probabilistic CMOS(PCMOS) Technology
S. Cheemalavagu, P. Korkmaz, K. Palem, “Ultra low-energy computing via probabilistic algorithms and
devices: CMOS device primitives and the energy-probability relationship,” Proc. Int. Conf. Solid State
Devices and Materials (SSDM), 2004.
P. Korkmaz, B. Akgul, K. Palem, L. Chakrapani, “Advocating noise as an agent for ultra-low energy
computing: probabilistic complementary metal-oxide-semiconductor devices and their characteristics,”
Japanese J. of App. Phys., April 2006.
Pinar Korkmaz, "Probabilistic CMOS (PCMOS) in the Nanoelectronics Regime", PhD Thesis, Georgia
Institute of Technology, December 2007
17
Effect of Dynamic Variations on the “Rule of thumb”
Consider the design flow again.
Truth tables
Transistors
Noise
Vdd
Probabilistic
Logic circuits
Probabilistic
Gates
+
Vin
X
X
Input
Probabilistic
Boolean
Formulae
X
y  (a  p b).q c
X
Output
0
1
0
1-p
p
1
p
1-p
Structural Abstraction
Behavioral
Abstraction
Technology
The previous section
This section
What do we have so far ?
18
CMOS Inverter as a Probabilistic Object
 Noise induced (energy) fluctuations
 Thermal
noise*
 Derive probability of error as a function of supply voltage
and noise magnitude
Vdd
Vin
Thermal
noise
Vn*
Probability of 1
being treated as 0
Vout
Vdd
2
“Digital 0”
Thermal
noise
distribution
Ideal
case case
Probabilistic

Probability of 0
being treated as 1
0
1 1  Vdd 
By symmetry whenp V
0
in1 =


p

 erf 

Probability of correctness

2 2
 2 2 
“Digital 1”

Vdd
Vout
Sum of areas
is equal to
the probability
of error = p(say)
*Projected to be a significant concern in future technology generations
*N. Sano, “Increasing importance of electronic thermal noise in sub-0.1m Si-MOSFETs,” IEICE Transactions on Electronics, vol.
E83-C, pp. 1203–1211, Aug.2000.
*L. B. Kish, “End of Moore’s law: thermal (noise) death of integration in micro and nano electronics”, Phys. Letters A, Vol. 305, 2002.
*H. Li, J. Mundy, W. Paterson, D. Kazazis, A. Zaslavsky, R.I Bahar, “Thermally-induced soft errors in nanoscale CMOS circuits”,
IEEE International Symposium on Nanoscale Architectures, 2007, pages 62—69
19
Validation through fabrication of a CMOS inverter
 CMOS 0.18  m 1-Poly 6-Metal technology from Chartered
Semiconductor (CHRT)
 Fabricated noise source: different values of resistors (60k, 600k, and
2M ohm)
 Measurement methodology
 Agilent
Technologies IC-CAP device modeling software
 HP 4142 source monitor unit
R
Output
swing
Area
(m2)
60K
1.4 V
645
600K
1.7 V
6225
2M
1.8 V
12403
20
Probabilistic CMOS inverter
output
For all three cases:
P= 0.5
Power = 665 uW at VDD = 1.8 V and CL = 20 pF
Varying probability of correctness
Can we control the probability of error ?

NSR and p relationship from fabricated data
p
2
1
Vout
0

V1
p

pˆ1  pˆ 2  pˆ 3
2
Vout
0
V2

V3
0.25
65nm, 90nm
1
V1  V2  V3
0
0.6
3
Vout
0
Sim.
0.5
0.5

p
Meas.
AMI 0.5
(yellow)
TSMC 0.25
IBM
1.5
NSR

0.7
p 0.8
0.9
1
Reduce error probability by
increasing Vdd
Law of Invariance: NSR uniquely determines the probability
parameter p independent of the Moore’s Law technology generation
21
Outline
 Device variations and perturbations
 Current-day (deterministic) logics are no longer adequate
─
Designing computing systems using current day design methodologies based on
traditional logics are no longer possible
 The role of probability in device abstraction
 Expressive and succinct
─
─
Probabilistic Boolean Logic(PBL)
Probabilistic CMOS(PCMOS) Technology
 The value of probabilistic design
 Exploit property of PCMOS
22
Efficient Designs Using Properties of PBL
 Encryption framework
 One
bit message m to be transmitted from A(sender) to B(receiver)
 List L of length , of n-bit Boolean functions
─
Such that Fi(0n) ≠ Fi(0n-11), where
 Choose
Sender &
Receiver
─
F  L (only last bit is different)
i
the kth function Fk randomly
most resourceintensive step of
the algorithm
Shared secret key k, 1  k  , exists between both A & B
Sender
 Encoded
bit c = Fk(0n-1m) and transmit c, L (m is the last bit)
Receiver
 Compute
Fk(0n), Fk(0n-11) compare with c
─
Retrieve m
List of  Boolean functions L
k
L
Attacker can listen to traffic
n-ary gate
0
0
A
Sender
c
c
B
Receiver
Only B knows which
function A used to
generate c from m
0
m
Yan Zong Ding, Michael O. Rabin, "Hyper-Encryption and Everlasting Security", Lecture Notes In Computer
Science; Vol. 2285, Proceedings of the 19th Annual Symposium on Theoretical Aspects of Computer Science, 2002
23
Compressing the Size of the Circuit through the Power of PBL
 Choose
─
the kth function Fk randomly
Shared secret key k, 1  k  , exists between both A & B
 Encoded
bit c = Fk(0n-1m) and transmit c, L (m is the last bit)
can be made less
resource-intensive
using PBL
0
0
0
0
0
0
0

0
α Boolean
functions
0
0
A useful transformation:
A circuit with probabilistic gates can be replaced with a family
of probabilistic inverters as inputs to a deterministic circuit.
A single PBL formula can be a compact representation of a family of Boolean functions
24
Compressing the Size of the Circuit through the Power of PBL
 Choose
─
the kth function Fk randomly
Shared secret key k, 1  k  , exists between both A & B
 Encoded
bit c = Fk(0n-1m) and transmit c, L (m is the last bit)
can be made less
resource-intensive
using PBL
1
0
1
1
0
0
0
0
0
0
0
α inputs
1
1
0
1
0
1
1
1
1
A deterministic circuit with
probabilistic inverters as its inputs
A deterministic circuit with many random inputs
25
The Hyper-Encryption Circuit
0
0
0
0
0
Corresponds to a subset
0
Different sets
of inverters
0
Series of
2n-to-1
Multiplexers
c
m
0
Tree of XOR gates
Encoding the ‘m’ bit
Secret Key ‘k’
Depending on the key choose an appropriate set
of inverters to the tree of XOR gates.
Basic blocks for the hyper-encryption algorithm using Probabilistic inverters
Probabilistic
Inverters
26
Implementing Hyper-encryption
32 Probabilistic Inverters as
Random Number Generators
32 bits
Probabilistic Inverter = Noise Source
+Noise Amplifier + CMOS inverter
     
32-to-1
Multiplexer
64 5-bit
Serial to
parallel
shift
registers
(secret
Key)
5 bits
to XOR
32 PCMOS Inverters



64-bit XOR
Other 63
32-to-1
Multiplexers
m
Block B
to XOR
Block B
Output = one encrypted bit per cycle
Technology Used: CMOS 0.18 m, 1-Poly 6-Metal technology from Chartered Semiconductor
27
Value of Probabilistic Design
A2
A1
PRNG based: (Energy * Performance )
Gain =
PCMOS based: (Energy * Performance )
For producing one
encrypted bit
*Simulated
~ 205X*
≥ ~≥10X*
B1 250nm technology
using TSMC
B2
measurement results
*Preliminary
Methodology
A1
A2
B1
B2
9.56 x10-8 Joules
3.13x10-6 sec
3.664 x 10-9 Joules
4x10-7 sec
PRNG
+ HE Block
Simulated
=0
• Everything else measured
28
Outline
 Device variations and perturbations
 Current-day (deterministic) logics are no longer adequate
─
Designing computing systems using current day design methodologies based on
traditional logics are no longer possible
 The role of probability
 Expressiveness and succinctness
─
─
Probabilistic Boolean Logic(PBL)
Probabilistic CMOS(PCMOS) Technology
 The value of probabilistic design
 Exploit property of PCMOS
 In conjunction with value of information
─
Trade “quality” for “cost”
29
Trading probability of correctness
Can we control the probability of error ?

p
1

Vout
0

Vdd1
p


2
1
Vdd2

2

p
3
Vdd1  Vdd 2  Vdd 3
Reduce error probability by
increasing Vdd

p

Does it cost us ? If so, how much ?
3
Vout
0

p p
Vout
0

Vdd3
30
The E-p relationship
Reduce error probability
through higher Vdd



p p
1
Vdd
Vin
Thermal
noise
Vout
R
Vn*
C

2

Vdd1  Vdd 2  Vdd 3
p
3
1 1
 V 
 erf  dd 
2 2  2 2 
1
2
E  E sw  CVdd
2
p
1
E  CVdd2
2
E1  E2  E3
E  4Cσ 2 inverf 2p  12
This relationship between Energy consumption and the probability of correctness can be
summarized as follows:
The First Law of PCMOS: In any technology generation (C) and constant noise magnitude (σ) the
switching energy (E) grows with p. The order of growth of E in p is asymptotically bounded below by an
exponential in p
Pinar Korkmaz, Bilge E. S. Akgul, Krishna V. Palem and Lakshmi N. Chakrapani, Advocating Noise as an Agent for Ultra LowEnergy Computing: Probabilistic CMOS Devices and Their Characteristics Japanese Journal of Applied Physics, SSDM Special Issue
Part 1, April 2006.
Stein, K.-U., “Noise-induced error rate as a limiting factor for energy per operation in digital ICs,” IEEE J. Solid-State Circuits, vol. 12,
pp. 527–530, Oct. 1977.
31
The Analytical E-p relationship
 Use the analytical model to develop a relationship between Energy and Probability of
correctness
18
14
12
10
8
6
4
2
0
0.7
0.75
0.8
0.85
0.9
0.95
1
Energy per switching step, fJ
16
CHRT 180 nm-analytical
p
1
0.84
2.2
0.9
4.5
0.98
A “Rule of thumb”
supporting a tradeoff
p
Energy-probability of correctness relationship (E-p) for an inverter
in 180nm CHRT technology
32
E(fJ)
Validation of the First Law
20
p
Energy
Vdd
Energy per switching step
(fJ)
18
180nm-Analytical
0.999
11
1.0
14
0.976
1.61
0.4
12
0.889
0.9
0.3
16
180nm-Simulated
PTM 32nm Analytical
PTM 32-nm Simulated
10
8
CMOS 0.18  m 1-Poly 6-Metal
technology from Chartered
Semiconductor (CHRT)
2.
Supply voltage is varied from 0.3V
to 1.8V
Inverter Load Capacitance = 286fF
6
4
2
0
0.773
1.
0.841
0.933
0.977
0.994
p
0.998
0.999
0.999
1
3.
Energy-probability of correctness relationship (E-p) for an inverter in CHRT 0.18m technology and Arizona
State University PTM 32 nm technology
33
Modeling the Filtering Effect of the Noise by
the PCMOS Inverter
Vdd
Noise
V*
n
Vin
1 1  V 
Basic Model p  1  p   erf  dd 
2 2  2 2 

Vout
C
The new model
 V

dd

p  0.5  0.5erf 
 2 2 
eq 


 eq    Tn



Vdd
 K1Tn  K 2

Vdd  Vth 





K1, K2, : parameters fitted
using simulations
Tn: maximum frequency
component of noise
 When the sampling frequency (or the maximum frequency component)
of the noise > the maximum switching frequency of the inverter
Noise is filtered by the inverter
 The analytically found p values are smaller than those that of the simulation results

Pinar Korkmaz, Bilge E. S. Akgul and Krishna V. Palem ,Analysis of Probability and Energy of Nanometre CMOS Circuits in
Presence of Noise, Electronics Letters, Vol. 43, Issue 17, Aug. 2007.
0.5
Extending To Other Gates
 The Energy-probability relationship of a CMOS-based switch can be
extended
 Consider
XOR gate
Vdd
Measured, Modeled Energy-probability of correctness relationship for a XOR gate
35
P
0.4
0.854
0.8
0.975
1.2
0.998
Effect of Parameter Variations
 Effect of channel length variation
 10% variation
25
1
0.9
0.18u-L
Energy per switching step, fJ
20
0.8
0.18u-L+10%
32nm-L
0.7
32nm-L+10%
15
0.6
0.5
10
0.4
0.3
5
0.2
0.1
0
0.6
0.65
0.7
0.75
0.8
p
0.85
0.9
0.95
1
0
1.05
Energy-probability of correctness relationship (E-p) for an inverter
for varying channel lengths
36
Outline
 Device variations and perturbations
 Current-day (deterministic) logics are no longer adequate
─
Designing computing systems using current day design methodologies based on
traditional logics are no longer possible
 The role of probability
 Expressiveness and succinctness
─
─
Probabilistic Boolean Logic(PBL)
Probabilistic CMOS(PCMOS) Technology
 The value of probabilistic design
 Exploit property of PCMOS
 In conjunction with value of information
─
Best Paper
CASES 2006
Trade “quality” for “cost”
•
The value of probabilistic design
Jason George, Bo Marr, Bilge E. S. Akgul and Krishna V. Palem, “Probabilistic Arithmetic and Energy Efficient Embedded Signal
Processing” Proceedings of the Intl. Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), Seoul,
Korea, October 23-25, 2006
Lakshmi N. B. Chakrapani, Kirthi Krishna, Lingamneni Avinash, Jason George and Krishna Palem, "Highly Energy and
Performance Efficient Embedded Computing through Approximately Correct Arithmetic", International conference on Compilers,
Architectures, and Synthesis for Embedded Systems, 2008.
Lakshmi N. B. Chakrapani, and Krishna Palem, “Probabilistic Arithmetic", Rice University, Department of Computer Science
Technical Report, TR08-85, October 2008.
37
The value of probabilistic design
Applications
Image Processing
8
Video decoding
1
f(x,y)
Primitives
FFT
Building Blocks
FIR
delay
adder
multiplier
7
8
9
10
11
Lossy Adder
Devices
Switches and basic gates
 Even a slight sacrifice of
probability of correctness
yields energy savings

a
b
carry-in
a
p
b
carry-in
carryout
p  0.99 to p  0.85 for
XOR gate
─ 10.6x reduction in
energy
 Use the First law to guide
the tradeoff
p
sum
38
H.264 Image Decoding using Probabilistic Design
Adders
Adder
S11 S10 S9
S8
S7
S6
MSB
S5
S4
S3
S2
S1
S0
Multipliers
LSB
FIR
2
1
3
Normal operation
Vdd
2.5
BIVOS
Uniform voltage scaling
0.9
0
11
10
9
8
7
6
5
4
3
2
1
0
Bit Error Rate
Bit Position
BIVOS
Uniform Voltage Scaling
0.18
Normal operation
0
11
10
9
8
7
6
5
4
3
2
1
Bit Position
 Probabilistic Biased Voltage Scaling or
BiVoS
39
FIR
0
Outline
 Device variations and perturbations
 Current-day (deterministic) logics are no longer adequate
─
Designing computing systems using current day design methodologies based on
traditional logics are no longer possible
 The role of probability
 Expressiveness and succinctness
─
─
Probabilistic Boolean Logic(PBL)
Probabilistic CMOS(PCMOS) Technology
 The value of probabilistic design
 Exploit property of PCMOS
 In conjunction with value of information
─
Trade “quality” for “cost”
•
The value of probabilistic design
 Future Directions
40
Probabilistic Design for Ultra-low energy devices
 Mobile Embedded
Devices
Cell Phone “Lite”
Collaborators:
1. Yeo Kiat Seng, NTU
2. Vincent Mooney, NTU
 Education
 Medical Prosthetics
A low power solar powered
visual device for educating in
rural areas with limited access
to electricity
Auditory and Visual
Prosthetic Design
High-Fidelity Video
and Graphics
Collaborators:
1. Al Barr, Caltech
Collaborators:
1. Jayanthi Sivaswamy
2. NGO - VIDAL
Collaborators:
1. Al Barr, Caltech
2. Danny Petrasek,Caltech
Perception based
design with a
neuro-biological
basis.
Perceptual
limitations
41
Putting It All Together - An Architectural Vision
 Substantial within-die variation is
Configurable Interconnect
expected in future architectures

Threshold Vth voltage variation is an
example
─
─
Storage for
variation
information
Variation is known only post manufacturing
Could result in upto 30% variation in speed1
Significant
 Ameliorate the effects of variations
 Design independent techniques (e.g Vth
variations)
─

Use
Store
information for
about
design
variation
dependent
techniques
Use mapping
like
information
design
on tofor
design
reconfigurable
independent
fabric
techniques
like adaptive
body biasing
Test “blocks” for speed and leakage
•
Use bidirectional adaptive body-biasing circuits to
compensate2
Design specific techniques (e.g ripple carry
adder)
─
Least
Slowest
Block
1
Use faster blocks for most significant bits
 What is an architecture amenable to such
techniques ?
Most
Fastest
Block
2
Significant
Slow3
Block
Logic
Blocksblocks
are
Reconfigured
which
tested comprise
to
chain
of
blocks to
adetermine
FIR filter their
implement
behaviors FIR
Collaborators:
1. Jim Meindl, Georgia Tech
2. Raghu Murali, Georgia Tech
Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Kesha varzi, and V. De. “Parameter variations and impact on circuits
and microarchitecture.” In ACM/IEEE 40th Design Automation Conference (DAC-03), pages 338–342, Anaheim, CA, June
2-6 2003.
1S.
J.W.; Kao, J.T.; Narendra, S.G.; Nair, R.; Antoniadis, D.A.; Chandrakasan, A.P.; De, V. “Adaptive body bias
for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage”, In IEEE
Journal of Solid State Circuits, pages 1396–1402, November 2002.
2Tschanz,
42