Transcript Slide 1

Enhanced
Standard
Interconnect
Performance
Parameters
Ertugrul Demircan, Judith Mueller
Freescale Semiconductor Inc.
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the
Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
Outline
• Introduction and Motivation
• SIPPs History
• ESIPPs Overview
• ESIPPs Sections
• Conclusions and Future Directions
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
Introduction
• Interconnect parasitic effects
•
•
are becoming more and more
important with new VLSI
technologies.
Interconnect delays are
comparable to transistor
switching delays.
Layout Parasitic Extraction is a
necessary part of design flows.
Detailed description of interconnect
for accurate models is needed.
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
Interconnect Trends
• Interconnect parameter
trends show a clear
increase in complexity.
 CMP effects due to local
and global density
variations.
60
50
40
Via
Dielectric
Metal
30
20
 Complex lithography
effects.
 Width/Space dependent
material properties, i.e.,
resistivity.
TM
10
0
1998
2001
2003
2005
2006
Number of parameters for interconnect
layers. (From several major LPE tool
documentations)
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
SIPPs History
• LPE tool support for technology development is increasingly more difficult
if there is not a standard format.
• A group of companies initiated discussions for a standard in 1998: SIPPs
(Standard Interconnect Performance Parameters):
Goal:
 Foundries provide process parameters characteristic for the design
 All circuit design tools must follow the SIPPs standard to ensure
accurate physical representation of IC processes that affect
interconnect performance.
Objective of standard:
 Tool independent,
 Provide information for electrically accurate description and
characterization,
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
SIPPs History
 Provide true physical representation of process layers,
 Flexibel yet consistent,
 Extensive to accommodate future process technologies.
• Si2 (Silicon Integration Initiative) took over responsibility for development.
• SIPPs was approved in September 2000 by participating companies.
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
SIPPs Overview
Adoption of SIPPs in the industry was not satisfactory.
Possible reasons are:
1. LPE tool vendors prefer to develop their own proprietary
formats.
> New enhancements cannot be rolled out quickly.
> Standard format can reduce competitive edge over other vendors.
2. Deficiencies with SIPPs format.
> Restrictive and unintuitive syntax. It would be desirable to write it in
a simple BNF (Backus-Naur Form) notation with little or no
exceptions.
> Recent developments in VLSI technologies is more suitable for a
modular format.
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
ESIPPs Motivation and History
• When did the activity start:
 2004 in the Crolles2 Alliance (Freescale, Philips, and
STMicrolectronics)
 Philips: Hans Van Walderveen, Branko Hoffmann,
 STMicoelectronics: Corinne Cregut, Jean-Paul Morin
• What are the features desirable for a new format:
 Simple syntax: User should not think how many parenthesis they have
typed 
 Keywords should be intuitive and easily extensible
 Module approach to reduce repetitions
 Need to be able to describe multiple backend stacks of a given
technology node
 Support for process variations and corner definitions
 Provide possible mask operations performed at LVS
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
ESIPPs Format
• ESIPPs format is comprised of four sections:
 PARAMETERS
> This section defines individual modules for each
dielectric/metal/substrate/via type layer and their parameters and
possible process variations
> Modules do not represent any position in the possible stacks
 OPTIONS
> Defines the backend stacks allowed for that technology
> Gives the order in which modules appear in the stack
 CORNERS
> Declares how many corners are given
> Defines the selectors for module parameters and their min/typ/max
values based on variations
 MASKS
> Defines BOOLEAN operations to create new layers that can be
used in module definitions
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
ESIPPs Introduction
• ESIPPs format uses only white-space and <EOL> (End of
Line) characters as delimiters.
• Tries to borrow ideas from SIPPs format for parameter names
and specifications.
It can be written in the EBNF form as:
<ESIPPs> ::=
<parameter_section>
<option_section>
<corner_section>
<mask_section>;
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
PARAMETER SECTION
• Section is defined
<parameter_section> ::= BEGIN PARAMETERS <EOL>
{<line>} END PARAMETERS <EOL>;
• Entries are defined in a single line parser syntax:
<line> ::= <module> <type> <element> <EOL>;
<module> ::= <text>;
<type> ::= metal | dielectric | substrate | via;
<element> ::= <parameter> <unit> <expression>;
<parameter> ::= <text>;
<unit> ::= <text>;
<expression> ::= <spec>|<T>;
<spec> ::= <S>|<F>|<N>|<R>;
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
Parameter Value Specifications
The important part of definition are the specifications:
 String value for the parameter
<S> ::= “S” <text>;
 Fixed value for the parameter with no variation
<F> ::= “F” <value>;
 Normal distribution
<N> ::= “N” <mean> <deviation>;
<mean>::=<value>;
<deviation>::=<value>;
 Range of values
<R> ::= “R” <min> <typ> <max>;
<min> ::=<value>;
<typ> ::=<value>;
<max> ::<value>;
 Table of fixed values
<T> ::= “T” {<value>};
<value> ::= <real>|<integer>;
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
Interconnect Parameters
• There are many parameters for
each layer type
• Most of them are taken from
SIPPs definition
• New parameters can be added as
long as the module definition
syntax is used.
• Metal:








Subtype: interconnect
Planarity, mask
Min_width, min_space
Thickness, thickness(w,s,d)
Edge_bias, edge_bias(w,s)
TCR, TCR(w)
Sheet_resistance, sheet_resistance(w)
Poly_contact_space, gate_width
• Dielectric:




Subtype: intra, inter
Planarity
Permittivity
Thickness, thickness(d)
• Substrate:







Subtype: base, oxide, diffusion
Planarity, mask
Min_width, min_space
Thickness, thickness(w,s,d)
Edge_bias, edge_bias(w,s)
TCR, TCR(w)
Sheet_resistance, sheet_resistance(w)
• Via:



TM
Min_width,min_space, min_length
Ressistance_per_via, resistance_per_via(area)
From_layer, to_layer
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
EXAMPLE: Parameter Section
BEGIN_PARAMETERS
NAME TYPE
PARAMETER
boxide
boxide
boxide
OD
OD
OD
OD
OD
PO
PO
PO
PO
PO
….
substrate
substrate
substrate
substrate
substrate
substrate
substrate
substrate
metal
metal
metal
metal
metal
thickness
k
planarity
min_spacing
min_width
r_sheet
thickness
planarity
min_spacing
min_width
r_sheet
tcr
thickness
UNIT
SPEC VALUE
um
NA
NA
um
um
ohm/sq
um
NA
um
um
ohm/sq
1/C
um
N
F
S
F
F
R
N
S
F
F
R
F
N
0.34
0.034
6.1
P
0.085
0.08
18
22
30
0.2
0.02
P
0.14
0.06
20
28
35
0.001
0.2
0.02
END_PARAMETERS
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
OPTION SECTION
Option section defines the possible backend options and the order they are
constructed from each module defined in the parameter section.
<option_section> ::= BEGIN OPTION<EOL>
{<option_line>}END OPTION<EOL>
<option_line> ::= <option_name> <step_name> <step_element><EOL>;
<option_name> ::= <text>;
<step_name> ::= <text>;
<step_element> ::= module <unit> “S” <module_name> | <parameter>
<unit> <expression>;
<module_name> has to be one of the modules defined in the parameter
section.
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
EXAMPLE: OPTION SECTION
BEGIN_OPTIONS
OPTION
NAME
9m4x3y1z
9m4x3y1z
9m4x3y1z
9m4x3y1z
9m4x3y1z
9m4x3y1z
9m4x3y1z
9m4x3y1z
9m4x3y1z
9m4x3y1z
…
boxide
OD
fox
gateox
PO
nit_spr
CON
con_bar
con_diel
M1
PARAMETER
UNIT
SPEC VALUE
module
module
module
module
module
module
module
module
module
module
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
S
S
S
S
S
S
S
S
S
S
END_OPTIONS
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
boxide
OD
fox
gateox
PO
nit_spr
CON
con_bar
con_diel
M1
CORNER SECTION
• Interconnect corners are critical for proper account of process
•
variations on system performance.
It should be a part of the interconnect parameter definitions in
order to be consistent.
EDA tools vendors increased
activity in this area.
Si2 is soliciting participation
in Statistical Static Timing
Analysis format.
TM
TYP
CMIN
CMAX
XTLK
DLY
Width
Typ
Min
Max
Max
Min
Thick
Typ
Min
Max
Max
Min
Resist
Typ
Max
Min
Min
Max
ILD
Thick
Typ
Max
Min
Max
Min
ILD k
Typ
Min
Max
Min
Max
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
EXAMPLE: CORNER
TYPE
SUBTYPE
PARA
RCTYP CMIN
CMAX
XTLK
DLY
via
via
thickness
typ
max
min
max
min
via
via
r_per_via
typ
min
max
min
max
metal
interconnect thickness
typ
min
max
max
min
metal
interconnect r_sheet
typ
max
min
min
max
metal
interconnect tcr
typ
max
min
min
max
dielectric inter
thickness
typ
max
min
max
min
dielectric inter
swthk
typ
max
min
max
min
dielectric inter
k
typ
min
max
max
max
dielectric intra
thickness
typ
min
max
max
min
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
MASK SECTION
• Mask section can be described
•
•
as a replication of LVS.
It is required in construction of
different layers needed for
tools that do not have LVS
capabilities.
For instance, gate and
interconnect poly layers may
need to be given separately for
some LPE tools.
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
Conclusions and Future Directions
• Increasing complexity in VLSI
•
•
•
•
technology is leading to more
number of parameters for
interconnect definition.
Different format for LPE tools will
cause difficulties in achieving
model accuracy and quick turn
around.
Process variation requirements
will make it even more
complicated.
ESIPPs is an example to
formulate a format using a proper
syntax based on a logical
grammar.
We are working on extending with
XML such that interconnect
parameters can be combined with
design rules.
TM
ESIPPs
Stack Constructor
Corner Constructor
Translator
LPE1
LPE2
LPE3
ESIPPs usage concept
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.