Transcript CMOS Technology Logic Circuit Structures

The Effect of Substrate-Coupled Noise
on the Design of SiGe BICMOS Circuits
for RF/Mixed-Signal Applications
• SC913 EE Design Project Description (summer 2002)
– “Substrate Noise Characterization Test Site”
•
•
•
•
•
•
•
•
Background on Substrate-Coupled Noise
MOSIS SiGe BICMOS Technology Options – IBM 5HP/6HP
Models and Layout Design Rules - SiGe Design Kit
Circuit Design in Cadence SpectreRF
Test Site Floorplan
Progress to Date
New Course in the Fall: RF/Analog IC Design Fundamentals (SC500)
Conclusions
R. W. Knepper
BBTalk, slide 1
SC913 EE Design Project: Substrate Noise
Characterization Test Site for SiGe BICMOS
•
Project Description:
– Design a test chip in SiGe BICMOS technology to characterize substrate-coupled noise in
a RF/analog/digital mixed-signal environment
• Digital CMOS drivers and/or NPN bipolar drivers to generate a controlled amount of substrate
bounce
• Sensitive RF and analog circuit behavior (failure and/or degradation) based on the number of
drivers switching at one time
• Study various substrate contact and guard ring structures at different distances to isolate analog
circuits from digital noise sources
• Single devices, transmission lines, wire coupling, and substrate contact structures for S parameter
measurements using on-chip probing
– Utilize MOSIS facility and IBM’s 6HP SiGe process to fabricate the test site via an
unfunded research MEP proposal
– Characterize chip in Fall or Spring semester when hardware is received
• Obtain RF probe station and network analyzer setup for on-chip testing
• Utilize high frequency scopes and bench test equipment for PGA packaged chips
•
Students:
– 12-13 ECE graduate students with various levels of participation
R. W. Knepper
BBTalk, slide 2
Students Participating on SC913 Project
•
•
•
•
•
•
•
•
•
•
•
•
•
Aspiyan Gazder
Yuchun (Justin) Liao
Andrew McKnight
Marianne Nourzad
Jing Wu
Raman Mathur
Sulakshana Pasnoor
Chien-Chih Huang
Soma Ghosh
Zibing Yang
Christian Karl
Fangyi Chen
Duk Joung Kim
R. W. Knepper
BBTalk, slide 3
IBM PRML Magnetic Recording Channel IC
•
IBM PRML magnetic recording chip, circa
1991, shown at top-left
– P+ substrate with P- epi layer
– All necessary analog and digital circuitry
except for read head pre-amp (27 MHz)
•
•
Digital CMOS logic coupled noise into 6bit A/D converter on chip
6-bit Flash A/D converter shown at
bottom-right
– Resistor ladder network
– Differential noise problem on the
ladder network experienced
Verghese, Schmerbeck, and Allstot, “Simulation Techniques and Solutions
For Mixed-Signal Coupling in Integrated Circuits”, Kluwer, 1995
Also, Verghese’ PhD Thesis, CMU, 1995
R. W. Knepper
BBTalk, slide 4
IBM PRML Magnetic Recording Channel IC
•
Common mode noise observed on
PRML magnetic disk head chip in
A/D converter resistor ladder
network (left-top)
•
AGC output with (right) and
without (left) digital logic
switching
Circuit techniques were used to
reduce the ADC error to less than
½ LSB
•
Verghese, Schmerbeck, and Allstot, “Simulation Techniques and Solutions
For Mixed-Signal Coupling in Integrated Circuits”, Kluwer, 1995
Also, Verghese’ PhD Thesis, CMU, 1995
R. W. Knepper
BBTalk, slide 5
Texas Instruments A/D Converter TVP5700
•
Triple 8-bit semiflash pipelined video A/D
converter by TI (left-top) continued to
have substrate noise problem after 3
design attempts
– Severe sparkle code error causing DNL
error above +/- 1 LSB
•
•
•
Twelve output buffer cells switching
simultaneously coupled excessive noise
into the P+ substrate
Verghese’s PhD substrate modeling
methodology was used to extract substrate
model
Circuit schematic of one output buffer and
ESD circuitry shown (bottom-left)
– Coupling through bonding pad
capacitance and M12 transistor
– Separate Digital VSS and Analog VSS
with wire/pin inductance values shown
– Extracted substrate resistances shown
TVP5700 – Triple 8-bit Video analog-to-Digital Converter,
Product Review, Texas Instruments Inc., April 1994.
Also, Nishath Verghese’ PhD Thesis, CMU, 1995
R. W. Knepper
BBTalk, slide 6
Texas Instruments A/D Converter TVP5700
• Simulation of ADC output and
coupled substrate noise shown at
top-left (prior to design fixes)
• Use of extracted substrate model
allowed design choices to be made
to alleviate the noise problem
– Routing N-wells under bonding
pads and clock lines
– Reducing lead inductance of DVSS
and DVDD lines
– Resistively damped DVSS and
DVDD lines
– Stagger the driver switching times
to reduce delta-I noise
• Simulation of ADC output and
coupled substrate noise after the
design fixes were made is shown at
bottom-left
– Tremendous improvement in noise
TVP5700 – Triple 8-bit Video analog-to-Digital Converter,
Product Review, Texas Instruments Inc., April 1994.
Also, Nishath Verghese’ PhD Thesis, CMU, 1995
R. W. Knepper
BBTalk, slide 7
Verghese PhD Thesis (CMU – August 1995)
•
Development of substrate circuit model:
– Using Poisson’s equation and continuity equations for electrons and holes we can derive an
equation for the substrate analysis
  (/t)(E) + (E) = 0 where  is a relaxation time constant
– Same equation can be derived from Maxwell’s equations
•
•
Substrate model (below left) was used to study effect of digital gate coupling noise into
substrate and affecting analog transistor tied into same substrate model
Figure (below right) shows admittance coupling (magnitude of Y12) between two
different nodal points of the substrate model versus frequency
– For 15 ohm-cm material, the frequency dependence starts to become important above about
4-5 GHz; for more heavily doped substrates, the roll-off moves to higher frequencies
Nishath Verghese’ PhD Thesis, CMU, 1995
R. W. Knepper
BBTalk, slide 8
Comparison of Device Medici Simulation with
Circuit SPICE Mesh Simulation: P+ Substrate
•
•
•
A comparison was done between Medici device simulation and SPICE circuit
simulation with the mesh substrate model for the case of a heavily-doped P+ substrate
with a lightly-doped P- epi layer on top.
The circuit schematic is shown at the bottom left figure with parasitic inductors added
to account for wire.
Results are shown bottom right for peak-to-peak noise voltage at the sensitive node for
various cases of guard ring, no guard ring, n-well, backside contact, etc.
– Good agreement between Medici Device Simulation and SPICE circuit simulation with
substrate model!
Nishath Verghese
PhD Thesis, CMU, 1995
R. W. Knepper
BBTalk, slide 9
Comparison of Device Medici Simulation with
Circuit SPICE Mesh Simulation: P- Substrate
•
•
•
A comparison was done between Medici device simulation and SPICE circuit
simulation with the mesh substrate model for the case of a lightly-doped P- substrate.
The circuit schematic is shown with parasitic inductors added to account for wire.
Results are shown bottom right for peak-to-peak noise voltage at the sensitive node for
various cases of guard ring, no guard ring, n-well, backside contact, etc.
– Good agreement between Medici Device Simulation and SPICE circuit simulation
– P+ guard ring is more effective in reducing noise than in P+ substrate case
– Backside contact ineffective
Nishath Verghese PhD Thesis, CMU, 1995
R. W. Knepper
BBTalk, slide 10
Discussions with IBM Engineer Robert Barry
Phone conversation with Bob Barry on June 5, 2002
• Suggest we read the following books on substrate noise, modeling and coupling
– Signal Integrity Effects in Custom IC and ASIC Designs, Raminderpal Singh, IEEE Press
and Wiley & Sons, Nov. 2001
– Analysis and Solutions for Switching Noise Coupling in Mixed-Signal IC’s, X. Aragones, et
al., Kluwer Academic Publishers, 1999.
•
Put capacitor across each resistor in substrate model to compute substrate relaxation
time accurately
– C = o/R where R is the resistance of the substrate region (cube)
• If R = l/A = /l = 13.5 ohm-cm / 0.01 cm = 1.35 K, and
• C = oA/l = ol = 8.85E-14 F/cm x 11.9 x 0.01 cm = 10 fF, then
• RC = substrate relaxation time constant = o = 13.5 ps
– For fast risetime pulses with spectral components in the 12-20 GHz range, we will need to
add the capacitors to our substrate model
•
Suggest we put some structures on the chip for S-parameter measurement using three
pad input and output ports (ground-signal-ground)
– Substrate contacts and guard ring structures
– Collector to substrate capacitor
– Transistors
•
Suggest to use bipolar drivers in addition to CMOS drivers due ability to induce large
current spikes into the substrate
R. W. Knepper
BBTalk, slide 11
Substrate Modeling Vendor Code (SeismIC)
•
Marketed by Cadence Design Systems
– Nishath Verghese was a principal at startup Apres Technologies – acquired by CadMOS
Design Technology in Oct 1998 – acquired by Cadence in April 2001
•
SeismIC Methodology
– Complete physical design of the chip
– Solves the equation   (/t)(E) + (E) = 0
• integral form using Green’s function for large multi-layered substrates (for greater speed)
• differential form for the top layer with wells, trenches, and devices (for greater accuracy)
– Extracts an RC network from the substrate matrix
– Simulate circuit to determine coupled noise injection points
– Perform transient simulation including all noise sources and devices
• Noise sources can be studied one at a time
– Modify design as required using new results and repeat process
•
Cost is excessive ( > $100K/seat)
“Preventing a NoiseQuake”,
IEEE Circuits and Devices
Magazine, Ponnapalli,
Verghese, Chu, and Coram,
Nov. 2001
R. W. Knepper
BBTalk, slide 12
“0.13 um 210 GHz Ft SiGe HBTs – Expanding the Horizons of SiGe BICMOS”,
Joseph, et al, IBM, IEEE ISSCC, Paper 11.1, Feb. 2002
R. W. Knepper
BBTalk, slide 13
IBM SiGe Technology Comparison
“0.13 um 210 GHz Ft SiGe HBTs – Expanding the Horizons of SiGe BICMOS”,
Joseph, et al, IBM, IEEE ISSCC, Paper 11.1, Feb. 2002
R. W. Knepper
BBTalk, slide 14
6HP SiGe Process: Base-after-Gate Integration
•
•
•
•
•
“0.13 um 210 GHz Ft SiGe HBTs – Expanding the Horizons of SiGe BICMOS”,
Joseph, et al, IBM, IEEE ISSCC, Paper 11.1, Feb. 2002
SiGe Bipolar is integrated into
CMOS process
SiGe film deposited with Low
Temperature Epi (LTE) tool with
Ge atomically graded from 0% to
about 10% and back to 0% within
the (<500A) base film
NPN built after CMOS is
structurally completed
Minimize NPN thermal budget
Utilized in technologies 0.25 um
and beyond
R. W. Knepper
BBTalk, slide 15
IBM 0.18um SiGe NPN Vertical Cross-section
•
•
•
•
•
“0.13 um 210 GHz Ft SiGe HBTs – Expanding the Horizons of SiGe BICMOS”,
Joseph, et al, IBM, IEEE ISSCC, Paper 11.1, Feb. 2002
Shallow and Deep trench
isolations
Buried N+ subcollector with epi
layer
Carbon-doped SiGe LTE base
region
Min WE = 0.2 um
CoSi2 collector and base
contacts
R. W. Knepper
BBTalk, slide 16
HBT Performance Trend - fT
•
Cutoff frequency quadrupled over 4 generations of SiGe HBTs
“0.13 um 210 GHz Ft SiGe HBTs – Expanding the Horizons of SiGe BICMOS”,
Joseph, et al, IBM, IEEE ISSCC, Paper 11.1, Feb. 2002
R. W. Knepper
BBTalk, slide 17
HBT Performance Trend - fmax
•
Rbb and Ccb reduced simultaneously with transit time to improve speeds > 200 GHz
“0.13 um 210 GHz Ft SiGe HBTs – Expanding the Horizons of SiGe BICMOS”,
Joseph, et al, IBM, IEEE ISSCC, Paper 11.1, Feb. 2002
R. W. Knepper
BBTalk, slide 18
IBM SiGe NPN Operating Voltage
•
•
•
•
BVCEO has been reducing with technology scaling (higher doping, narrower base)
Avalanche does not create degradation
Designers may readily design above BVCEO (using BVCER) with low base resistance RB
Modeling reverse base current is the key
“0.13 um 210 GHz Ft SiGe HBTs – Expanding the Horizons of SiGe BICMOS”,
Joseph, et al, IBM, IEEE ISSCC, Paper 11.1, Feb. 2002
R. W. Knepper
BBTalk, slide 19
6HP BICMOS Models and Layout Design Rules
•
Obtain SiGe 6HP Design
Kit from IBM via MOSIS
(USC)
– License agreement must
be signed by Boston
University legal dept
– IBM Microelectronics
conducts training sessions
on use of models and
design kit
•
•
Runs in Cadence SpectreRF
CAD tool
Device specs at left
R. W. Knepper
BBTalk, slide 20
Circuit Design in Cadence SpectreRF
•
•
•
Cadence Affirma RF Simulator (SpectraRF) is already installed in ECE VLSI Lab
running on new SUN Blade 100 workstations
SC913 students have completed tutorials on simulation of a mixer, an oscillator with
transmission delay line, a low noise amplifier, and transmission line
SpectreRF capability
–
–
–
–
–
–
–
•
Periodic Steady State analysis (PSS) – large signal
Periodic AC analysis (PAC)
Periodic S Parameter analysis (PSP)
Periodic Transfer Function analysis (PXF)
Periodic Noise analysis (PNoise)
Quasi-periodic noise analysis (QNoise)
Periodic Distortion analysis (Pdisto)
Standard methodology
–
–
–
–
Design (schematic) in Composer
Layout in Virtuoso
Checking with DRC and LVS
Extract models and simulate in Analog Environment with SpectreRF model library
R. W. Knepper
BBTalk, slide 21
Noise Characterization Test Site Preliminary Floorplan
•
•
Allowed chip area = 10 mm2 max
CMOS and NPN drivers
– Utilize to generate capacitive noise
coupling to the P- substrate from
switching drains and collectors
– Selectable in groups of 4 to 32
simultaneously switching
•
Analog and RF circuits
– Design in a way to observe behavior (or
failure) with increasing numbers of
switching digital drivers
– Utilize different types of substrate
contacts and guard ring protection
– To be designed by teams of 2 or 3
students each
•
On-chip probe-able structures for Sparameter and simple dc measurements
– Single devices and capacitors
– Interconnect wire and transmission lines
– Substrate contact and guard ring exp’s
R. W. Knepper
BBTalk, slide 22
Progress To Date
•
•
•
•
Students completed SpectreRF tutorials
Assigned reading and reports on selected
IEEE papers on substrate modeling research
results
Study of Nishath Verghese PhD thesis,
CMU, 1995, on substrate modeling
Started development of three-layer
substrate resistive model for 700 um thick
P- substrate with digital and analog circuits
tied-in to demonstrate effects of substrate
noise
– Top layer schematic sketch shown at left
with arbitrary points to hook in circuits
– CMOS driver NFET device node N2 (&
output pad capacitance)
– Current mirror and diff amp tie-in via N1
– BICMOS mixer circuit tie-in via N3
•
•
Initial Cadence simulation complete
Waiting for license signing to receive SiGe
6HP design kit
R. W. Knepper
BBTalk, slide 23
Progress To Date (continued)
•
•
•
Resistive substrate model (top layer only) show below at left
Cadence simulation results show severe noise spikes coupled into differential outputs of
CMOS diff amp with current mirror current source – somewhat independent of location
Bottom two traces show mixer output (NPN collectors) - seems immune to substrate noise
R. W. Knepper
BBTalk, slide 24
Chien-Chih Huang,
Raman Mathur
SC500: RF/Analog IC Design Fundamentals
Course Description:
• This course will teach the fundamentals of CMOS and SiGe HBT BICMOS RF and
analog circuit technology used in the design of a single chip radio. Topics to be
covered include low noise amplifiers, switched capacitor circuits, A/D and D/A
converters, phase locked loops, oscillators, mixers, active filters, low power design,
RF design techniques, and mixed-signal circuitry typical of modern
telecommunications technology. The course will include VLSI laboratory exercises
involving the design, layout, and simulation of RF and analog integrated circuits
using Cadence CAD software tools.
• Textbook(s):
– Design of CMOS Radio Frequency Integrated Circuits, Thomas Lee, Cambridge Univ
Press, 1998
– Low-Power CMOS Radio Receivers, Shaeffer and Lee, Kluwer, 1999
– Analog Integrated Circuit Design, Johns and Martin, Wiley, 1997
•
Prerequisites:
– SC410, SC412, SC571, or permission of instructor
•
•
Professor: Ron Knepper, ECE Dept.
Meets: M/W 2-4 PM
R. W. Knepper
BBTalk, slide 25
SC500 RF/Analog IC Design Fundamentals
Topic
• Compact analog/RF circuit models for BICMOS devices
• SiGe BICMOS Technology: process, layout, and design rules
• Operational amplifiers, comparators, current mirrors
• Switched capacitor circuits
• A/D and D/A Converters
• Active Filters
• Noise analysis/low noise amplifier design
• RF techniques on-chip
• Mixers
• Oscillators
• RF Power Amplifiers
• Phase-Locked Loop
• Low power design techniques
• Radio receiver architectures
• Design of a single chip radio
Total:
Weeks
1
1
1
0.5
1
0.5
1
1
1
1
0.5
1
0.5
0.5
1.5
13
R. W. Knepper
BBTalk, slide 26