Introduction to FPGAs - Science and Technology Facilities
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Transcript Introduction to FPGAs - Science and Technology Facilities
Introduction to
Programmable Logic Devices
John Coughlan
STFC Technology Department
Detector & Electronics Division
PPD Lectures
Programmable Logic is a Key Underlying Technology for PP Experiments.
First-Level and High-Level Triggering
Data Transport (Networks)
Computers interacting with Hardware (Networks)
Silicon Trackers (Millions of Data Channels)
Commercial Devices. Developments driven by Industry.
Telecomms, Gaming, Aerospace, Automotive, Set-top boxes….
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The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Particle Physics Electronics
CMS
CERN LHC
[email protected]
Custom Electronics Chips
ASICs ANALOGUE $$$
Rad Hard, Low Power
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Particle Physics Electronics
CMS
Custom Electronics Chips
ASICs ANALOGUE $$$
Rad Hard, Low Power
CERN LHC
Electronics Rooms
Trigger Systems. DAQ Systems.
DIGITAL
[email protected]
Custom Digital Processing Boards
VME Bus Crates
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Particle Physics Electronics
Special Dedicated Logic Functions (not possible in CPUs)
Ultra Fast Trigger Systems (Trigger Algorithms) Clock Accurate
Timing
Massively Parallel Data Processing (Silicon Trackers with Millions of
Channels)
Custom Designed
Printed Circuit Boards PCBs.
Commercial
Programmable Logic
Devices, FPGAs
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Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
CMS DAQ/Trigger Architectures
CMS
Fully custom PP ASICs
Programmable Logic
DIGITAL
CPUs Commodity PCs
“Telecoms Network” ~ 1 Tbps
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Lecture Outline
Programmable Logic Devices
FPGA Field Programmable Gate Array
Basics
Evolution
Architecture
Design Flow
Hardware Description Languages
Design Tools
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Devices, Tools, and Flows. ISBN 0750676043
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Digital Logic
Logic Gates
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Digital Logic
Logic Gates
Transistor Switches
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Digital Logic
Logic Gates
MOORE’S LAW
Transistor Switches
< 40 nm ! $$$
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Digital Logic
Digital Logic Function
Product AND (&)
Sum OR (|)
3 Inputs
Black Box
[email protected]
Truth Table
(Look Up Table LUT)
SUM of PRODUCTS
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Digital Logic
Digital Logic Function
Product AND (&)
Sum OR (|)
3 Inputs
Black Box
[email protected]
Truth Table
(Look Up Table LUT)
SUM of PRODUCTS
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Digital Logic
Digital Logic Function
Product AND (&)
Sum OR (|)
3 Inputs
Black Box
[email protected]
Truth Table
(Look Up Table LUT)
SUM of PRODUCTS
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Programmable Logic Devices
PLDs
Inputs
Un-programmed State
ANDs
SUM of PRODUCTS
(Re-)Programmble Links
Reconfigurable
GLUE LOGIC
Planes of
ANDs, ORs
ORs
Outputs
Logic Functions
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Programmable Logic Devices
PLDs
Inputs
Un-programmed State
ANDs
SUM of PRODUCTS
(Re-)Programmble Links
Reconfigurable
GLUE LOGIC
Planes of
ANDs, ORs
ORs
Outputs
Logic Functions
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Programmable Logic Devices
PLDs
Inputs
Un-programmed State
ANDs
SUM of PRODUCTS
(Re-)Programmble Links
Reconfigurable
GLUE LOGIC
Planes of
ANDs, ORs
ORs
Outputs
Logic Functions
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Programmable Logic Devices
PLDs
Inputs
Un-programmed State
ANDs
SUM of PRODUCTS
(Re-)Programmble Links
Reconfigurable
GLUE LOGIC
Planes of
ANDs, ORs
ORs
Outputs
Logic Functions
Sums
Programmed PLD
Product Terms
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Programmable Logic Devices
PLDs
Logic Functions
Programmed PLD
Sums
Product Terms
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Programmable Logic Devices
PLDs
Logic Functions
x
x
x
Programmed PLD
x
x
Sums
Product Terms
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Programmable Logic Devices
PLDs
Logic Functions
x
x
x
GLUE LOGIC
x
Programmed PLD
x
x
x
Sums
Product Terms
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Complex PLDs
CPLDs
Programmable PLD Blocks
Programmable Interconnects
Electrically Erasable links
Feedback Outputs
CPLD Architecture
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Sequential Circuits
Combinational Logic (Larger circuits difficult to predict)
Synchronous Logic driven by a CLOCK
Registers, Flip Flops (Memory)
Inputs
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Sequential Circuits
Combinational Logic (Larger circuits difficult to predict)
Synchronous Logic driven by a CLOCK
Registers, Flip Flops (Memory)
Intermediate
New Output every clock edge
Inputs
CLOCK
Register
EDGES
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Sequential Circuits
Combinational Logic (Larger circuits difficult to predict)
Synchronous Logic driven by a CLOCK
Registers, Flip Flops (Memory)
Intermediate
New Output every clock edge
Inputs
Clock Rate determines speed
CLOCK
EDGES
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Register
Comb Logic Must meet Timing
=> Predictable circuits
Shift Registers,
Pipelines,
Finite State Machines
…
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Field Programmable Gate Arrays
FPGA
Field Programmable Gate Array
‘Simple’ Programmable Logic Blocks
Massive Fabric of Programmable Interconnects
Standard CMOS Integrated Circuit fabrication process as for
memory chips (Moore’s Law)
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Field Programmable Gate Arrays
FPGA
Field Programmable Gate Array
‘Simple’ Programmable Logic Blocks
Massive Fabric of Programmable Interconnects
Standard CMOS Integrated Circuit fabrication process as for
SRAM memory chips (Moore’s Law)
Huge Density of Logic Block ‘Islands’
1,000 … 100,000’s
in a ‘Sea’ of Interconnects
FPGA Architecture
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Field Programmable Gate Arrays
FPGA
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Logic Blocks
Logic Functions implemented in Look Up Table LUTs.
Flip-Flops. Registers. Clocked Storage elements.
Multiplexers (select 1 of N inputs)
16-bit SR
16x1 RAM
a
b
c
d
4-input
LUT
y
mux
flip-flop
q
e
clock
clock enable
set/reset
FPGA Fabric
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Logic Block
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Look Up Tables LUTs
LUT contains Memory Cells to implement small logic functions
Each cell holds ‘0’ or ‘1’ .
Programmed with outputs of Truth Table
Inputs select content of one of the cells as output
3 Inputs LUT -> 8 Memory Cells
16-bit SR
16x1 RAM
3 – 6 Inputs
a
b
c
d
4-input
LUT
y
mux
flip-flop
q
e
clock
clock enable
set/reset
SRAM
SRAM
Multiplexer MUX
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Static Random Access Memory
SRAM cells
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Look Up Tables LUTs
LUT contains Memory Cells to implement small logic functions
Each cell holds ‘0’ or ‘1’ .
Programmed with outputs of Truth Table
Inputs select content of one of the cells as output
Configured by re-programmable SRAM memory cells
3 Inputs LUT -> 8 Memory Cells
16-bit SR
16x1 RAM
3 – 6 Inputs
a
b
c
d
4-input
LUT
y
mux
flip-flop
q
e
clock
clock enable
set/reset
SRAM
SRAM
Multiplexer MUX
[email protected]
Static Random Access Memory
SRAM cells
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
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Logic Blocks
Larger Logic Functions built up by connecting many Logic
Blocks together
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Logic Blocks
Larger Logic Functions built up by connecting many Logic
Blocks together
Determined by SRAM cells
SRAM
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SRAM cells
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Clocked Logic
Registers on outputs. CLOCKED storage elements.
Synchronous FPGA Logic Design, Pipelined Logic.
FPGA Fabric Pulse from Global Clock (e.g. LHC BX frequency)
16-bit SR
16x1 RAM
a
b
c
d
e
4-input
LUT
y
mux
flip-flop
q
clock
clock enable
set/reset
FPGA Fabric
Special Routing for Clocks
Clock from Outside world (eg LHC bunch frequency)
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Input Output I/O Getting data in and out
1
0
2
7
General-purpose I/O
Up to
> 1,000
I/O “pins”
(several 100 MHz)
banks
0 through
7
3
6
4
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5
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Input Output I/O Getting data in and out
1
0
2
7
General-purpose I/O
Up to
> 1,000
I/O “pins”
(several 100 MHz)
banks
0 through
7
3
6
4
Special I/O SERIALISERS
~ 10 Gbps transfer rates
5
Transceiver block
Differential pairs
FPGA
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Optical TRx
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Designing Logic with FPGAs
Design Capture.
High level Description of Logic Design.
Graphical descriptions
Hardware Description Language (Textual)
Textual HDL
Graphical State Diagram
When clock rises
If (s == 0)
then y = (a & b) | c;
else y = c & !(d ^ e);
Top-level
block-level
schematic
Graphical Flowchart
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Block-level schematic
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Hardware Description Languages
Language describing hardware (Engineers call it FIRMWARE)
Doesn’t behave like “normal” programming language ‘C/C++’
Describe Logic as collection of Processes operating in Parallel
Language Constructs for Synchronous Logic
Compiler (Synthesis) Tools recognise certain code constructs
and generates appropriate logic
Not all constructs can be implemented in FPGA!
2 Popular languages are VHDL , VERILOG
Easy to start learning… Hard to master!
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VHDL
ENTITY Declaration Input Output to Module (STD LOGIC)
SIGNALS Declaration WIRES
CONCURRENT ASSIGNMENTS
CONDITIONAL ASSIGNMENTS => MULTIPLEXERS
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VHDL
PROCESS Declaration. CONCURRENT functions. Synchronous Logic.
COMPONENT Declaration
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Designing Logic with FPGAs
High level Description of Logic Design
Hardware Description Language (Textual)
Compile (Synthesis) into NETLIST.
Boolean Logic Gates.
Target FPGA Device
Mapping
Routing
Schematic
capture
Gate-level
netlist
BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B,
DATA, CLOCK,
CLEAR_A, CLEAR_B;
OUTPUT Q, N_Q;
WIRE
SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A,
IN2=SET_B,
OUT1=SET);
GATE G2=NOT (IN1=DATA,
OUT1=N_DATA);
GATE G3=OR
(IN1=CLEAR_A,
IN2=CLEAR_B,
OUT1=CLEAR);
GATE G4=DFF (IN1=SET, IN2=N_DATA,
IN3=CLOCK, IN4=CLEAR,
OUT1=Q, OUT2=N_Q);
Bit File for FPGA
END CIRCUIT=TEST;
Mapping
Commercial CAE Tools
(Complex & Expensive)
Logic Simulation
Packing
Design Flow
Place-andRoute
Fully-routed physical
(CLB-level) netlist
Timing analysis
and timing report
Gate-level netlist
for simulation
SDF (timing info)
for simulation
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Designing Logic with FPGAs
High level Description of Logic Design
Hardware Description Language (Textual)
Compile (Synthesis) into NETLIST.
Boolean Logic Gates.
Target FPGA Device
Mapping
Routing
Schematic
capture
Gate-level
netlist
BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B,
DATA, CLOCK,
CLEAR_A, CLEAR_B;
OUTPUT Q, N_Q;
WIRE
SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A,
IN2=SET_B,
OUT1=SET);
GATE G2=NOT (IN1=DATA,
OUT1=N_DATA);
GATE G3=OR
(IN1=CLEAR_A,
IN2=CLEAR_B,
OUT1=CLEAR);
GATE G4=DFF (IN1=SET, IN2=N_DATA,
IN3=CLOCK, IN4=CLEAR,
OUT1=Q, OUT2=N_Q);
Bit File for FPGA
END CIRCUIT=TEST;
Mapping
Commercial CAE Tools
(Complex & Expensive)
Logic Simulation
Packing
Design Flow
Place-andRoute
Fully-routed physical
(CLB-level) netlist
Timing analysis
and timing report
Gate-level netlist
for simulation
SDF (timing info)
for simulation
[email protected]
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Designing Logic with FPGAs
High level Description of Logic Design
Hardware Description Language (Textual)
Compile (Synthesis) into NETLIST.
Boolean Logic Gates.
Target FPGA Device
Mapping
Routing
Schematic
capture
Gate-level
netlist
BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B,
DATA, CLOCK,
CLEAR_A, CLEAR_B;
OUTPUT Q, N_Q;
WIRE
SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A,
IN2=SET_B,
OUT1=SET);
GATE G2=NOT (IN1=DATA,
OUT1=N_DATA);
GATE G3=OR
(IN1=CLEAR_A,
IN2=CLEAR_B,
OUT1=CLEAR);
GATE G4=DFF (IN1=SET, IN2=N_DATA,
IN3=CLOCK, IN4=CLEAR,
OUT1=Q, OUT2=N_Q);
Bit File for FPGA
END CIRCUIT=TEST;
Mapping
Commercial CAE Tools
(Complex & Expensive)
Logic Simulation
Packing
Design Flow
Place-andRoute
Fully-routed physical
(CLB-level) netlist
Timing analysis
and timing report
Gate-level netlist
for simulation
SDF (timing info)
for simulation
[email protected]
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Devices, Tools, and Flows. ISBN 0750676043
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Configuring an FPGA
Millions of SRAM cells holding LUTs and Interconnect Routing
Volatile Memory. Lose configuration when board power is
turned off.
Keep Bit Pattern describing the SRAM cells in non-Volatile
Memory e.g. PROM or Digital Camera card
Configuration takes ~ secs
JTAG Port
Configuration data in
Configuration data out
= I/O pin/pad
= SRAM cell
SRAM
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Configuring an FPGA
Millions of SRAM cells holding LUTs and Interconnect Routing
Volatile Memory. Lose configuration when board power is
turned off.
Keep Bit Pattern describing the SRAM cells in non-Volatile
Memory e.g. PROM or Digital Camera card
Configuration takes ~ secs
JTAG Port
Configuration data in
Configuration data out
= I/O pin/pad
Programming
Bit File
= SRAM cell
SRAM
JTAG Testing
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Field Programmable Gate Arrays
FPGA
Large Complex Functions
Re-Programmability, Flexibility.
Massively Parallel Architecture
Processing many channels simultaneously cf MicroProcessor
Fast Turnaround Designs
Standard IC Manufacturing Processes. Moore’s Law
Mass produced. Inexpensive.
Many variants. Sizes. Features.
PP Not Radiation Hard
Power Hungry
No Analogue
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FPGA Trends
State of Art is 40nm on 300 mm wafers
Top of range >500,000 Logic Blocks
>1,000 pins (Fine Pitched BGA)
Number of LCs
1.00E+09
1.00E+08
1.00E+07
1.00E+06
1.00E+05
1.00E+04
1.00E+03
1.00E+02
1985
Logic Block cost ~ 1$ in 1990
Today < 0.1 cent
1990
1995
2000
2005
2010
2015
2020
2025
Year
1
Problems
Power. Leakage currents.
Design Gap
CAE Tools
$ / LC
0.1
0.01
0.001
0.0001
1990
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1995
2000
2005
2010
2015
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Summary
Programmable Logic Devices
FPGA Field Programmable Gate Arrays
Basics
Evolution
Architecture
Design Flow
Hardware Description Languages
Design Tools
Importance for Particle Physics Experiments
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References
The Design Warrior’s Guide to FPGAs
VHDL for Logic Synthesis
Andrew Rushden, Wiley
FPGA manufacturer web sites
Clive Maxfield, Newnes Elsevier
www.xilinx.com
www.altera.com
FPGA Online
www.pldesignline.com
www.fpgajournal.com
www.doulos.com
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Devices, Tools, and Flows. ISBN 0750676043
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Spare Slides
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System on a Chip
Add Embedded Micro-Processor Cores in Fabric
e.g. RISC PowerPC
Ethernet Interface
Run Operating System e.g. Linux
Combine Micro-Processor
& Massively Parallel Logic
Dual Design Flows
uP
uP
uP
uP
Firmware HDL
Software C
(a) One embedded core
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uP
(b) Four embedded cores
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Time line of Programmable devices
1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000
Transistors
ICs (General)
SRAMs & DRAMs
Microprocessors
SPLDs
CPLDs
ASICs
FPGAs
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Application Specific Integrated Circuits
ASICs
PLDs
SPLDs
Prefabricated
Programmed
CPLDs
ASICs
The
GAP
Gate Arrays
Custom Fabricated
Design from Scratch
Structured ASICs*
Standard Cell
Full Custom
*Not available circa early 1980s
Limited Complexity
Thousands of Gates
Large Complex Functions . Millions of Gates
Customised for Extremes of Speed, Low Power, Radiation
Hardness
Cheap
Easy to Design
Reprogrammable.
(Very) Expensive to Design (in small quantities)
> $1 Million mask set
(Very) Hard to Design.
Long Design cycles.
NOT Reprogrammable. FROZEN in Silicon. High Risk
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