Transcript Very Deep Sub Micron Overview

Intel® Microelectronics Services
VDSM Issues and Design Methodology
January 2002
www.Intel.com/design/ASICs
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What’s Ahead for Technology
Morning Summary
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Key Parameters of Scaling
Process
.18u to .13u to 90n…
Complexity
2M to 5M to 10M gates…
Performance
300MHz to multi-GHz…
Density
Metal layer tradeoff, library
selection, optimization
Productivity
Gates/designer-day,
Design reuse
Quality / Reliability
DPM, FIT, SER,
Hot Carrier Effect
Power
Active, Leakage
Major inflections in each create
significant design challenges
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Dis-aggregation of Electronic
Product Development
Software
Development
Systems
Design
What’s the Best Use of
Internal and External
Resources?
Chip
Architecture,
Specification
Logic Design
& Verification,
Integration
Physical
Design &
Validation
Package
Design
Manufacturing,
Assembly, &
Test
Proto, Debug,
FA, QA
Volume Prod/
Yield Mgmt
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Escalating Development
Costs and Time
Sample (Actual) VDSM Projects
Application
Graphics
Wireless Networking
Networking
Wireless
Geometry
0.13µ
0.13µ
0.13µ
0.13µ
0.13µ
Transistors
30M
12M
12M
24M
12M
Cost
$10.7M
$9.0M
$5.7M
$10.9M
$16.3M
Staff-months
346
326
161
333
483
Average: $10M+, 300+ Staff-months !
Source: International Business Strategies, 2002
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Meet New Friends: NBTI…
 Transistor
performance degrades
as a function of time,
temperature, and
voltage
 Unpredictable effect
on transistors - vary
by design parameters
 NBTI may not manifest
itself in first silicon,
but during production
use
EE Times, 4/15/2002
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Success May Be Fleeting
Probability of Success
100
90
80
Operates As Expected
70
Full Mask Re-spin
60
50
40
30
20
10
0
0.25
0.18
0.15
0.13
0.10 µm
(estimated)
Source: International Business Strategies, 2002
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Re-spins are EXPENSIVE
Costs
($K) 10,000
$10.7M
Proto & Validation
8,000
Support SW
Physical Design
6,000
Verification
$4.7M
4,000
Design Planning
IP Dev and Qual
2,000
Spec
0
Original
Re-spin
Plus a) lost revenue, b) opportunity costs
Source: International Business Strategies, 2002
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Scaling Challenge Era
1998
0.13
m
0.18
m
1999
2000
2001
SER on Static
Leakage Power
In-die Variation
Power Integrity
Signal Integrity
0.25
m
Interconnect RC
Inflection Point
m
0. 5 m
0. 7 m
0.35
Increasing Design Complexity
Each Generation
9
2002
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IP Creation and Integration
Challenges
Effort to reuse
internal IP ?
Is the IP available in the
fab/process that I need?
What about
support ?
IP
Decisions
Are business terms
acceptable ?
Does it have all
the views I need?
I’ve got IP
from multiple sources,
will it integrate?
Does the IP come with
verification suites I can reuse?
DRC/LVS rule
decks - are they
consistent ?
Will the IP meet
timing?
All IP is not created equal !
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Hierarchical Design Method Used
Spec
Top-Level
Constraints
Pre-RTL
Floor planning
Static Analysis
Physical
Verification
Block
Constraints
Floor planning
RTL
Pin File
Libraries
Cells
Rule Decks
Routing
•
•
•
•
•
•
•
•
To
I/OPlaced
Power
RTL
Clocking
Critical
Extraction
ERC,
Placement
toDRC,
Analysis
Gates
Nets
Topology
Gates
LVS
Topology
Powermngt
Connectivity
Skew
Global,
Static
Metal
Fills/Slots
&Bus/Grid
Detail
Formal
Partitioning
Clock
Congestion
Line
ECO
Without
Re-visit
delay
Pre-routes
Timing
Crosstalk
ctrl
Antennae
Timing
BlockCrosstalk
Other
Fan-out
With
GDSII
location
Pre-routes
Finishing
Driven
ctrl
Fixing
Block pin
Power
andlocation
Clocks
Obstructions
Pre-Routes
Refinement
Fillers/Spares
Scan Re-order
Power Planning &
Pre-Routing
Physical Synthesis
& Placement
Synthesis
11
Clock-Tree
Synthesis
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What’s Ahead
High Speed
Device Scaling
Power
Reliability
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Technology Convergence
OC-- 192
OC
Gigabits per second
10
10G-- FC
10G
Storage Area Networks (SAN)
Fiber
Channel
OC-- 48
OC
10GE
1
Gigabit
Ethernet (LAN)
OC-- 12
OC
Local Area Networks
(LAN)
OC--3
OC
0.1
Synchronous
Optical
Networks
(WAN)
Fast
Ethernet( LAN)
Storage (SAN)
Sonet (WAN)
Ethernet (LAN)
Ethernet (LAN)
0.01
1996
13
1998
2000
2002
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High Speed I/O Trends
 Single-ended scheme to differential
 Parallel bus to serial link
 Voltage drivers to current mode drivers
 Simple signaling to timing & voltage modulations
 Multi-drop interfaces to point-to-point links
 Source-synchronous to embedded clocking
 Wire bond to FCBGA
Fundamental change in designing high speed I/O
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On-die & On-package Wave Equations
 What is moving inside silicon, package and board?
• Electrons and electromagnetic field ?
V ( x, t )
V 2 ( x, t ) / x2  RC  V ( x, t ) / t  LC  V 2 ( x, t ) / t 2
 Diffusion (RC) Equation
• On-Chip, RC >> LC
V 2 ( x, t ) / x2  RC  V ( x, t ) / t
 Dispersion (LC) Equation
• On package and board, LC >> RC
On-die & on-package are
mathematically & physically
very different.
V 2 ( x, t ) / x2  LC  V 2 ( x, t ) / t 2
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Diffusion and Dispersion Waveform
 Diffusion
• Both delay and rise/fall time are linear proportional to RC, and the
distance by X2
Delay ~ 0.4 X2 RC, and Rise/Fall ~ X2 RC
 Dispersion
• Both delay and rise/fall time are linear proportional to and X
Delay ~ X, and amplitude ~ 1/X
Diffusion
Dispersion
0.8ns
4m
2ns
20m
I/O design is fundamentally different from core design
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Cross-talk
vin
 Inductive & capacitive
coupling
 Near and far end crosstalk noise
 Amplitude and duration
• Prop. to Lm and Cm
• Prop. to signal swing
• Related to
tr
V
Far end
Near end
0.5*(tr+X*sqrt(LC))
termination
transmission line length
Slew rate
 Impact on timing and
noise margin
17
Scan – more cases
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Inter-Symbol Interference
 ISI
Ideal pattern
Realistic pattern
• A value or symbol on a channel
can corrupt another traveling
on the same channel at a later
time.
• This ISI occurs as a result of
energy from one symbol stored
in the channel sums later with
a unrelated symbol.
 Example:
DV
Clock pattern
Single pulse
D time
Random
Data Pattern
• In the LVCMOS bus, the ISI
is on the order of 250ps
Clock Pattern
18
Scan - Data an clock pattern
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Signal Return Discontinuity
 Impedance mis-match
Signal 1
Signal 1
Signal 2
Signal 2
GAP
• Along signal return path
Reference plane
0.1”
 For example, a GAP
Reference plan
Return
current
• If the gap is comparable
to the edge rate
• The effect will be similar
to that of the serial
inductance
 Effect
• Inductive spike at driver
Scan -
• Ledge on the signal
• Significant coupling
onto next line
19
D
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High Frequency Loss
 High freq. skin loss
• The changing current
distribution due to change of
freq. results a increase of
resistance
R ~ k * sqrt ( freq )
Scan picture
 High freq. dielectric loss
• Due to electric polarization,
resulted change of dielectric
constant, usually over GHz
• Measured by loss tangent
 Return loss
• Reflection due to Zo mis-match
• Seen at 3GI/O SPEC
20
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Transmitter Equalization
 Freq. dependent
attenuation
• The “lone” pulse
 Use high-pass FIR
filter
• Transfer function
that approximates
the inverse of Tx
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Signal Schemes, “Direction”
 Uni-directional
• Sending signal one directional
• Receive signal at end of transmission
• Such as LVDS, LVCMOS on Eagle
 Bi-directional
Uni-directional Eye
• Sending signal sometime one way, sometime
on the opposite way, but not the same time
• Such as DDR memory bus for Ocelot
 Simultaneous bi-directional
• Sending signal both way “Simultaneously”
• Save pins or higher BW/pin
• Such as scalability port on Intel McKinley
platform
22
Simultaneous bi-directional Eye
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Signaling with Current and Voltage
 Signaling with voltage
Signaling with voltage
• Driver transistor in linear
range
• Bigger mis-match with line
Zo (~15 ohms vs. 50
ohms)
tr
~ 15 ohms
50 ohms
50 ohms
 Signaling with current
Signaling with current
• Driver in saturation
• Driver side termination to
match better with line Zo
tr
>300ohms
50 ohms
50 ohms
• Isolate the ground noise
23
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50 ohms
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Sample IME I/Os
SSTL2
300
singleended
PCI
66
singleended
SPI-4
1680
PECL
840
differential
LVCMOS
125
singleended
differential
differential
HSTL
200
singleended
current
voltage
voltage
voltage
current
current
voltage
Driver Equalization
no
no
no
no
yes
no
no
Driver Rise/Fall (ns)
1
2
1
3
1
3
3
300
linear
amplifier
CMOS
CMOS
CMOS
300
linear
amplifier
Link Speed (Mb/s)
Driving Scheme
Driver
Driver Swing (mv)
Receiver
Termination(W)
cmos
50 ? , on-die, ??? , on-die,
drv&rev
drv&rev
cmos
cmos
no
no
CMOS
linear
amplifier
50 ? , on-die, 50 ? , on-die,
drv&rev
drv&rev
cmos
no
< 5"
< 5"
~10"
~10"
< 7"
~10"
~10"
Package
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
I/O voltage (V)
3.3, 1.8
2.5, 1.8
2.5, 1.8
3.3, 1.8
3.3, 1.8
(-5.1, 1.8)
3.3, 1.8
Interconnect/PCB
24
LVDS
1200
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What’s Ahead
High Speed
Device Scaling
Power
Reliability
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Why Go Smaller?
CoSi2
Si3N4
130nm
Improved density
– 0.7x feature size per generation
70 nm
– Pack ~2x more transistors per
area
Faster switching speed
– 0.7x gate delay per generation
65nm
– >1.4x frequency increase
Lower switching power
LG = 30nm
R. Chau IEDM 2000
– Reduced supply voltage (VDD)
– Reduced device area
Source: Mark Bohr Intel 2001 IVC/AVS
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Process Technology Challenge
Minimum Feature Size Trend
10
3.0um
2.0um
1.5um
1.0um
0.8um
1
0.5um
0.35um
0.25um
180nm
130nm
90nm
65nm
Micron
LGATE
0.1
LGATE
0.01
1970
1980
1990
2000
2010
Year
27
2020
Source: Mark Bohr Intel 2001 IVC/AVS
Sub-100nm is closer than you think
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Shrinking Transistor Challenge
Power Leakages Increase
Sub-threshold Leakage (IOFF)
Reduce VDD for power
Gate
Drain
Source
IOFF
Reduce VT for performance
Lower VT increases IOFF
Gate
IGATE
Drain
29
Source
Gate Oxide Leakage (IGATE)
Thinner oxide for performance
130 nm generation down to
1.5 nm (~6 atoms)
Tunneling current becoming
significant
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Shrinking Transistor Challenge
Power Leakages Increase
1.E-05
1.E-06
Sub-threshold Leakage (IOFF)
IOFF
1.E-07
• Reduce VDD for power
• Reduce VT for performance
• Lower VT increases IOFF
High-k
Leakage 1.E-08
(A/um) 1.E-09
IGATE
1.E-10
1.E-11
1.E-12
65
90
130
180
250
Technology Generation (nm)
0100nm 15mm die 0.7V
70
Power (Watts)
49%
41%
60
33%
50
40
Gate Oxide Leakage (IGATE)
56%
6%
9%
14%
19%
26%
Leakage
Active
30
20
– Thinner oxide for performance
– 130 nm generation down to 1.5
nm (~6 atoms)
– Tunneling current becoming
significant
10
-
Temp (C)
30
S. Borkhar, ISPLED ‘00
Becoming a major design consideration
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Shrinking Transistor Challenge
Option 1: Metal Gate Transistors
NMOS
PolySi Gate
N+
• Eliminate poly depletion
P+
N+
Metal Gate
PMOS
N+
P+
P+
P-well
N-well
M1
M2
N+
N+
P-well
P+
P+
• Optimal performance
requires FMS to match
N+ and P+ silicon
• Process flow is complex
N-well
Reduce equivalent oxide thickness by eliminating poly-gate
depletion
31
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Shrinking Transistor Challenge
Option 2: Double Gate Transistors
G
• ~2x drive current
S
D
• ~2x gate capacitance
• Better short channel
characteristics
Top
S
D
• Complex process
Bottom
Increase drive current per unit area
32
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Intel® Microelectronics Services
Shrinking Transistor Challenge
Option 3: High-k Gate Dialectics
top gate
S
G
100 nm
D
source
S
G
bottom gate
drain
D
S
G
D
Reduce equivalent oxide thickness without increasing
leakage
33
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Shrinking Transistor Challenge
Option 4: Sleep Transistors
Leakage reduction for 5% delay penalty
sleep
transistor
(32-bit KS adder)
Virtual Vcc
Boosted
MTCMOS Sleep
Circuit block
Sleep-TR size
Leakage
power
reduction
Virtual supply
bounce
Virtual Vss
NonBoosted
Sleep
Stackforcing
5.1%
2.3%
3.2%
11.5%
1450X
3130X
11.5X
12X
60 mV
59 mV
58 mV
50 mV
sleep
transistor
R. Krishnamurthy, Intel DAC 2002
Leakage control techniques are very effective
 100X S/D leakage improvement
 ETA second half of decade
34
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The 10,000 Foot View
 100nm introduces a whole new
world of issues
• The days of simple device scaling are
over
• Process technology will continue to drive
to smaller geometries
 New approaches, structures, design
methods and flows are needed to
meet scaling challenges
35
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What’s Ahead
High Speed
Device Scaling
Power
Reliability
36
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Power Scaling
Power density is increasing
70
Surpassed hot-plate power
density in 0.6m
– Performance (higher freq)
– Exponential growth in
leakage
– Exponential impact on
reliability
50
Watts/cm2
Junction Temp <= 100 C is
recommended
60
40
30
20
10
0
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38
Leakage Power
Frequency
C density
30% Vdd
Area
Watts
Power Scaling
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Active capacitance density
Active Cap 
2
Active Cap Density (nf/mm )
1.00
Power
VCC2  freq
Cap Density 
C
Area
0.10
0.01
1.5m
1m
0.8m
0.6m
0.35m
0.25m
0.18m
Active capacitance grows 30-35%
each technology generation
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0.13m
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Leakage Power
10,000
0.10m
0.13m
0.18m
Ioff (na/ )
1,000
Constant E scaling -> Vdd scales
Higher performance -> lower Vt
Lower Vt -> higher drain Leakage
0.25m
100
Reference:
Mark Bohr, et al
IEDM, 1996
10
1
30
40 50
60
70 80
90 100 110
Temp (C)
Sub Threshold Leakage Trend
40
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Leakage Effect on Power
Lkg Pwr
Watts
Active Pwr
75
Power Density
50
25
Power Density (W/cm2 )
100
Each Generation
Constant Die Size
(2x transistors)
~15mm die
1.5X freq increase
each generation
0
0.25m
41
0.18m
0.13m
0.1m
Shekhar Borkar,
ISPD 04/10/00
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Shrinking Transistor Challenge
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Number of paths
Option 5: Dual VT design
Dual VT design
- High VT with nominal Ioff (lower performance)
- Low VT with ~10X higher loff (higher
High VT
performance)
Number of paths
Delay
Employing high VT everywhere yields lower
performance, and lower leakage (1X)
Low VT
Employing low VT everywhere yields higher
performance, but higher leakage (10X)
Number of paths
Delay
Dual VT
Logic path between latch boundaries
Delay
42
Selective usage of low and high Vt yields
higher performance, yet low leakage
between 1X, and <<10X
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What’s Ahead
High Speed
Device Scaling
Power
Reliability
Soft Errors
Wear Out
Degradation
43
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The Reliability and Quality
Challenges
 The bathtub curve
 Common aging and random failure mechanisms
 Hot-e transistor degradation due to hot electrons
 EM – electromigration
 SH - self heat
 Oxide wear out
 NBTI – Negative bias temperature instability (P-Channel)
 SER - Single-event soft errors
44
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Failures
 Failure rate is defined as a function of operating life of a group of
parts or probability per unit time of a given part to fail.
Infant Mortality
• Show up early in life of products
Failure Rate
Infant
Mortality
Event
Related
(random)
Device
Wear-out
• Detected by Burn-in
Event Related
DSM effects
• Show up at various intervals in life
• Random nature
Useful life (years)
Time
The classical bath tub curve presents
failure rate for ICs and DSM effects
45
• Mainly due to product defects
• Example – Signal/Power integrity, SER
• Can be reduce by construction design
Device Wear-out
• Aging mechanism dominate
• Can be pushed out by construction
design
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Reliability and Quality
 Reliability is defined as “the probability of a device
performing its purpose for a period of time intended under
the operation conditions.”
 Quality is defined as the degree of conformance to
specification and/or workmanship. It does not include time
frame, but reliability does
 Reliability means reputation, revenue, and even success to
IME’s customers.
 Three keys for reliable and quality IC products are
•
•
•
46
Construction design
Reliable and consistent manufacture processes
Burn-in and Bake
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What’s Ahead
High Speed
Device Scaling
Power
Reliability
Soft Errors
Wear Out
Degradation
47
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Soft Error Susceptibility
Logic 0
Logic 1
Vinduced
10
Soft error susceptibility
1
0.25m
48
0.18m
0.13m
0.1m
0.07m
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Junction Charge Collection
Ion Track
+V
Vss
n+ diffusion
Junction
Collection
Electric
Field
p- epi
Potential Contour
Deformation
Funnel Collection
Diffusion Collection
Electron-Hole
Pairs
p+ substrate
Recombination
49
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Single Event Environments
 Satellite and other spaceborne applications
• High-energy heavy ions (cosmic rays)
Long range, large dE/dx, direct interaction
• High-energy protons (trapped and solar)
Indirect interaction through recoil Silicon
 Terrestrial and high-altitude applications
• Alpha particles (radioactive decay)
Short range, small dE/dx, direct interaction
• High energy neutrons (cosmic ray byproduct)
Indirect interaction through recoil Silicon
• Low energy neutrons (thermal)
Indirect interaction via Boron nuclear reaction
50
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Single Event Upset (SEU)
 Reversed biased junctions collect charge
• Static latches
• SRAMs
 Circuit feedback magnifies voltage transients
• Data state flips if voltage crosses switch point
 Critical charge for upset decreases as the square of
the technology feature size
 Error rates are independent of clock frequency
51
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Single Event Transient (SET)
 Reversed biased junctions collect charge
• Combinatorial logic circuits
 Voltage transients propagate un-attenuated
• Indistinguishable from normal signals
• Incorrectly latched if arrive at a clock edge
 Critical width for un-attenuated propagation
decreases as the square of the feature size
 Error rates now depend on clock frequency
• Static CMOS: Proportional to frequency
• Dynamic CMOS: Decreases with frequency
52
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Many Types of SET Induced
Errors
DATA
D
Q
DFF
Combinatorial
Logic
D
Q
DFF
CLOCK
 Data input transients
 Clock line transients
 Asynchronous control line transients
 Synchronous control line transients
53
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OUT
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Errors Due to Data SETs
Setup Time
Hold Time
Clock
Data
Non-Latching SET
Data
Earliest-Latching SET
Window of
Vulnerability
54
Data
Latest-Latching SET
Data
Non-Latching SET
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What’s Ahead
High Speed
Device Scaling
Power
Reliability
Soft Errors
Wear Out
Degradation
55
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Oxide Wear-Out
 Oxide wearout is a time and voltage dependent oxide
breakdown
• Very little changes in transistor characteristics before failure
• Failure evolves from recoverable soft breakdown to nonrecoverable hard breakdown
56
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Device Wearout/Life Time Trend
57
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What’s Ahead
High Speed
Device Scaling
Power
Reliability
Soft Errors
Wear Out
Degradation
58
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Common Aging Failure
Mechanisms
 Hot Electron Degradation
 Negative Bias Temperature instability
 Oxide wear-out
 Electromigration
 Self-Heat
59
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Hot-E Degradation
60
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Hot-E Degradation
Trapped electron
NMOS Gate
SiO2
Ids
Source
e-h pair
Substrate hole current
Drain
spacer
SiO2
n-
n-
n+
n+
The n - region acts as a series resistor therefore the transistor’s Vds is
reduced. This lightly doped region also reduces the electric field
across the pinch-off region. (Side effect - the transistor is slower!)
61
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Hot-e Degradation
 How to reduce the hot-e degradation – partial
list
•
•
•
•
62
Decrease Cload (reduce fan out).
Speed up the input edge rate.
Avoid slowly varying output signals where possible.
Avoid capacitive coupling above VCC.
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Negative Bias Temperature
instability
 What is it?
• The P Transistor performance (Idsat, Vt) degrades as a function of
time, temperature, and voltage
• The cause is not fully understood but is believed to be caused by
dopant migration into the gate while the P-Channel is “off”
 Are all transistors effected equally?
• No. It is a function of the design.
Activity (“On” devices degrade quicker than “off” devices)
High voltage outputs degrade faster than internal devices
The temperature is not uniform across a die. “Hot spots” will
degrade quicker (i.e. clock drivers).
Analog functions dependent upon Idsat, Vt relationships
63
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Designing for NBTI
 Use “end of life” simulation files
• Suitable for digital circuits
• More area and higher power if applied indiscrimately
• First silicon can be misleading indication of success
The ASIC runs faster than expected and meets a customer’s
acceptance specs….. today…..
 AgeSim
• Intel uses a transistor age simulator to simulate transistor
behavior as it degrades over its entire life cycle (important for
analog functions)
 Intel uses a combination of AgeSim and EOL
64
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Testing for NBTI
 Burn In
• Burn In accelerates NBTI quickly
• Burn in adds to the cost
• Need to assure that burn in patterns are complex enough to be
representative of actual activity
 Guardband tester parameters with the expected
degradation
 Intel uses a combination of Burn In and Tester guard
banding
65
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Electromigration Damages
Voids
Interlayer metal voids
Hillock
ILD Crack
66
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Electro Migration Failure Mechanism

Electro Migration (EM) - migration of metal ions along the electrons flux in
case of DC currents. Causes opens and shorts in metal segments
void
(open)
e
migrated ions
(short hazard)
I
Ion motion due to momentum transfer
mostly lattice vacancies (few interstitial ions)
grain boundary is vacancy source/sink
67
•
Vacancies drift against electron wind
accumulate at cathode, deplete at anode
•
Pressure inverse to vacancy concentration
low density = high pressure (crack surrounding glass and subsequent
metal short)
high density = low pressure (coalesce into metal void and subsequent
high resistance or open circuit)
•
Electro-migration is exponentially enhanced at elevated temperatures ==>
requires strict interconnect SH rules
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EM Failure Types
(a)
(b)
(c)
(d)
(a) Open in a line (void)
(b) Short between two lines (whisker)
(c) Short between lines on different layers (hillock)
(d) Open between line and via (via void)
68
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VIA Electro Migration
• Left - voids under a via, high resistance or open circuit
• Right - ILD crack, possible short circuit with adjacent wires
e
High Resistance
Vcc
I
Damage
Electron direction
Vss
I
Electron direction
Damage
69
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EM Via Failure Calculation
 The AE (Activation Energy) changes the temperature
factor (TF).
Activation energy
TF  e
ae  1
1

k  TPr oject TBase




 Vias will use activation energy according to current
direction:
 Current up  take AE of metal below.
 Current dn  take AE of metal above.
 Temperature factor is computed per current
direction.
70
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Self-Heat
 IBM CMOS 7S
copper process,
0.16 mm
71
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Self Heat (SH)
 SH is the rise in temperature due to the electron
movement within a conductor.
 It is also known as Joule Heating, since it is related
to the power that is dissipated onto the interconnect.
 SH is dependant on bi-directional AC (Root Mean
Squared) current, since Joule heating is a result of
P=I2R.
 SH also has a Design Rule Current Density JMAX for
each layer. A SH violation occurs when J > JMAX.
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Self Heating = More EM
 Self Heating ?
More EM.
 Since SH increases temperature, self-heating on a
metal line can aggravate EM effects.
 SH on a line can also increase EM effects on
neighboring lines.
 Because self-heating contributes to electromigration, failures are typically labeled as EM, not
SH.
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