Transcript CS 2204 Fall 2005 - NYU Polytechnic School of Engineering

CS 2204
Lab 6
Digital Logic
and
State Machine Design
As you wait for the lab to start :
 Is your laptop up-to-date ?
Experiment 3
Spring 2014

Experiment 3 Lab 6 Outline
 Presentation

Digital product development overview
 Component selection for a new chip
• Xilinx component usage

Using A Brief Look at Semiconductor Technology

Analysis of the term project
 Moore’s Law, smaller transistors, their implications and potential issues
 Analysis of Block 6 of the term project (using Term Project pages 38-48)
 Implementing a machine player

A machine playing strategy
 Individual work

Experiment 3
 Develop the Rightmost Zero Display circuit of the Ppm term project
 Develop a new machine player that uses the Rightmost Zero Display
circuit

New handouts

Digital Product Development
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Presentation
 Developing a Digital Product

CS2204 sets out to develop a prototype
 A prototype chip
 A prototype PCB

If everything goes well and the product is not obsolete, it is
mass produced
 Mass produce the prototype chip
• Whoever wants to use the chip must develop a new PCB
 Mass produce the prototype PCB
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Developing a new chip
1) Development Cycle on Computers
Major error : Redesign
DESIGN
TEST
MODIFY
Major error : Redesign or terminate the project due to TTM
2) Development Cycle with FPGA chips
Mount
Test
Modify
Major error : Redesign or terminate the project due to TTM
3) Development Cycle on prototype chip
Fabricate
Test
TEST : applying input combinations,
test vectors, and simulating
During testing If you see MODIFYING
hardware to optimize it is possible, do
that after you correct logic and timing
errors. Then, test again to see if your
minimization has logic/timing errors
Mount : FPGAs are mounted on
bread/boards, wired and programmed
Test : apply test vectors to FPGAs
Modify : either FPGA mounting/wiring
is changed or a simple design change is
made on computers, simulated, then
FPGAs are programmed and tested
Fabricate chip by sending a GDSII file
to a fabrication facility : tape out
Apply test vectors to the chip
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Developing a new PCB
1) Development Cycle on Computers
Major error : Redesign
DESIGN
TEST
MODIFY
Major error : Redesign or terminate the project due to TTM
TEST : Simulating by applying input
combinations, test vectors, may not be
possible. It may be coarse grain simulation
During testing if you see MODIFYING
hardware to optimize it is possible, do that
after you correct logic and timing errors.
Then, test again to see if your minimization
has logic/timing errors
2) Dev. Cycle with off-the-shelf chips Mount : Chips are mounted on
bread/boards and wired
Mount
Test : apply test vectors to the chips
Test
Modify
Major error : Redesign or terminate the project due to TTM
3) Dev. Cycle on prototype PCB
Fabricate
Test
Modify
Modify : chip mounting/wiring is changed
and tested or a simple design change is
made on computers, simulated, then chip
mounting/wiring is changed and tested
Fabricate PCB at a fabrication facility,
mount chips and other components
Apply test vectors to the PCB
Modify means chip mounting/wiring is
changed and tested
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Developing a Digital Product
 In the lab we use the FPGA chip

In the lab, we practice how to develop a new chip
 In the classroom we discuss both
How to develop a new chip
 How to develop a new PCB

CS 2204 Spring 2014 Experiment 3 Lab 6
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
CS2204 Lab New Chip Development
Steps
1) Development Cycle on Computers

As described above
2) Development Cycle with FPGA chips

Mount : we will not mount FPGAs nor wire them


Test



We will just program FPGAs
Apply test vectors by using switches and push buttons
Observe the 7-segment displays and LED lights
Modify

A simple schematic design change is made on the
computer, simulated, then the FPGA is programmed and
tested
CS 2204 Spring 2014 Experiment 3 Lab 6
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Development Cycle
Development Cycle on Computers
with FPGA chips

Xilinx Project Development Steps Today’s work
 Develop the schematic

Design the schematic
 Design blocks, (sub)blocks
• Place the components and wires
 Do a schematic check

What are these
components ?
Test the schematic via functional simulations
 Do a Xilinx IMPLEMENTATION

It maps the components to the CLBs of the chip
 Do timing simulations to test the schematic

It generates the bit file
 Download the bit file to the FPGA and test the
design on the board

It programs the chip
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Developing a digital product
 A new chip

Which gates & FFs and how many is determined by
 The application (major operations)
 Available chips of the technology chosen
 Besides speed, cost, power, etc. : design goals


We will try to use high density components (MUXes,
decoders, adders, comparators, encoders, deMUXes,
registers, counters, shift registers) as much as possible
We will try not to use low-density components (gates and
flip-flops)
 We will work on chips design in the lab and classroom

Labs, lectures, homework assignments, the term project and
exams
CS 2204 Spring 2014 Experiment 3 Lab 6
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
CS2204 Components
 Available components for a new chip
Use these
Generic components
as much
as possible Lectures, homework, exams
Flip-flops Popular digital circuits
AND
D
OR
JK
NOT
T
NAND
SR
NOR
…
…
To save time,
space, power.
weight,…
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
High-density components
Gates
Xilinx components
Labs
Gates
AND
OR
NOT
NAND
NOR
…
Flip-flops
D
T
JK
Popular digital circuits
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
CS 2204 Spring 2014 Experiment 3 Lab 6
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Implementing a Combinational Circuit on a New Chip

 By using generic components that are AND, OR, NOT,…

The 2-to-1 MUX
Which generic components ?
1 generic inverter
2 generic 2-input AND gates
1 generic 2-input OR gate
a
Total : 4 generic components used
NOT
b
AND
OR
c
a
AND
y(a, b, c) = a.b + a.c
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Implementing a Combinational Circuit on a New
Chip
 By using generic components that are AND, OR, NOT

The 2-to-1 MUX
Use a generic 2-to-1 MUX already designed
Do not design your own 2-to-1 MUX
a
NOT
b
AND
OR
c
a
AND
y(a, b, c) = a.b + a.c
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Implementing a Combinational Circuit on a New Chip
 The 2-to-1 MUX

Use a generic 2-to-1 MUX already designed
a
Sel
c
1
b
0
Which generic components ?
2-to-1
MUX
y
1 generic 2-to-1 MUX
Total : 1 generic component used
a
NOT
b
AND
OR
c
a
AND
y(a, b, c) = a.b + a.c
CS 2204 Spring 2014 Experiment 3 Lab 6
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Implementing a Combinational Circuit on a New Chip

 By using generic components that are AND, OR, NOT,…
Which generic components ?
a
ab
2 generic inverters
5 generic 2-input AND gates
1 generic 5-input OR gate
b
a
ad
d
z
d
a
Total : 8 generic components used
ac
c
ab + ad + ac + c d + b c
c
c
cd
Output z = 1 if (a,b) > (c, d)
d
b
bc
c
2-bit Unsigned Binary Comparator
From Handout 3
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Implementing a Combinational Circuit on a New Chip
 By using generic components that are AND, OR, NOT,…
2-bit
Unsigned Binary Comparator
Use a generic comparator already designed
You need an extra NOT gate besides the comparator
Do not design your own Comparator
a
ab
b
a
ad
d
z
d
a
ac
c
c
c
cd
d
b
bc
c
CS 2204 Spring 2014 Experiment 3 Lab 6
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Implementing a Combinational Circuit on a New Chip

 2-bit Unsigned Binary Comparator

a
A1
By using a generic comparator already designed
b
c
A0
B1
d
B0
2-bit Unsigned Binary Comparator
Which generic components ?
1 generic 2-bit Unsigned Comparator
1 generic NOT gate
Total : 2 generic components used
AGTB
AEQB
ALTB
z
Output z = 1 if (a,b) > (c, d)
CS 2204 Spring 2014 Experiment 3 Lab 6
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
CS2204 Components
Lab design
 Available components for a new chip
Gates Flip-flops
AND
OR
NOT
NAND
NOR
…
D
JK
T
SR
Popular digital circuits
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
Xilinx components
Labs
Gates Flip-flops Popular digital circuits
AND
OR
NOT
NAND
NOR
…
D
T
JK
Try not to use
these components
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
CS 2204 Spring 2014 Experiment 3 Lab 6
High-density components
Generic components
Lectures, homework, exams
Use Xilinx macros
as much as possible
Page 17

Implementing a Combinational Circuit on a New Chip
 By using Xilinx components that are AND, OR, NOT,…

The 2-to-1 MUX
1 inverter, INV
2 2-input AND gates, AND2
1 2-input OR gate, OR2
Which Xilinx components ?
Total : 4 Xilinx components used
a
NOT
b
AND
OR
c
a
AND
y(a, b, c) = a.b + a.c
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Implementing a Combinational Circuit on a New
Chip
 By using Xilinx components that are AND, OR, NOT,…

The 2-to-1 MUX
Xilinx already has 2-to-1 MUXes
Use them
Do not design your own 2-to-1 MUX
a
NOT
b
AND
OR
c
a
AND
y(a, b, c) = a.b + a.c
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Implementing a Combinational Circuit on a New Chip
 The 2-to-1 MUX

Xilinx already has 2-to-1 MUX macros
 M2_1
Which Xilinx components ?
1 Xilinx M2_1 MUX
a
Total : 1 Xilinx component used
NOT
b
AND
OR
c
a
AND
y(a, b, c) = a.b + a.c
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Implementing a Combinational Circuit on a New Chip
 By using Xilinx components that are AND, OR, NOT,…
Which Xilinx components ?
a
2 inverters, INV
5 2-input AND gates, AND2
1 5-input OR gate, OR5
ab
b
a
Total : 8 Xilinx components used
ad
d
z
d
a
ac
c
c
c
cd
ab + ad + ac + c d + b c
Output z = 1 if (a,b) > (c, d)
d
b
c
bc
2-bit Unsigned Binary Comparator
From Handout 5
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 21

Implementing a Combinational Circuit on a New Chip
 By using Xilinx components that are AND, OR, NOT,…
2-bit
Unsigned Binary Comparator
Use them
Xilinx already has Comparators
You need an extra NOT gate besides the comparator
Do not design your own Comparator
a
ab
b
a
ad
d
z
d
a
ac
c
c
c
cd
d
b
bc
c
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Implementing a Combinational Circuit on a New Chip
 2-bit Unsigned Binary Comparator

By using Xilinx comparators
1 2-bit Comparator, COMPM2
1 NOT gate, INV
Total : 2 Xilinx components used
Which Xilinx components ?
Output z = 1 if (a,b) > (c, d)
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Silicon Technology and Moore’s Law
 Number of transistors on a chip doubles every two years

Because transistors are becoming smaller !
 We will continue to shrink size of transistors !
 We will continue to double the number of transistors

NVIDIA TESLA K40 GPU chip : 7.1 Billion transistors
World’s
densest chip
7.1 Billion
transistors
28 nm process
A 2-D chip with 2-D transistors
NVIDIA TESLA K20 GPU chip
has 7.08 Billion transistors
3-D transistors
increase the transistor
density per chip
3-D chips increase
the transistor
density per chip
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Silicon Technology and Moore’s Law
 Number of transistors on a chip doubles every two years

Because transistors are becoming smaller !
 We will continue to shrink size of transistors !
 We will continue to double the number of transistors

The transistor size depends on process length
 There are chips with shorter process lengths now or later this year
•
•
•
•
•
•
Micron 128-Gbit Flash memory : 16 nm (16x10-9 meter)
Samsung 128 Gbit Flash memory : 19nm (19x10-9 meter)
Xilinx Virtex UltraScale, VU 440 : 20nm (20x10-9 meter)
Xilinx Virtex UltraScale : 16nm (16x10-9 meter)
Altere Arria 10 FPGA chip : 20nm (20x10-9 meter)
Altera Stratix 10 FPGA chip : 14nm (14x10-9 meter)
3-D transistors
increase the transistor
density per chip
3-D chips increase
the transistor
density per chip
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Silicon Technology and Moore’s Law
 Number of transistors on chips doubles every two years

Micron Automata Processor : Processor & memory are one chip !
 For high speed search and analysis across massive, complex,
unstructured data

Intel Knights landing microprocessor : 2015 !
 72 cores !
Micron Automata Processor die
Intel Knights Landing die
3-D chip with DRAM dice stacked
up on the processor chip
14 nm process
A 3-D chip with 3-D
(FinFet) transistors
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Silicon Technology and Moore’s Law
 Number of transistors on chips doubles every two years

3-D chips ?
 Monolithic 3-d chips
• One die but with layers on top of each other
• Many connections between the layers
 Die-on-die
• Dice stacked up
• Less number of connections via Through-Silicon Vias (TSVs)
Samsung 3-D Vertical 128Gbit
Flash EPROM with 24 layers
Xilinx Virtex-7 2000T FPGA
IBM’s conception
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Silicon Technology and Moore’s Law
 Number of transistors on chips doubles every two years

3-D chips ?
 Hybrid Memory Cube (HMC) !
• Multiple dice stacked up
• There are logic and memory dice stacked up : Hybrid
 Micron has 2GByte DRAM chips : 4 stacks of 4 Gbit DRAMs
 Micron will have 4GByte DRAM chips this year !
Samsung model
HMC
Hybrid memory Cube
TSVs
TSVs
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
Silicon Technology and Moore’s Law
 Advantages of smaller transistors
1.
Smaller transistors are faster
2.
Smaller transistors consume less power
3.
More transistors are packed in the same area
 Digital circuits are faster
 Clock frequency is increased
 Digital circuits consume less power
 Batteries are charged less frequently
 More functionality on the chip
 Smaller devices
3-D transistors
increase the transistor
density per chip
3-D chips increase
the transistor
density per chip
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Silicon Technology and Moore’s Law
 Issues with smaller transistors
1. Smaller transistors will be susceptible to alpha particles, neutrons
 Soft errors !
•
Programs crash if we do not detect faults !
2. More transistors will be defective
 Programs do not run if we do not test chips well
•
Design for testing !
3. Narrower wires result in longer wire delays
 Timing delays result in slower circuits to avoid faulty results
•
Locally synchronous but globally asynchronous chips may be needed
4. Hardware security will be a concern
 Hardware trojans inserted during design/fabrication !
•
We must develop prevention and testing mechanisms
5. Higher clock frequencies result in higher heat generation
 Power consumption increases with clock frequency
•
Heat generation increases with power consumption
•
•
A combination of heat sink, fans and liquids are used to cool chips
Nanotubes inserted to chips will circulate water to cool chips in the future
 Chips melt if we do not cool them !
3-D transistors increase the
transistor density per chip
3-D chips increase the
transistor density per chip
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Analysis of the Term Project
 Polytechnic Playing Machine, Ppm

The term project is human vs. machine
 The black-box view
From the input devices
13
19
Ppm
To the output devices
Figure 1. The Ppm black box view.
From page 2 of the Term Project Handout
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 31
Reset mode
(Initial state)
Player 1 presses BTN3, P1play, four times to play
Player 1 turns on SW0 if wanted. Player 1 turns on and off one
of SW7-SW4 to select a position. Player 1 turns off SW0 if on
2
Player 1 points being calculated !
3
If one of SW7-SW4 is on
in state 3, a random digit
is input for the machine
player from SW3-SW0
when BTN2 is pressed
Player 1 examines the s ituation !
Player 1 presses BTN3, P1play,
Player 1 presses BTN2, P2play,
to allow the machine player to play
to allow herself to play again if
there is an adjacency
4
Player 2 thinks !
r2
Playe
skips p
lay
Player 2 plays on a pos ition
5
Player 2 points being calculated !
6
Player 1 examines the situation !
Player 1 can press BTN3, Reset, in any
state to return to the Reset state, State 0
Player 1 presses BTN3, P1play,
to allow hers elf to play
Player 1 can press BTN4, Shpts, in any state to see players’ points
pr esse s
la y
P laye r 1 pla y, to skip p
, P2
2
N
T
B
From page 8 of the Term Project Handout
Player 1 can press BTN3, P1play,
in state 1 or 3 to see next two RDs
Player 1 press es BTN2, P2play,
to allow the machine player to
play again if there is an adjacency
Ppm
operation
diagram
The game is reset : 0 points for players, 0s on position displays !
Player 1 thinks !
Player 1 mode
(Player 1 plays)
Ppm
Input/output
relationship
0
1
Player 2 mode
(Player 2 plays)
LD0-LD2 on the
FPGA board
show the
current state
Download to the FPGA chip
Figure 5. The operation diagram of Ppm.
CS 2204 Spring 2014 Experiment 3 Lab 6
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
The Ppm Term Project
 Ppm is a digital system !
From the input devices
19
13
Ppm
To the output devices
Figure 1. The Ppm black box view.
 The Ppm term project partitioning

First partitioning of the digital system
 Control Unit
 Data Unit

core
Second partitioning (Data Unit partitioning)





Interfacing to the input/output devices core
Handling human player’s play core
Controlling display operations based on game rules core
Calculating new player points core
Determining the machine player play non-core
CS 2204 Spring 2014 Experiment 3 Lab 6
Page
33

The Ppm Digital System Partitioning
From page 9 of the Term Project Handout
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 34

Machine Play Block, Block 6
 How is it designed ?

Machine player gathers information and then decides
 It must have inputs to gather information
• The number of inputs depends on the strategy
• But, a few inputs are required for some strategies
 It must have outputs to be able to play the game
• The number of outputs depends on the strategy
• But, a few outputs are required for any strategy
?
Block 6
?
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Machine Play Block, Block 6
 How is it designed ?

Machine player gathers information and then decides
 It must have a subblock to gather information
• Information gathering is a major operation
 It must have a subblock to decide how to play
• Decision making is another major operation
 Any other subblock (major operation) ?
?
Block 6
?
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 36

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip

Machine player stays at least one clock period in state 4 to
gather information and decide

It stays more than one clock period since gathering information is
done sequentially

Because the information needed is not available all at once and so
must be collected one by one
•

The loop-back arrow indicates that more than once clock period is spent
in state 4
Collecting information could be done in parallel
•
But, it would require a lot of hardware !
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip

Machine player stays at least one clock period in state 4 to
gather information and decide

It stays more than one clock period since gathering information is
done sequentially


It collects the information in eight clock periods and then in one
more clock period it plays
The course web site machine player collects information for 8 clock
periods and decides to play/skip in the 9th clock period !
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip

The course web site machine player collects information for 8
clock periods and decides to play/skip in the 9th clock period !
Information
Gathering
Subblock
Decision
Making
Subblock
Any other major operation ?
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 39

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip

Machine player stays at least one clock period in state 4 to
gather information and decide

It stays more than one clock period since gathering information is
done sequentially

We need a controlling major operation to determine the sequence of
information gathering and then deciding !
•
•
A controller subblock is needed in addition to the information gathering
and decision making blocks !
Since the machine player is a complex sequential circuit with a controller
then Block 6 is a tiny digital system itself
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 40

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip

Machine player stays at least one clock period in state 4 to
gather information and decide

A controller subblock is needed in addition to the information
gathering and decision making blocks !

Since the machine player is a complex sequential circuit with a
controller then Block 6 is a tiny digital system itself
Block 6
Information
Gathering
Decision
Making
Sequencing
Data Unit
Control Unit
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 41
Machine Play Block, Block 6
 The implementation at the course web site
70
Block 6
15
CS 2204 Spring 2014 Experiment 3 Lab 6
From page 40 of the Term Project Handout

Page 42

Machine Play Block, Block 6
 The implementation at the course web site
Decision making
M2
Information gathering
Sequencing
M4
M3
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 43

Machine Play Block, Block 6
 The implementation at the course web site

The inputs
P1PT is Player 1 points
P2PT is Player 2 points
RWD is the regular reward points
RD is the random digit
DISP is the four displays
NSD is the adjacency
R1D is the next random digit
BRWD is the digit played
CODERWD is the code reward points
PSEL indicates on which position
the current player played
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Machine Play Block, Block 6
Means at least one of them must be used
 The implementation at the course web site

The inputs
Means must be used
P2sturn is 1 when it is Player 2 to play
Stp2pt stores Player 2 points,
here used to increment a
counter to check if Player 2
has played 3 times or less
Clearp2ffs stores 0 on
registers, counters and
FFs after Player 2 plays
Clear stores 0 on registers,
counters and FFs after reset
Sysclk is the system clock at 6 Hz
P2clk is the Player2 clock at 48 Hz
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip

It stays more than one clock period if gathering information is
done sequentially

The required inputs if it stays more than one clock period

Other inputs are needed to gather information
P2sturn
.
.
.
Block 6
Clearp2ffs
P2clk
CS 2204 Spring 2014 Experiment 3 Lab 6
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
Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip
Today !

Machine player stays at least one clock period in state 4 to
gather information and decide

If the information needed is available all at once, then the
machine player stays one clock period in state 4

It collects the information and decides to play/skip in one clock
period !
•

The loop-back arrow is not needed then !
Today’s machine player is a very simple one and so takes only one
clock period !
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 47

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip
Today !

Machine player stays at least one clock period in state 4 to
gather information and decide

If the information needed is available all at once, then the
machine player stays one clock period in state 4

We do not need a controlling major operation to determine the
sequence of information gathering and then deciding !
•
•
A controller block is not needed in addition to the information gathering
and decision making blocks !
The machine player is a combinational circuit that gathers information
and decides how to play
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 48

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip
Today !

Machine player stays at least one clock period in state 4 to
gather information and decide

If the information needed is available all at once, then the
machine player stays one clock period in state 4

Since the machine player is a combinational circuit, there are only
two subblocks in Block 6
Block 6
Information
Gathering
Decision
Making
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 49

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip
Today !

The machine player stays one clock period in state 4

There is no required input if it stays one clock period

But, other inputs are needed to gather information
.
.
.
.
Block 6
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 50

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip

How can the machine player indicate how it plays after
collecting information and deciding (taking one or more clock
periods) ?

It needs to have outputs to indicate its decision


If it decides to play the random digit
•
•
•
Output lines to indicate which position : P2SEL
An output line to indicate whether it is an addition or direct play : P2add
An output line to indicate that it is playing, not skipping : P2played
•
An output line to indicate it is skipping : P2skip
If it decides to skip
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 51

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip

How can the machine player indicate how it plays after collecting
information and deciding (taking one or more clock periods) ?

It needs to have outputs to indicate its decision

The required outputs whether it stays one clock period or longer
•
Other outputs may be needed for the strategy, but not recommended
4
P2SEL
P2add
Block 6
P2played
.
.
P2skip
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 52

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip

It needs to have outputs to indicate its decision

The required outputs whether it stays one clock period or longer
4
P2SEL
P2add
Block 6
P2played
.
.
P2skip
P2SEL has a 1 corresponding to the
position played when the machine
player plays the random digit
P2add is 1 if the machine player
adds the random digit to a display
P2played is 1 if the machine player
plays the random digit on a display
P2skip is 1 if the machine
player skips the plays
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 53

Machine Play Block, Block 6
 The implementation at the course web site

The outputs
70
Block 6
15
The 7 required outputs to be
generated no matter what the
playing strategy is
P2CODE outputs the code
digits that are discovered
by the machine player
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 54

Machine Play Block, Block 6
 The implementation at the course web site

The outputs
70
Block 6
15
P2CODE outputs the code digits
that are discovered by the
machine player
If the strategy does not check
for code digits, P2CODE outputs
must be connected zero to avoid
unnecessary warnings
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 55

Machine Play Block, Block 6
 Let’s design a simple machine player

To design it we must have a playing strategy !
 We develop a machine player strategy then !
There is a zero display ?
N
Y
Play on the
(rightmost)
zero position
directly
(Action 1)
Skip
(Action 0)
?
A very simple
playing strategy !
Block 6
?
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 56

Machine Play Block, Block 6
 To design it we must have a playing strategy !

We develop a machine player strategy then !
There is a zero display ?
A very simple
playing strategy !
N
Skip
(Action 0)
Y
Play on the
(rightmost)
zero position
directly
(Action 1)
We need to collect only the display values : DISP
We input 16 bits : DISP15 – DISP0
?
Block 6
?
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 57

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip
Today !

Machine player stays at least one clock period in state 4 to
gather information and decide

If the information needed is available all at once, then the
machine player stays one clock period in state 4

The DISP lines are available all at once, so no need to have more than
one clock period
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 58

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip
Today !

The DISP information is available all at once, and so the
machine player stays one clock period in state 4

We do not need a controlling major operation to determine the
sequence of information gathering and then deciding !

The machine player is a combinational circuit that gathers
information and decides how to play
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 59

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip
Today !

The DISP information is available all at once, and so the
machine player stays one clock period in state 4

Block 6
Since the machine player is a combinational circuit, there are only
two subblocks in Block 6
Information
Gathering
Decision
Making
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 60

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip
Today !

The machine player stays one clock period in state 4

DISP
It needs 16 DISP lines to be input
16
Block 6
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 61

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip
Today !

How can the machine player indicate how it plays after
collecting information and deciding ?

It needs to have outputs to indicate its decision

The required outputs
•
•
•
•
P2SEL
P2add
P2played
P2skip
4
P2SEL
P2add
Block 6
P2played
.
.
CS 2204 Spring 2014 Experiment 3 Lab 6
P2skip
Page 62

Machine Play Block, Block 6

The machine player is active in state 4 to think and play/skip
Today !

The black box view of the machine player
4
DISP
16
Block 6
P2SEL
P2add
P2played
P2skip
We must also output 8 P2CODE
lines to avoid unnecessary warnings
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 63

Machine Play Block, Block 6

The design of the machine player that is completely
combinational

The partitioning of the machine player block
4
DISP
16
Information
Gathering
P2SEL
P2add
Decision
Making
P2played
P2skip
8
P2CODE
Block 6
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 64

Machine Play Block, Block 6

The design of the machine player that is completely
combinational

The Information Gathering Subblock
DISP
16
Aposzero
M3
2
ZERODISP
Information
Gathering
Already designed in class
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 65

Machine Play Block, Block 6

The design of the machine player that is completely
combinational

The Decision Making Subblock
4
Aposzero
ZERODISP
P2SEL
P2add
2
Decision
Making
P2played
P2skip
8
P2CODE
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 66

Machine Play Block, Block 6

Generating P2skip output

P2skip is 1 when there is no zero display

P2skip is 1 when Aposzero is 0
P2skip = Aposzero
Aposzero
P2skip
4
Aposzero
ZERODISP
P2SEL
P2add
2
Decision
Making
P2played
8
P2skip
P2CODE
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 67

Machine Play Block, Block 6

Generating P2played output

P2played is 1 when there is a zero display

P2played is 1 when Aposzero is 1
P2played = Aposzero
Aposzero
P2played
4
Aposzero
ZERODISP
P2SEL
P2add
2
Decision
Making
P2played
P2skip
8
P2CODE
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 68

Machine Play Block, Block 6

Generating P2add output

Player 2 always plays directly on zero display

P2add is always 0
P2add = 0
P2add
0
4
Aposzero
ZERODISP
P2SEL
P2add
2
Decision
Making
P2played
P2skip
8
P2CODE
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 69

Machine Play Block, Block 6

Generating P2SEL outputs

P2SEL outputs are determined by ZERODISP inputs

We need to convert the 2-bit ZERODISP lines to 4 P2SEL lines
•
We need a 2-to-4 decoder !
Y3
I1
ZERODISP1
I0
ZERODISP0
P2SEL3
Y2
2-to-4
Decoder
P2SEL2
Y1
P2SEL1
Y0
P2SEL0
4
Aposzero
ZERODISP
P2SEL
P2add
2
Decision
Making
P2played
P2skip
8
P2CODE
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 70

Machine Play Block, Block 6

Generating P2CODE outputs

P2CODE outputs are always zero
0
P2CODE7
0
P2CODE6
0
P2CODE5
0
P2CODE4
0
P2CODE3
0
P2CODE2
0
P2CODE1
0
P2CODE0
4
Aposzero
ZERODISP
2
P2SEL
P2add
Decision
Making
P2played
P2skip
8
P2CODE
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 71

Machine Play Block, Block 6

The design of the machine player that is completely combinational

The Decision Making Subblock
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 72

Machine Play Block, Block 6

The design of the machine player that is completely combinational
Information Gathering
Decision
Making
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 73

Machine Playing Strategies
 Teams have to come up with a primary playing
strategy before they can design their machine player

A playing strategy is shown as a graph and consists of
 Conditions shown as ovals
• Game situations
 Actions shown as rectangles
• Playing the random digit on a display
• Skipping the plays

The graph is NOT with respect to time
 The graph is with respect to game situations !
 Teams must also have to come up with a secondary
strategy to resolve game situations where the
primary playing strategy results in multiple playable
positions
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 74

Playing Strategy of Player 1 of Ppmmvsm
 Its Implementation
Play on the
(rightmost)
largest
regular
reward
position
(directly if
equal)
(Action 0)
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 75

A Machine Player Strategy
Largest regular reward = 0 ?
Play on the
(rightmost)
largest
regular
reward
position
(directly
if equal)
(Action 0)
N
Y
Skip
Are all displays zero and
the random digit is 0 ?
448C
4
 44CC
E233
1
 F233
DFFD
2
 DFFF
0000
0
 Skip
 There are two actions and one condition

The primary strategy is playing on the largest regular
reward position if all displays are not zero
 No checking for code digits !

The secondary strategy is playing on the rightmost of
equally playable (largest regular reward) position directly
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 76

A Machine Player Strategy
 Its Implementation
Largest regular reward = 0 ?
N
Play on the
(rightmost)
largest
regular
reward
position
(directly
if equal)
(Action 0)
CS 2204 Spring 2014 Experiment 3 Lab 6
y
Skip
Page 77

Playing Strategy of Term Project machine player
 Its Implementation
Decision making
Information gathering
Sequencing
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 78

Assignment by next lab
 Make sure that you have completed Experiment 1,
Experiment 2 and Experiment 3
 Your Experiment 3 will be collected and graded
 The last day to submit Experiment 2 as a team is
March 7, 2014
 The last day to submit Experiment 3 as a team is
March 14, 2014
 It will be graded and returned by the following lab
Submit your Experiment 3 during a lab session !
Not during Open Lab Hours !
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 79
Make sure you have the LABS account and see the S drive
Make sure you have installed WebPACK 12.4 on your laptop
Make sure you create a CS2204 folder on both
Read slides at the end to learn about the software, Project Manager,
Schematic design and other related topics
Do not leave the lab before your partners finish
► Help your partners
QUESTIONS ?
Continue
reading the
Term
Project
handout
Digital
Logic
and
State Machine Design
Think about
the machine
player
strategy
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 80

Today’s Individual Xilinx Work
 We will continue to study (analyze) the term
project

We will develop the rightmost zero display circuit
of the Ppm term project in Block 6, based on our
classroom discussion on it and develop a simple
machine player : Experiment 3
 We will replace Macro 3 (M3) in Block 6 with our own
circuits
 We will develop a machine player with one condition and
two actions
 Help our partners complete today’s project
 We will continue reading the Term Project
handout

Also read slides at the end
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 81

Today’s Individual Xilinx Lab Work
1. Open the ppm project in the exp2 folder
a) Open the Project Manager and then open
the Ppm project in the exp2 folder
b) Look at the six Ppm schematics
c) Enter the team information to the schematics if
it has not been entered

Save the schematic if the team information is entered
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 82
Today’s Individual Xilinx Lab Work

1.
Open the ppm project in the exp2 folder
d)
Make sure Experiment 1 and Experiment 2 are completed

That is on screen you have the following :
Experiment 1
Experiment 2
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 83

Today’s Individual Xilinx Lab Work
1.
Open the ppm project in the exp2 folder
d) Make sure Experiment 1 and Experiment 2 are completed

If they are not complete finish the designs by studying


Lab 4 presentation for Experiment 1
Lab 5 presentation for Experiment 2
•
So that eventually Block 3 looks like as follows :
Make sure your circuits in
Block 3 follow the Term
Project Check List handout
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 84

Today’s Individual Xilinx Lab Work
1.
Open the ppm project in the exp2 folder
d)
Make sure Experiment 1 and Experiment 2 are completed

If they are not complete finish the designs by studying
•
Lab 4 presentation for Experiment 1 so that the new circuit looks like as follows :
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 85

Today’s Individual Xilinx Lab Work
1.
Open the ppm project in the exp2 folder
d)

Make sure Experiment 1 and Experiment 2 are completed
If they are not complete finish the designs by studying

Lab 5 presentation for Experiment 2 so that a portion of the new circuit looks
like as follows :
NPDISP15
Pd3prd
1-bit ADDer implemented by gates !
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 86

Today’s Individual Xilinx Lab Work
1.
Open the ppm project in the exp2 folder
d)
Make sure Experiment 1 and Experiment 2 are completed

If they are not complete finish the designs by studying
•
Lab 5 presentation for Experiment 2 so that a portion of the new circuit looks like as follows :
DISP14
RD2
RD1
RD0
DISP13
DISP12
3-bit ADDer
implemented by
a 4-bit ADDer
NPDISP12
NPDISP13
C3
NPDISP14
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 87

Today’s Individual Xilinx Lab Work
1.
Open the ppm project in the exp2 folder
d) Make sure Experiment 1 and Experiment 2 are completed
 So that eventually Block 3 looks like as follows :
Make sure your circuits in
Block 3 follow the Term
Project Check List handout
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 88

Today’s Individual Xilinx Lab Work
2.
Submit the Experiment 2 project after deciding
whose project is the best to submit

Decide whose project on the team will be submitted

Block 3 must look like as follows :
Experiment 1
Make sure your circuits
follow the Term Project
Check List handout
Experiment 2
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 89

Today’s Individual Xilinx Lab Work
2.
Submit the Experiment 1 project after deciding whose
project is the best to submit

Fill out a Term Project Check List handout before signaling to the
TA

Block 3 must look like as follows :
Experiment 1
Make sure your circuits
follow the Term Project
Check List handout
Experiment 2
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 90

Today’s Individual Xilinx Lab Work
3. By using Microsoft and Xilinx ISE create
exp3 from the exp2

Remember that we must create a new project
from an earlier one by using Microsoft and Xilinx
ISE

We will experiment with the Ppm schematics
4. Open the Ppm project in exp3
5. Look at the six Ppm schematics

If it has not been entered, place your team info
on the schematics

Save the schematic if you enter the team information
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 91

Today’s Individual Xilinx Lab Work
6. Switch to schematic 6
7. Zoom into the lower left area, containing
M3
8. There is a custom macro designed by the
professor

It has three outputs


Two outputs that indicate the number of the rightmost
zero position : ZERODISP
An output to indicate a display is zero : Aposzero
•

If there are no zero displays, it is 0
See Block 6 on next two slides
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 92
Today’s Individual Xilinx Lab Work


Ppm Schematic 6
Macro 3
M3
CS 2204 Spring 2014 Experiment 3 Lab 6
Page
93
Today’s Individual Xilinx Lab Work


Ppm Schematic 6
The rightmost zero position
is indicated by ZERODISP
If Aposzero is zero,
do not use ZERODISP
If a position is zero is
indicated by Aposzero
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 94

Today’s Individual Xilinx Lab Work
9. Analyze the macro to determine how it is
used

See the correspondence between the classroom
discussion and M3 inputs and outputs

Search for the inputs and outputs of the macro



Determine which components generate the inputs
•
DISP
•
ZERODISP1, ZERODISP0 and Aposzero
•
•
•
•
Select the Nets mode
Select With Name
Enter Disp15 and then press Enter
The software will automatically switch to the first schematic
that has the wire and show the wire in yellow
Determine which components use outputs
To search for a wire click on Edit -> Find… or press Ctrl+F to
find the wire with a name
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 95

Today’s Individual Xilinx Lab Work
9. Analyze the macro to determine how it is used

Do a Hierarchy Push and notice that its implementation
cannot be shown by Xilinx


A window will pop up indicating that its internal structure
cannot be shown
Click on No to close the window
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 96

Today’s Individual Xilinx Lab Work
9.
Analyze the macro to determine how it is used

The macro is needed by the machine player strategy
It checks if
there is a
position which is
zero, besides
other conditions
If yes (Aposzero
must be 1), it plays
on the rightmost
zero position
directly
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 97

Today’s Individual Xilinx Lab Work
9.
Analyze the macro to determine how it is used

The macro is needed by the machine player strategy
If yes
It plays on the
rightmost
zero position
directly
1) A position is zero
(Aposzero = 1)
and
2) RD is not zero
and
3) There is no adjacency
and
4) The machine player is
playing one its first
three plays in the game
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 98

Today’s Individual Xilinx Lab Work
9.
Analyze the macro to determine how it is used

The macro is needed by the machine player strategy
In order to determine if a
position is zero it checks
the value of Aposzero
In order to determine
which position is the
rightmost zero position,
it checks ZERODISP
CS 2204 Spring 2014 Experiment 3 Lab 6
Page 99

Today’s Individual Xilinx Lab Work
10. Delete the macro : M3 in schematic 6
 Do not delete the wires
 Save the schematic

See modified Block 6 on the next slide
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 100
Today’s Individual Xilinx Lab Work


Ppm Block 6
Macro 3, M3,
deleted
CS 2204 Spring 2014 Experiment 3 Lab 6
Page
101

Today’s Individual Xilinx Lab Work
11. Draw the schematic of the macro in the same area
in schematic 6 by using classroom discussions and
your design

You will implement the ZERODISP1, ZERODISP0 and Aposzero
outputs by using gate networks



First draw the complete schematic on a sheet of paper by
using your class notes
Compare your schematic with your partners’ and make sure
the schematic is correct before you start the design on your
computer
Draw the schematic on your computer based on your design on
the sheet

•
•
•
You will use the Add Symbol button on the leftmost side (or
Ctrl+M) to get the component list
You will use the Add Wire button on the leftmost side (or
Ctrl+W) to draw wires
To rotate components right press ctrl-r
Note, wires cannot be rotated
 But, by pulling from one end of a wire, it can be rotated !
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 102

Today’s Individual Xilinx Lab Work
11. Draw the schematic of the macro in the same area in
schematic 6 by using classroom discussions and your design
Implement
Macro 3,
M3, in this
area
Make sure your circuits in
Block 3 follow the Term
Project Check List handout
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 103

Today’s Individual Xilinx Lab Work
11. Draw the schematic of the macro in the same area
in schematic 6 by using classroom discussions and
your design

Draw the schematic based on your design on the sheet

•
•
•

You will use the Add Symbol button on the leftmost side
(or Ctrl+M) to get the component list
You will use the Add Wire button on the leftmost side
(or Ctrl+W) to draw wires
To rotate components right press ctrl-r
Note, wires cannot be rotated
 But, by pulling from one end of a wire, it can be rotated !
Label the wires (inputs and outputs) based on your
analysis in part (9)
•
Label the outputs of the NOR gates as discussed in class
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 104

Today’s Individual Xilinx Lab Work
11. Draw the schematic of the macro in the same area
in schematic 6 by using classroom discussions and
your design



Label the components
Determine that there is no component labeled U289 and
above
How can I search for a component in the schematics, for
example, to search for component U289 ?
•
•
•
•
•
To search for components click on Edit -> Find… or press Ctrl+F
to find the component with a label
Select the Instance mode
Select With Name
Enter U289 and then press Enter
The Xilinx software will not show any component meaning there
is no component labeled U289
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 105

Today’s Individual Xilinx Lab Work
11. Draw the schematic of the macro in the same area
in schematic 6 by using classroom discussions and
your design


Label the components
Determine that there is a component labeled U288
•
•
•
•
•


To search for components click on Edit -> Find… or press Ctrl+F
to find the component with a label
Select the Instance mode
Select With Name
Enter U288 and then press Enter
The Xilinx software will switch to Block 3 and show the 4-bit
ADDer on the lower right side in a yellow rectangle
 Label the gates starting at U289
 The last component label for the macro is U297
Save the schematic
See modified Block 6 on the next slide
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 106
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Today’s Individual Xilinx Lab Work
11. Draw the schematic of the macro in the same area in
schematic 6 by using classroom discussions and your design
Macro 3, M3,
implemented
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 107
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Today’s Individual Xilinx Lab Work
12. Do a schematic check on the new design
 The schematic check is to see if there
are simple errors to catch on all
schematics

Select Tools  Check Schematic
• The Console panel will indicate that there
are no errors but three warnings
 See the next slide
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 108
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Today’s Individual Xilinx Lab Work
12. Do a schematic check on the new design
 The schematic check is to see if there are simple errors
to catch on all schematics
 Read the bottom portion of the Console panel for warnings and
correct them if there are any
 We see the same warnings as the 4-bit ADDer case

The warnings are about
•
•
•


The unused wire attached to GND in Block 2 where GND was supplying the
Enable input to the deleted MUX, XLXN_88
An unused (unconnected) output in Block 4, RDC0
The unused wire attached to GND in Block 4 where GND was supplying the
CI input to the deleted ADD4 component, XLXN_11261
The three warnings are OK since we do not need these outputs
We will ignore these unneeded output warnings and decide there is
nothing to correct
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 109
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Today’s Individual Xilinx Lab Work
12. Do a schematic check on the new design
The schematic check is to see if there are simple errors
to catch on all schematics



You might wonder how the project works if wires are not connected to
outputs nor inputs
• The Xilinx software integrates all the schematics during its
implementation
• If the wire names are the same, it would not matter where the
wires are placed, the software connects them internally
Schematic checks do not catch all the errors
 That is why after the Schematic checks we have to
perform
 Functional simulations
 Xilinx IMPLEMENTATIONs
 Timing simulations
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 110
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Today’s Individual Xilinx Lab Work
13. Perform functional simulations on this macro in
schematic 6 to verify that it is working

Note that to do functional simulations, you must perform a
synthesis
You will see that there are 140 warnings, many of them new
due to copying this project from exp2
ReRun the synthesis so that you eliminate most of the new
warnings
There will be 66 warnings after the second synthesis
Note that in Experiment 2 we also had 66 warnings
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 111
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Today’s Individual Xilinx Lab Work
13.
Perform functional simulations on this macro in schematic 6 to verify
that it is working

You will confirm the input/output relationship of the macro

Select the wires as follows :
•
•
DISP as inputs
Aposzero and ZERODISP as the three output lines
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 112
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Today’s Individual Xilinx Lab Work
13. Perform functional simulations on this macro
in schematic 6 to verify that it is working

Use your operation table that was studied in the classroom


You can start with the following values to simulate
•
•
•
•
•
•
DISP = A0E1  Aposzero = ? ; ZERODISP1, ZERODISP0 = ?
DISP = 0C80  Aposzero = ? ; ZERODISP1, ZERODISP0 = ?
DISP = 290D  Aposzero = ? ; ZERODISP1, ZERODISP0 = ?
DISP = 4F97  Aposzero = ? ; ZERODISP1, ZERODISP0 = ?
DISP = 06F1  Aposzero = ? ; ZERODISP1, ZERODISP0 = ?
Use the classroom input combinations
See the next slide
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 113
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Today’s Individual Xilinx Lab Work
13.
Perform functional simulations on this macro in schematic 6 to verify
that it is working
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Today’s Individual Xilinx Lab Work
13. Perform functional simulations on this macro in
schematic 6 to verify that it is working



Come up with other input combinations to test the macro
further
If you catch errors correct them on schematic 6
Before completing this step, make sure the circuit in
schematic 6 is beautified and the schematic is saved again
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 115
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Today’s Individual Xilinx Lab Work
14. Perform a Xilinx IMPLEMENTATION
•
Xilinx IMPLEMENTATION is required after a schematic
is changed
•
•
•
When we indicate IMPLEMENTATION we mean Synthesis,
Implement Design and Generate Programming File steps we
see on the Project Navigator window
Since we changed schematic 6 we have to do a Xilinx
IMPLEMENTATION
Xilinx IMPLEMENTATIONS are needed for three reasons



Catching more errors not discovered via schematic checks
and functional simulations as the software analyzes the
schematics
Catching even more errors by doing timing simulations
possible after the Xilinx IMPLEMENTATION
Creating a new bit file
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 116
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Today’s Individual Xilinx Lab Work
14. Perform a Xilinx IMPLEMENTATION
•
Xilinx IMPLEMENTATION maps the schematics to the
FPGA resources (CLBs and wires)

•
If the mapping is complete then there are no errors but
there can be warnings
• Mapping allows real components to be considered, hence
timing simulations
Xilinx IMPLEMENTATION consists of 3 major steps
•
•

Synthesis to translate the schematic to a netlist file after
converting the schematic to a VHDL file
Implement Design which consists of
• Translate, Map, Place & Route
Generate Programming File to generate the bit file
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 117
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Today’s Individual Xilinx Lab Work
14. Perform a Xilinx IMPLEMENTATION


Click on Design Summary (out of date) to be able to see number
of errors and warnings
Right click on Generate Programming File and select Rerun All


We will do the Synthesis, Implement Design and Generate Programming File
steps altogether
•
Even though we already did the synthesis, we will do it again to get
practice on this as we will do it many times
Wait until the IMPLEMENTATION completes
•
If it does not complete, it stops at one of the steps
 We have to read the errors on the Design Summary panel


Once completed, there are no marks next to any one of the steps
just performed
See the Project Navigator window on the next slide
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 118

14.
Today’s Individual Xilinx Lab Work
Perform a Xilinx IMPLEMENTATION

The Project Navigatorwindow looks like this after the
IMPLEMENTATION is completed successfully :
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 119
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Today’s Individual Xilinx Lab Work
14. Perform a Xilinx IMPLEMENTATION

For the current IMPLEMENTATION we will get




•
Read the warnings by clicking on 68 Warnings on the Design
Summary window whether or not the Xilinx IMPLEMENTATION
completes
We often check Design Summary for the warnings and the FPGA
utilization



0 Errors
68 Warnings which is the same as the Experiment 2 project
6% Slice utilization
Most warnings we check are in the Synthesis section
The FPGA utilization is lower than expected if there are errors or
warnings that must be corrected
In Experiment 3, the number of warnings will change

It will be 68 as it is now
•

Out of 68 warnings, 66 of them are synthesis warnings and 2 are Place &
Route warnings
But, later on with more modifications in Block 6, it will go up to 70 !
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 120
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Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro



Timing simulations are based on delays for the components and
signal propogations on the wires
Xilinx ISE records these delay only if we perform a Generate
Post-Place & Route Simulation Model
We select this option by expanding the Place & Route step
Click here
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 121
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Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro



Timing simulations are based on delays for the components and
signal propogations on the wires
Xilinx ISE records these delay only if we perform a Generate
Post-Place & Route Simulation Model
Since the Generate Post-Place & Route Simulation Model step has
a question mark next to it, we have to perform the step by double
clicking on it
Double click on this line
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 122
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Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro

When it stops the Generate Post-Place & Route Simulation Model
step has a check mark which means we can do timing simulations
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 123
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Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro

To start the simulation, click on Simulation
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 124

Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro

You will see that the Processes panel has a new selection :
Simulate Behavioral Model (functional simulation)
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 125
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Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro

However, we want timing simulations and so we will click here and
select Post Route
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 126
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Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro
•
We are now ready to perform timing simulations
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 127

Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro
•
Click on the ppm name to view the Simulate Post-Place & Route
step
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 128

Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro
•
Double click here, on the Simulate Post-Place & Route Model
step to start the timing simulation
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 129

Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro
•
•
•
•
•
•
•
•
•

To simulate the macro we need to select its inputs and outputs
The macro has 16 inputs : DISP
The macro has three outputs : Aposzero and ZERODISP
The simulator wire list and object list are not alphabetically
ordered !
We have to delete all the wires on the wire list
We click on Objects on the left side to view the object list
We right click in the Objects panel and select Search to select
the wires one by one
After we enter a wire name, for example DISP and press Enter
the simulator will list a number of wires with this name
We select and drag all the wires that are DISP15 through DISP0
to the wire list area
See the next slide
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 130

Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro
16 wires dragged up
After scrolling down
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 131

Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro
•
•
To simulate macro we need to select its inputs and outputs
The macro has 16 inputs and 3 outputs
Make sure you select the signals as follows :
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 132
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Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro

Click on Restart on the upper tool bar so that the starting time is 0
seconds

Change observation duration time from 1 microseconds to 5 nanoseconds
by entering 5ns

Apply 0 to all the inputs and note that outputs ZERODISP1 takes the
longest time to compute which is 3.195 ns



Note that on your computer the timing for ZERODISP1 can be different and
also another output can take the longest time
This is due to the fact that Xilinx randomizes the placement of the CLB to
obtain close to best placement
See the next slide
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 133

Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro

Determining ZERODISP1 is 0 takes 3.195 ns
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 134

Today’s Individual Xilinx Lab Work
15.
Perform timing simulations on the macro
time
time
0000
A0E1
time
time
time
time
0C80
290D
4F97
06F1
Note again that your timings can be different
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 135
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Today’s Individual Xilinx Lab Work
15.

Perform timing simulations on the macro
As the previous slide shows there are glitches generated
by the circuit you designed !

If yes, which output(s) would have the glitch ?
•


WHY ?
Which input combination pairs would generate the glitch ?
Before completing this step, make sure the circuit in
schematic 6 is beautified, the schematic is saved and a
Xilinx IMPLEMENTATION is done again
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 136

Today’s Individual Xilinx Lab Work
16. Download the Ppm project to the FPGA chip
and play the game and to verify that the
schematic works correctly

In order to test the circuit fast you can input
random digits directly to the machine player




After you play, when the state is 3, leave one of
switches SW7 – SW4 on to signal you will input the
random digit
Use switches SW3 – SW0 to select a random digit
value
Press push button BTN2 so the machine player starts
with the random digit you input
Turn off the signaling switch (one of SW7 – SW4)
before you press push button BTN3 to play
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 137

Today’s Individual Xilinx Lab Work
16. Download the Ppm project to the FPGA chip
and play the game and to verify that the
schematic works correctly

In order to test the circuit, the four conditions
in the playing strategy must be true
1.
2.
3.
4.
A position is zero
RD is not zero
There is no adjacency
The machine player is playing one its first three plays
•
In addition
5. Player 2 cannot win the game with the current play
6. A code digit cannot be played
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 138

Today’s Individual Xilinx Lab Work
16. Download the Ppm project to the FPGA chip
and play the game and to verify that the
schematic works correctly

Therefore, testing the circuit is possible right
after the reset

Repeat the following until you are sure your circuit is
correct
a) Reset/download
b) Play on a position
c) Input a non-zero random digit which does not generate an
adjacency
d) If there are still zero positions, go back to step (b).
Otherwise, go back to step (a)
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 139

Today’s Individual Xilinx Lab Work
16. Download the Ppm project to the FPGA chip
and play the game and to verify that the
schematic works correctly

If it does not work, inspect your circuit in Block
6 and correct the circuit
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 140

Today’s Individual Xilinx Lab Work
17. Modify Machine Play Block (Block 6) circuits to
implement a simple machine playing strategy as
explained on slides 28 to 66

Develop the new Block 6 schematic

Delete all the circuits drawn by the professor
•


Draw the new schematics by following slides 28 to 66
Label the components so that the last component label is
U299
•
•
•



Keep your M3 circuit
Note that a buffer is needed to rename Aposzero as P2played
We do not label buffers as Uxyz but the outputname_BUF
Therefore, label the P2played buffer as P2played_BUF
Beautify your circuits
Save the schematic
See modified Block 6 on the next slide
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 141

Today’s Individual Xilinx Lab Work
17.
Modify Machine Play Block (Block 6) circuits to implement a simple
machine playing strategy as explained on slides 28 to 66
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 142

Today’s Individual Xilinx Lab Work
17. Modify Machine Play Block (Block 6) circuits to
implement a simple machine playing strategy as
explained on slides 28 to 66

Develop the new Block 6 schematic

Perform a schematic check
•
•
•
There will be 0 errors and 5 warnings
The two new warnings compared with Experiment 2 are P2sturn
and Clearp2ffs
Since Block 6 is not using them, the warnings are acceptable !
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 143

Today’s Individual Xilinx Lab Work
17. Modify Machine Play Block (Block 6) circuits to
implement a simple machine playing strategy as
explained on slides 28 to 66

Develop the new Block 6 schematic

Perform logic simulations
•
•

In order to do logic simulations, perform a synthesis
The number of synthesis warnings is 68
Perform logic simulations to observe that the machine player
follows the playing strategy
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 144

Today’s Individual Xilinx Lab Work
17. Modify Machine Play Block (Block 6) circuits to
implement a simple machine playing strategy as
explained on slides 28 to 66

Perform a Xilinx IMPLEMENTATION

The Xilinx IMPLEMENTATION results in 70 warnings
•
•
•
The number of synthesis warnings is 68
The number of Place & Route warnings is 2
The slice utilization is 4%
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 145

Today’s Individual Xilinx Lab Work
17. Modify Machine Play Block (Block 6) circuits to
implement a simple machine playing strategy as
explained on slides 28 to 66

Perform timing simulations to observe the delays

Make sure that the machine player follows the playing
strategy
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 146

Today’s Individual Xilinx Lab Work
17. Modify Machine Play Block (Block 6) circuits to
implement a simple machine playing strategy as
explained on slides 28 to 66

Download the Ppm project to the FPGA chip and play the
game and to verify that the schematic works correctly


Make sure that the machine player follows the playing
strategy
If it does not work, inspect your circuits in Block 6 and
correct the circuit
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 147

Today’s Individual Xilinx Lab Work
17. Modify Machine Play Block (Block 6) circuits to
implement a simple machine playing strategy as
explained on slides 28 to 66

If you are sure your Experiment 3 circuit is correct
then
•

Copy your experiment 3 folder from the S drive to your
laptop
Make sure you refresh your memory about the game
rules and how to play the game
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 148

Today’s Individual Xilinx Lab Work
18. Help your partners complete today’s project
19.
Submit your exp3 project once everyone
completes the design



If all the team members have finished the new machine
player design (Step 17 on the previous slide), they will
decide whose project will be submitted
Students will fill out a Term Project Check List handout
so that feedback can be given to them by the grading
TAs
Students will signal to a TA who will copy their project
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 149

Today’s Individual Xilinx Lab Work
20. Obtain the full circuitry of the Rightmost Largest
Display circuit studied in class

The circuit was partially designed in class


It will be designed next week
Determine all the components of the circuit and draw the
full circuit on paper to be ready for next week
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 150

Today’s Individual Xilinx Lab Work
21. Continue Reading the Term Project handout

Study and play the other two types of the Ppm
game to think more about the our machine
player’s strategy


Human vs. human : ppmhvsh
Machine vs. machine : ppmmvsm
•

Think about the playing strategy of the machine player that will
be designed
Also read slides at the end to learn about the
software, Project Manager, Schematic design and
other related topics
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 151

Understand Critical Wires
RD : 4 bits
 The random digit
R1D : 4 bits
Next random digit
R2D : 4 bits
The random digit after next random digit
DISP : 16 bits
 They represent the four position displays
 In Hex
 DISP15-DISP12 : The leftmost position display, PD3
 DISP11-DISP8 : position display PD2, etc
NPDISP : 16 bits
 The result of RD to each display digit
 In Hex
 NPDISP15-NPDISP12 : The leftmost position, PD3, value + RD
 NPDISP11-NPDISP8 : Position display PD2 value + RD
NPSELDISP : 4 bits
 Selects one of NPDISP display values
 In Hex
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 152

Understand Critical Wires
BRWD : 4 bits
 Basic reward
 In Hex
 The digit played and also minimum points earned
 It is selected from RD or NPSELDISP
 Based on how the player played : Directly or with an addition
Brwdeqz : 1 bit
 BRWD is zero when it is 1
PDPRD : 4 bits
 Display overflow bits after addition
Pdprd : 1 bit
The display overflow bit of the position played
Selplyr : 1 bit
 The current player
 If it is 0, it is the human player, otherwise, it is the machine
player
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 153

Understand Critical Wires
P1SEL : 4 bits
 The position played by the human player
P2SEL : 4 bits
 The position played by the machine player
PSEL : 4 bits
 Position Select bits of current player
ENCPSEL : 2 bits
 The number of the position played
EQ : 4 bits
 The equality of the four displays to the digit played
NSD : 2 bits
 The number of similar digits, i.e. the adjacency information of the
position played
RWD : 8 bits
 The regular reward points calculated based on adjacencies
 In Unsigned Binary
CODERWD : 8 bits
 The code reward points calculated based on the code digits
 In Unsigned Binary
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 154

Understand Critical Wires
P1PT : 8 bits
 Player 1 points
 In Hex
P2PT : 8 bits
 Player 2 points
 In Hex
PT : 8 bits
 The points of the current player
 In Hex
NPT : 8 bits
 New player points for the current player
 In Hex
Ptovf : 1 bit
The points overflow
 if it is 1, the new player points is above (255)10
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 155

Understand Critical Wires
P1add : 1 bit
 Player 1 adds when it is 1
P2add : 1 bit
 Player 2 adds when it is 1
Add : 1 bit
 The current player adds when it is 1
P1skip : 1 bit
 Player 1 skips when it is 1
P2skip : 1 bit
 Player 2 skips when it is 1
P1played : 1 bit
 Player 1 has played when it is 1
P2played : 1 bit
 Player 2 has played when it is 1
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 156

Understand Critical Wires
DISPSEL : 2 bit
 Selects one of four values for displays




00 Selects position displays (displays that RD is played on)
01 Selects player points
10 Selects next two random digits
11 Selects discovered code digits
Add : 1 bit
Shows that the current player has selected to add
Stp1pt : 1 bit
 Store Player 1 points
Stp2pt : 1 bit
 Store Player 2 points
Grd : 1 bit
 Signals to generate a new random digit
 The random digit counter output is stored as P2RD while P2RD and
P1RD are shifted to generate the new P1RD and RD
Bpds : 1 bit
Blink one or all displays slowly
Bpdf : 1 bit
Blocks a display fast after a display overflow
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 157

Understand Critical Wires
Clear : 1 bit
 Clear FFs, registers, counters, etc. during reset in Block 2, Block 4
and Block 6 so that it can play again
Clearp2ffs : 1 bit
 Clears Player 2 FFs, counters and registers
Clff : 1 bit
 Clears FFs in Block 2 so that the next player can play if there is no
overflow
S1 : 1 bit
 State 1 where when it is 1, the Ppm is in state 1
P2sturn : 1 bit
 Signals that Player 2 has the turn
 It is 1 when the Ppm is in state 4
Sysclk : 1 bit
 System clock of the operation diagram at 6 Hz
 P2clk : 1 bit
 The clock signal of Player 2 at 48 Hz
 Rdclk : 1 bit

The random digit counter clock at 192 Hz
CS 2204 Spring 2014 Experiment 3 Lab 6 Page 158