Transcript Microelectronic System Design

3. ASIC and SOC Design Methods:
Structured VLSI Design
Spring 2009
Rajesh K. Gupta
Outline
Circuit Styles
 The evolving ASIC Design Methodology


References:
Basic Logic Families, Kerry Bernstein, Ch. 7, of A.
Chandrakasan et. al. book
 Chapter 11 of Rabaey book

Basic Logic Families

Circuit Styles
Different possible circuit topologies for a given logic function
(from the same set of basic transistor devices)
 even within CMOS: compatible CMOS styles

Choice determined by design criteria: performance,
power consumption, testability, ease of design
(analysis)
 Available styles


Nonclocked logic (clocked logic discussed after clocking)
 example: static combinatorial CMOS, differential cascode
voltage-switch logic, pass-transistor logic
 generally: low power, ease of automated synthesis, easy
timing analysis, reliability and noise immunity, defect
tolerance, migration across process.
 Reliability because nodes maintain values (never left to
float), direct control of nodal values (noise immunity), switch
points can be varied.
Nonclocked: Static Combinatorial
CMOS
Operate under “push-pull” action
 Transfer function

similar to the inverter transfer function
 unity gain point (UGP)
 point on the transfer function where slope is -1
 a circuit will attenuate inputs less than the lower UGP and
amplify inputs higher than the lower UGP
 switch point (SWP)
 where Vin = Vout
 can be skewed by the effective device sizing by hastening
transition in a given direction
 noise margin
 is the difference between the least positive up level of the
preceding stage and the upper UGP of the given stage
 or the most positive down level of the previous stage and
the lower UGP of the given stage.

Static CMOS

Delay variations
by the input pattern, by switching history
 by the active fanout load
 depending upon the channel state, gate-substrate
capacitance changes (towards inversion gate-substrate
capacitance drops)
 signal coupling in interconnect changes fanout load
 false switching (consumes about 15% of the total power)


Design rules
Alpha ratio:
 ratio of the total output capacitance on a given stage
divided by its total input capacitance; (2.7 produces
minimum PDP)
 Beta ratio:
 ratio of a given stage’s PFET W/L to its NFET W/L
 NAND n-stack design:
 body effect on the top device decreases its drive
 device tapering and signal positioning.

Domino CMOS

Domino logic is evaluated through single-sided
transitions
no need for complimentary logic implementations
 generally N-FET evaluation trees (smaller area)

To ensure single transitions, all outputs are inverted
so that the inputs only make a transition from low to
high
 several issues related to capacitive coupling, noise
immunity and false discharges

Pass-Gate Logic

Logic evaluation by signal coupling

rather than by signal evaluation and redriving
Generally lower capacitive loads
 However, many liabilities

limited fan-in capability
 current discharge to ground through a pass-gate must be
limited to achieve acceptable low levels at the receiver
 excessive fan-out
 the driver to pass gates (for example, output inverter driving
subsequent pass gates) must be sized for all the paths its
serves
 noise vulnerability
 interconnect coupling can be propagated through a passgate
 Body bias effects reduce available drive
 Path protection need for decoders: when used as mux, gate
inputs are needed to ensure paths are maintained.

Structured VLSI Design
Four Phases in Creating a Chip
The Design Problem
Source: sematech97
A growing gap between design complexity and design productivity
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
VLSI-design Tools & Methodologies
Goal is to reduce complexity, increase productivity,
and increase chances of a working chip
 Key is the use of Constraints and Abstractions

Constraints
 help automate the procedure by simplifying the problem
 Abstractions
 collapse detail and arrive at a simpler problem to deal with


Different design methodologies
 different
types of constraints and trade-offs
 choice driven by economics!
Design Domains

Behavioral
 what

Structural
 how

a system does
entities are connected together to perform the behavior
Physical (geometrical)
 how
to build a structure that has the required connectivity to
implement the prescribed behavior
Levels of Design Abstractions for Each
Design Domain
Architectural
 Algorithmic
 Module or functional block
 Logical
 Switch
 Circuit
 Device
 etc.

Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
Vin
Vout
DEVICE
G
S
n+
D
n+
Adapted from Irwin & Nayaranan’s Slides from PSU. Copyright 2002 J. Rabaey et al."
Design Methodology


Design process traverses iteratively between behavior,
structure, and geometry abstractions
CAD tools providing more and more automation
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
A Simplified Flow
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Implementation Choices
Digital Circuit Implementation Approaches
Custom
Semicustom
Cell-based
Standard Cells
Compiled Cells
Macro Cells
Array-based
Pre-diffused
(Gate Arrays)
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Pre-wired
(FPGA's)
Transition to Automation and Regular Structures
Intel 4004 (‘71)
Intel 8080
Intel 8286
Intel 8085
Intel 8486
Courtesy Intel
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Cell-based Design (or standard cells)
Routing channel
requirements are
reduced by presence
of more interconnect
layers
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Standard Cell - Example
3-input NAND cell
(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Automatic Cell Generation
Initial transistor
geometries
Placed
transistors
Routed
cell
Compacted
cell
Courtesy Acadabra
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Finished
cell
MacroModules
25632 (or 8192 bit) SRAM
Generated by hard-macro module generator
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
“Soft” MacroModules
Synopsys DesignCompiler
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
“Intellectual Property”
A Protocol Processor for Wireless
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Semicustom Design Flow
Design Capture
Behavioral
Design Iteration
HDL
Pre-Layout
Simulation
Structural
Logic Synthesis
Floorplanning
Post-Layout
Simulation
Placement
Circuit Extraction
Routing
Tape-out
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Physical
The “Design Closure” Problem
Iterative Removal of Timing Violations (white lines)
Courtesy Synopsys
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Integrating Synthesis with
Physical Design
RTL (Timing) Constraints
Physical Synthesis
Macromodules
Fixed netlists
Netlist with
Place-and-Route Info
Place-and-Route
Optimization
Artwork
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Late-Binding Implementation
Digital Circuit Implementation Approaches
Custom
Semicustom
Cell-based
Standard Cells
Compiled Cells
Macro Cells
Array-based
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA's)
Array-based
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA's)
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Gate Array — Sea-of-gates
polysilicon
VD D
rows of
uncommitted
cells
metal
possible
contact
GND
In 1 In 2
Uncommited
Cell
In 3 In4
routing
channel
Committed
Cell
(4-input NOR)
Out
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Sea-of-gate Primitive Cells
Oxide-isolation
PMOS
PMOS
NMOS
NMOS
NMOS
Using oxide-isolation
Using gate-isolation
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Prewired Arrays
Classification of prewired arrays (or field-programmable devices):

Based on Programming Technique
Fuse-based (program-once)
 Non-volatile EPROM based
 RAM based


Programmable Logic Style
Array-Based
 Look-up Table


Programmable Interconnect Style
Channel-routing
 Mesh networks

Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Antifuse

Normally high resistance (>
100 M)
 on
application of appropriate
voltage, the antifuse is
changed permanently to a low
resistance structure (200500)
Array-Based Programmable Logic
I5
I4
I3
I2
I1
I0
Programmable
OR array
Programmable AND array
I2
I1
I0
Programmable
OR array
Fixed AND array
O 3O 2O 1O 0
PLA
I3
I5
I4
I3
I2
I1
I0
Fixed OR array
Programmable AND array
O3O2O1O0
PROM
Indicates programmable connection
Indicates fixed connection
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
O 3O 2O 1O 0
PAL
Programming a PROM
1
X2
X1
X0
: programmed node
NA NA f 1 f 0
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
2-input mux
as programmable logic block
Configuration
A
0
F
B
1
S
A
B
S
F=
0
0
0
0
X
Y
Y
1
1
1
0
X
Y
Y
0
0
1
0
0
1
0
1
1
X
Y
X
X
X
Y
1
0
X
Y
XY
XY
XY
X1 Y
X
Y
1
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Logic Cell of Actel Fuse-Based FPGA
A
B
1
SA
Y
1
C
D
1
SB
S0
S1
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Memory
Look-up Table Based Logic Cell
Out
In
Out
00
00
01
1
10
1
11
0
ln1 ln2
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
LUT-Based Logic Cell
4
C1....C4
xx
xxxx
xxxx
xxxx
Bits
control
D4
D3
D2
Logic
function
of
xxx
D1
Logic
functionx
of
xxx
F4
F3
F2
F1
xx
xx
xx
xx
Logic
function
of
xxx
x
xxxxx
Xilinx 4000 Series
xxxx
xx
x xx x
xx xx
x
x
x
x
Bits
control
xx
xx
xx
xx
xxxx
x xx x
xx
xx xx
H
P
x
Multiplexer Controlled
by Configuration Program
Courtesy Xilinx
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
x
Array-Based Programmable Wiring
M
Interconnect
Point
Programmed interconnection
Input/output pin
Cell
Horizontal
tracks
Vertical tracks
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Mesh-based Interconnect Network
Switch Box
Connect Box
Interconnect
Point
Courtesy Dehon and Wawrzyniek
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Transistor Implementation of Mesh
Courtesy Dehon and Wawrzyniek
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Hierarchical Mesh Network
Use overlayed mesh
to support longer connections
Reduced fanout and reduced
resistance
Courtesy Dehon and Wawrzyniek
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
EPLD Block Diagram
Macrocell
Primary inputs
Courtesy Altera
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Altera MAX
From Smith97
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Altera MAX Interconnect Architecture
column channel
row channel
t PIA
LAB1
LAB2
LAB
PIA
t PIA
LAB6
Array-based
(MAX 3000-7000)
Mesh-based
(MAX 9000)
Courtesy Altera
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Field-Programmable Gate Arrays
Fuse-based
I/O Buffers
Program/Test/Diagnostics
Vertical routes
I/O Buffers
I/O Buffers
Standard-cell like
floorplan
Rows of logic modules
Routing channels
I/O Buffers
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Xilinx 4000 Interconnect Architecture
CLB
12
Quad
8
Single
4
Double
3
Long
2
3
12
4
4
8
Quad
Long
Global
Long
Clock
4
8
4
Double Single Global
2
Carry
Direct
Clock Chain Connect
Courtesy Xilinx
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Direct
Connect
Long
RAM-based FPGA
Xilinx XC4000ex
Courtesy Xilinx
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Architecture ReUse

Silicon System Platform
Flexible architecture for hardware and software
 Specific (programmable) components
 Network architecture
 Software modules
 Rules and guidelines for design of HW and SW


Has been successful in PC’s


Dominance of a few players who specify and control
architecture
Application-domain specific (difference in
constraints)
Speed (compute power)
 Dissipation
 Costs
 Real / non-real time data

Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Platform-Based Design
A platform is a restriction on the space of possible
implementation choices, providing a well-defined
abstraction of the underlying technology for the
application developer
 New platforms will be defined at the architecturemicro-architecture boundary
 They will be component-based, and will provide a
range of choices from structured-custom to fully
programmable implementations
 Key to such approaches is the representation of
communication in the platform model

Source:R.Newton
Adapted from Digital Integrated Circuits
(2nd
Edition). Copyright 2002 J. Rabaey et al."
Heterogeneous Programmable Platforms
FPGA Fabric
Embedded memories
Embedded PowerPc
Hardwired multipliers
Xilinx Vertex-II Pro
High-speed I/O
Courtesy Xilinx
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
Principles of Structured Design
Techniques

Hierarchy

Regularity

Modularity

Locality
Source: Mani Srivastava, UCLA
Hierarchy

Divide and conquer
 compose

Analogy with software
 break

large programs into threads and subroutines
Hierarchy can be there in all domains
 behavior,

system from simpler widgets
structural, physical
The hierarchy in different domains may not
correspond
 e.g.
a structural hierarchy may not map well to physical
Source: Mani Srivastava, UCLA
Example of Structural Hierarchy
Source: Mani Srivastava, UCLA
Example of Physical Hierarchy
Source: Mani Srivastava, UCLA
Example of Structural Hierarchy
Source: Mani Srivastava, UCLA
Example of Physical Hierarchy
Source: Mani Srivastava, UCLA
Repartitioning Structural Hierarchy to Fit
Physical Hierarchy
Source: Mani Srivastava, UCLA
Regularity

Hierarchy breaks a system into submodules
 but
this may not solve the complexity problem
 there may not be any regularity in the subdivision
'

we just end up with a large # of different submodules
Regularity as a guide
 subdivide
'

into a set of similar building blocks
e.g. RAM composed of identical cells
Regularity means that the hierarchical decomposition
of a large system should result in not only simple,
but also similar blocks, as much as possible
Source: Mani Srivastava, UCLA
Regularity (contd.)

Regularity can be at all levels
 circuit:
use identically sized transistors
 gate: similar gate structures
 higher level: architectures with identical processors

Regularity helps in many ways
 correct
by construction
 reuse of design
 simplify verification of correctness
Source: Mani Srivastava, UCLA
Circuit-level Regularity Example



A 2-1 Mux
D-type edge triggered
flipflop
One-bit full add
All designed using
inverter and tristate
buffer
Source: Mani Srivastava, UCLA
Modularity

Condition that submodules have “well-defined”
functions and interfaces
 in
addition to regularity and hierarchy
‘Well-formed” modules allow their interaction with
others to be “well-characterized”
 Depends on the situation

 e.g.
in s/w a subroutine has a well-defined interface
'
argument list with typed variables
 e.g.
in IC a well-defined physical, structural, and behavioral
interface
'
pin position, layer, size, signal type, electrical characteristics,
logic function
Source: Mani Srivastava, UCLA
Why Modularity?
Allows the design of system to be broken up with
confidence that the system will work as specified
when the parts are combined
 Allows team design by a number of designers
 Examples:

 bad
use: use of transmission gates as inputs
'
internal signals now depend on source impedance
 bad
use: use dynamic CMOS logic but fail to latch or
register the inputs
'
timing of each module will have to be checked
Source: Mani Srivastava, UCLA
Locality

Modularity provided “well-characterized” interfaces
 internals
'
a
internal details remain at the local level
form of “information hiding”
'

of modules unimportant to exterior interface
reduces apparent complexity of the module
Locality ensures that connections are between
neighboring modules, avoiding long-distance
connections
 Example:
timing locality so that time critical operations are
local
'
'
'
clock generation and distribution network
entire clock cycle for global signals to traverse chip
placement so that global wiring is minimized
 Analogy
'
with software
global variables are to be avoided
Source: Mani Srivastava, UCLA
Parallels between H/W & S/W Design
Strong parallels in the way VLSIs are designed and
the way complex software is
 HDLs used to describe hardware systems in
essence merge these two disciplines

 software
methods used to define hardware
Hardware-software Co-design
 But, can’t ignore hardware aspects entirely

 important
Source: Mani Srivastava, UCLA
since a physical chip is the end product