Transcript PowerPoint 프레젠테이션 - German University in Cairo

ELCT 903
Programmable Logic Circuits:
Introduction
Dr. Eng. Amr T. Abdel-Hamid
Fall 2010
Course Contents
Programmable Logic Circuits
 Introduction to Programmable Logic Devices
 Number systems and basic arithmetic operations
 Computer Arithmetic Basic Functions:
 Addition
 Multiplication
 Division
 Floating-point arithmetic
 Special FP Functions
Dr. Amr Talaat
 Pipelining Basics
 Test Bench Generation
ELECT 90X
Course Grading
Programmable Logic Circuits
 Exams
 Quizzes (10%)
3 Quizzes: best 2
 Midterm (20%)
 Final exam (40%)
 Assignments (50%)
Dr. Amr Talaat
 Project (25%)
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Project
Programmable Logic Circuits
 Course Project:
 Building a Fast Floating Point MIPS Microprocessor
 Other topics (after instructor approval)
 Mixed Signal Design
 IP Protection
 More in your master/graduation project topic to publish a paper?
Dr. Amr Talaat
ELECT 90X
Project
Programmable Logic Circuits
 Phase 0: Select your partner
(27/9/2010)
 Submit list of your group members (2-4 per group)
Dr. Amr Talaat
 Phase 1:
.
.
.
.
.
 Phase N: Finael Project Implementation + Report
(2 weeks before finals)
FINAL Non-Negotiable deadline
ELECT 90X
In time
&
It is too LATE Policy
Programmable Logic Circuits
 In phases 0, & 1:
 5% of project grade penalty per day for being late
 In phase 2, to n:
 No late presentation is possible.
Dr. Amr Talaat
 Honor code
 100% penalty for both copier and copy-giver of Any
Report/CODE.
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Why PLCs?
Programmable Logic Circuits
 Main Design Goal: Construct an implementation with d
esired functionality.
 Key design challenge: Simultaneously optimize numer
ous design metrics
 Design metric:
 A measurable feature of a system’s implementation
 Optimizing design metrics is a key challenge
Dr. Amr Talaat
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Design Challenge
Programmable Logic Circuits
 Size: the physical space required by the system
 Performance: the execution time or throughput of the syst
em
 Power: the amount of power consumed by the system
 Energy
Dr. Amr Talaat
 What is the difference between power and Energy?
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Design Challenge
Programmable Logic Circuits
 Time-to-prototype: the time needed to build a working version of the
system
 Time-to-market: the time required to develop a system to the point th
at it can be released and sold to customers
 Maintainability: the ability to modify the system after its initial release
 NRE cost (Non-Recurring Engineering cost): The one
-time monetary cost of designing the system
 Flexibility: the ability to change the functionality of the s
ystem without incurring heavy NRE cost
Dr. Amr Talaat
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Time-to Market
 Period during which the product would have highest sales
 Average time-to-market constraint is about 8 months
 Delays can be costly
Dr. Amr Talaat
Revenues ($)
Programmable Logic Circuits
 Time required to develop a product to the point it can be sold t
o customers
 Market window
Time (months)
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Delayed Market Entry
Peak revenue
Revenues ($)
Programmable Logic Circuits
 Simplified revenue model
Peak revenue from
delayed entry 
Market
rise
Delayed
Dr. Amr Talaat
D
On-time
entry
On-time
W
Delayed
entry
Market
fall
 Product life = 2W, peak at W
 Time of market entry defines
a triangle, representing marke
t penetration
 Triangle area equals revenue
Loss
 The difference between the o
n-time and delayed triangle ar
eas
2W
Time
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Design Productivity Gap
Programmable Logic Circuits
 1981 leading edge chip required 100 designer months
 10,000 transistors / 100 transistors/month
 2002 leading edge chip requires 30,000 designer months
 150,000,000 / 5000 transistors/month
 Designer cost increase from $1M to $300M
Dr. Amr Talaat
Logic transistors
per chip
(in millions)
10,000
100,000
1,000
10,000
100
10
1
0.1
0.01
0.001
Gap
IC capacity
productivity
1000
100
10
1
Productivity
(K) Trans./Staff-Mo.
0.1
0.01
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The Mythical Man-Month
Programmable Logic Circuits
 The situation is even worse than the productivity gap indicates







In theory, adding designers to team reduces project completion time
In reality, productivity per designer decreases due to complexities of team management and c
ommunication
In the software community, known as “the mythical man-month” (Brooks 1975)
At some point, can actually lengthen project completion time! (“Too many cooks”)
1M transistors, 1 designer=5000 trans/month
Each additional designer reduces for 100 trans/month
So 2 designers produce 4900 trans/month each
Dr. Amr Talaat
60000
50000
40000
30000
20000
10000
16
Team
15
16
18
19
23
24
Months until completion
43
Individual
0
10
20
30
Number of designers
40
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NRE and Unit Cost Metrics
Programmable Logic Circuits
 Costs:
 Unit cost: the monetary cost of manufacturing each copy of the system, exclu
ding NRE cost
 NRE cost (Non-Recurring Engineering cost): the one-time monetary cost of d
esigning the system
 total cost = NRE cost + unit cost * # of units
 per-product cost
= total cost / # of units
= (NRE cost / # of units) + unit cost
• Example
Dr. Amr Talaat
– NRE=$2000, unit=$100
– For 10 units
– total cost = $2000 + 10*$100 = $3000
– per-product cost = $2000/10 + $100 = $300
Amortizing NRE cost over the units results in an
additional $200 per unit
ELECT 90X
NRE and unit cost metrics
Programmable Logic Circuits
 Compare technologies by costs -- best depends on quantity
 Technology A: NRE=$2,000, unit=$100
 Technology B: NRE=$30,000, unit=$30
 Technology C: NRE=$100,000, unit=$2
• But, must also consider time-to-market
Dr. Amr Talaat
ELECT 90X
Hardware Design Flow
Programmable Logic Circuits
Human
Behavioral
Description
Human
Gate Level
Synthesis
RTL
Implementation
Logic Synthesis
Layout Synthesis
Chip Programming
Layout
(Masks)
Dr. Amr Talaat
PLC
Manufacturing
Product ASIC
ELECT 90X
Programmable Logic
Programmable Logic Circuits
Dr. Amr Talaat
 Many programmable logic devices are field- programmable, i. e.,
can be programmed outside of the manufacturing environment
 Most programmable logic devices are erasable and reprogramm
able.
 Allows “updating” a device or correction of errors
 Allows reuse the device for a different design - the ultimate i
n re-usability!
 Ideal for course laboratories
 Programmable logic devices can be used to prototype design th
at will be implemented for sale in regular ICs.
 Complete Intel Pentium designs were actually prototyped wit
h specialized systems based on large numbers of VLSI progr
ammable devices!
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Programmable Logic Circuits
Programmable Logic Circuits
 Facts:
 It is most economical to produce an IC in large volumes
 Many designs required only small volumes of Ics
 A programmable logic part can be:
 made in large volumes
 programmed to implement large numbers of different low-volum
e designs
Dr. Amr Talaat
ELECT 90X
Hierarchy of Logic Implementations
Programmable Logic Circuits
Logic
Standard
Logic
TTL
ASIC
Programmable
Logic Devices
CMOS
SemiCustom
ICs
(FPLDs)
SPLDs
(e.g., PALs)
CPLDs
FPGAs
Gate
Arrays
Full Custom
ICs
Cell-Based
ICs
Dr. Amr Talaat
ELECT 90X
Programming Technologies
Programmable Logic Circuits
 Programming technologies are used to:
 Control connections
 Build lookup tables
 Control transistor switching
Dr. Amr Talaat
 The technologies
 Control connections
Mask programming
Fuse
Antifuse
Single-bit storage element
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Programming Technologies
Programmable Logic Circuits
Dr. Amr Talaat
 The technologies (continued)
 Build lookup tables
Storage elements (as in a memory)
 Transistor Switching Control
Stored charge on a floating transistor gate
Erasable
Electrically erasable
Flash (as in Flash Memory)
Storage elements (as in a memory)
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Technology Characteristics
Programmable Logic Circuits
 Permanent - Cannot be erased and reprogrammed
 Mask programming
 Fuse
 Antifuse
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 Reprogrammable
 Volatile - Programming lost if chip power lost
 Single-bit storage element
 Non-Volatile
 Erasable
 Electrically erasable
 Flash (as in Flash Memory)
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Field- Programmable Logic Devices
Programmable Logic Circuits
Dr. Amr Talaat
• Component function is defined by user
s program.
• Logic Cells Fields are interconnected b
y programming.
• Advantages:
- Flexible design that changes by re
programming, ease of design chang
es
- Reduce prototype-product time
- Large scale integration (over 100 0
00 gates)
- Reliability increased, low financial
risk
- Smaller device, low start-up cost
ELECT 90X
4/13
Programmable Configurations
Programmable Logic Circuits
 Read Only Memory (ROM) - a fixed array of AND gate
s and a programmable array of OR gates
 Programmable Array Logic (PAL) - a programmable
array of AND gates feeding a fixed array of OR gates.
 Programmable Logic Array (PLA) - a programmable
array of AND gates feeding a programmable array of O
R gates.
 Complex Programmable Logic Device (CPLD) /Field
- Programmable Gate Array (FPGA) - complex enoug
h to be called “architectures”
Dr. Amr Talaat
ELECT 90X
ROM
Programmable Logic Circuits
• A special device (called a burner),
used to put the information,
supplies an electrical current
to specific cells in the ROM that
effectively blows a fuse in them
= burning the PROM.
From that point on, chip is read-only.
• PROM was the first type of user-programmable chi
p; address lines = logic circuit inputs
data lines = logic circuit outputs
Dr. Amr Talaat
• PROMs are inefficient architecture for realizing logi
c circuit:
ELECT 90X
6/13
Read Only Memory Example
Programmable Logic Circuits
Dr. Amr Talaat
 Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines)
 The fixed "AND" array is a
X
X
D7
D6
“decoder” with 3 inputs and 8
X
D5
outputs implementing minterms.
X
D4
 The programmable "OR“
A2 D3
A
X
D2
array uses a single line to
X
B
A1 D1
represent all inputs to an
X
A0 D0
C
OR gate. An “X” in the
array corresponds to attaching the
minterm to the OR
 Read Example: For input (A2,A1,A0)
= 011, output is (F3,F2,F1,F0 ) = 0011.
F2
F1
F3
 What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?
X
X
X
F0
ELECT 90X
PLA
Programmable Logic Circuits
• PLA was the first device deve
loped for implementing
f ( x1,...,xn )  ( x1,...,xn )
• Consist of two levels
of logic gates - programmable
“wired” AND-plane & OR-pla
ne
• Drawbacks:
Dr. Amr Talaat
• Expensive to manufact
ure
Note:
• Offered somewhat poor
speed-performance
ELECT 90X
Programmable Logic Array Exampl
e
Programmable Logic Circuits
A

B
 Could the PLA implement the
What are the equations for F1 and F2?
functions without the XOR gates?
C
X
X
X
X
X
Dr. Amr Talaat
X
X
AB
2
X
BC
3
X
AC
1
X
X
4
X
X
AB
X
C C B B AA
 3-input, 3-output PLA with 4 p
roduct terms
X Fuse intact
Fuse blown
X
0
1
F1
F2
ELECT 90X
Programmable Logic Array (PLA)
Programmable Logic Circuits
 Compared to a ROM and a PAL, a PLA is the most flexible havi
ng a programmable set of ANDs combined with a programmable
set of ORs.
 Advantages
 A PLA can have large N and M permitting implementation of
equations that are impractical for a ROM (because of the nu
mber of inputs, N, required
 A PLA has all of its product terms connectable to all outputs,
overcoming the problem of the limited inputs to the PAL Ors
 Some PLAs have outputs that can be complemented, adding
POS functions
Dr. Amr Talaat
ELECT 90X
Programmable
Logic Array (PLA)
Programmable Logic Circuits
 Disadvantages
 Often, the product term count limits the application
of a PLA.
 Two-level multiple-output optimization is required t
o reduce the number of product terms in an imple
mentation, helping to fit it into a PLA.
 Multi-level circuit capability available in PAL not av
ailable in PLA. PLA requires external connections
to do multi-level circuits.
Dr. Amr Talaat
ELECT 90X
PAL
Programmable Logic Circuits
• Overcame weaknesses of P
LA
• Single level
of programmability consists of a programmable
“wired” AND-plane & fixed
OR-gates
• Simpler to program
and cheaper implementation
Dr. Amr Talaat
• Limited numbers
of terms in each output
ELECT 90X
Programmable Array Logic (PAL)
Programmable Logic Circuits
Dr. Amr Talaat
 The PAL is the opposite of the ROM, having a programmable set of
ANDs combined with fixed ORs.
 Disadvantage
 ROM guaranteed to implement any M functions of N
inputs. PAL may have too few inputs to the OR gates.
 Advantages
 For given internal complexity, a PAL can have larger N and M
 Some PALs have outputs that can be complemented, adding PO
S functions
 No multilevel circuit implementations in ROM (without external co
nnections from output to input). PAL has
outputs from OR terms as internal inputs to all AND
terms, making implementation of multi-level circuits easier.
ELECT 90X
AND gates inputs
0 1 2 3 4 5 6 7 8 9
X
2
F1
3
I 15 A
X X
X
6
X
7
F2
X
5
X
4
X
X
I25 B
X
X
8
X
F3
X
F1 =
F2 =
F3 =
F4 =
Product 1
term
X
 4-input, 3-output PAL with
fixed, 3-input OR terms
 What are the equations for
F1 through F4?
X
Programmable Logic Circuits
Programmable Array Logic Exampl
e
9
X
F4
X
12
X
11
X
10
X
Dr. Amr Talaat
I35 C
I4
0 1 2 3 4 5 6 7 8 9
ELECT 90X
Programmable Logic Devices (PLD)
Programmable Logic Circuits
Dr. Amr Talaat
ELECT 90X
Register PLA
Programmable Logic Circuits
• Contain flip flops connected to
the OR gate outputs
• Importance:
sequential circuit
s can be realize
d
• Profound effect on
digital hardware desi
gn
• Basis for more
sophisticated archite
ctures
Dr. Amr Talaat
ELECT 90X
9/13
CPLD
Programmable Logic Circuits
possibility to produce devices
• Technology advanced
with higher capacity than SPL
Ds.
• Structure grows too quickly in size as the number of inputs is
increased
• Integrating multiple SPLDs onto a single chip the only feasible way to provide large capacity devices
based on SPLD
Dr. Amr Talaat
• Programmably connect the SPLD blocks together
• Logic capacity up to the equivalent of about 50 typical SPLD de
vices
ELECT 90X
10/1
Sequential PLD
Programmable Logic Circuits
 Sequential Programmable Logic Device (SPLD)
Dr. Amr Talaat
ELECT 90X
Basic Macrocell of Sequential PLD
Programmable Logic Circuits
Dr. Amr Talaat
ELECT 90X
Complex PLD (CPLD)
Programmable Logic Circuits
CPLD consists multiple
SPLD arrays and
programmable
interconnections.
 LAB = SPLD
 PIA: Programmable
Interconnect Array
Dr. Amr Talaat
LAB & PIA are
programmed using
software.
CPLD “density” is usually
specified in terms of
macrocells or LAB.
Altera & Xilinx are the
major manufacturers.
ELECT 90X
CPLD
Programmable Logic Circuits
Dr. Amr Talaat
ELECT 90X
Altera CPLDs
Programmable Logic Circuits
Altera produces three lines of
CPLDs
EPLD series
MAX series
FLEX series
It also produces a complete
design tool
Dr. Amr Talaat
MAX+PLUS 2
Quartus II
ELECT 90X
Programmable Logic Circuits
Altera MAX 7000 CPLD
Dr. Amr Talaat
ELECT 90X
Xilinx CPLDs
Programmable Logic Circuits
 CoolRunner II, XC9500
 XC9500 is similar to MAX 7000, has PAL architecture
 CoolRunner II has PLA architecture
Dr. Amr Talaat
ELECT 90X
Programmable Logic Circuits
CoolRunner II Architecture
Dr. Amr Talaat
FB =
LAB
AIM
(Advanc
ed
Intercon
nect
Matrix)
= PIA
2~32
FBs
ELECT 90X
FPGA
Programmable Logic Circuits
 Provides logic blocks instead of AND or NAND plane
 Typical logic blocks is LUT
 Volatile devices
 Programmable read-only memory (PROM) can be
used to make it nonvolatile
Dr. Amr Talaat
ELECT 90X
FPGA
Programmable Logic Circuits
• Difficult extending CPLDs architectures to higher densiti
es - a different approach is needed
• FPGAs comprise an array of uncommited circuit elemen
ts, called logic blocks, and interconnect resources
• FPGA configuration is performed through
programming by the end user.
Dr. Amr Talaat
ELECT 90X
FPGA
Programmable Logic Circuits
Dr. Amr Talaat
ELECT 90X
LUT as Logic Block
Programmable Logic Circuits
x1
0/1
0/1
f
0/1
0/1
x2
(a) Circuit for a two-input LUT
x1 x2
f1
0
0
1
1
1
0
0
1
0
1
0
1
3-input LUT
x1
x2
0/1
0/1
(b) f 1 = x 1 x 2 + x 1 x 2
0/1
0/1
x1
0
0/1
f1
Dr. Amr Talaat
0
0/1
1
0/1
x2
f
0/1
1
x3
(c) Storage cell contents in the LUT
ELECT 90X
FPGA concept
Programmable Logic Circuits
 Field Programmable
Gate Array
 Basic elements:
 Configurable logic
block (CLB)
 I/O block
 interconnections
 CLB is simpler than
LAB or FB, but there
are many more of
them
Dr. Amr Talaat
ELECT 90X
Configurable Logic Block (CLB)
Programmable Logic Circuits
 Many FPGAs
are volatile
because their
LUTs are based
on SRAM.
Dr. Amr Talaat
ELECT 90X
Which Way to Go?
Programmable Logic Circuits
ASICs
FPGAs
Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Dr. Amr Talaat
Low cost in
high volumes
Reconfigurability
ELECT 90X