Transcript Trigger Base Personnel - University of Wisconsin–Madison

SLHC Trigger, DAQ, Electronics
CERN Academic Training:
LHC Upgrade: detector challenges
Wesley H. Smith
U. Wisconsin - Madison
March 16, 2006
Outline:
Introduction to LHC Trigger & DAQ
Impact of Luminosity up to 1035
Calorimeter, Muon & Tracking Triggers
DAQ requirements & upgrades
SLHC-era Electronics
This talk is available on:
http://cmsdoc.cern.ch/cms/TRIDAS/tr/06/03/smith_slhc_tridas_mar06.pdf
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 1
Processing LHC Data
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 2
LHC Trigger & DAQ Challenges
Challenges:
40 MHz
COLLISION RATE
LEVEL-1
TRIGGER
DETECTOR CHANNELS
Charge
Time
Pattern
100- 50 kHz
16 Million channels
3 Gigacell buffers
Energy
Tracks
1 MB EVENT DATA
1 Terabit/s
200 GB buffers
READOUT
50,000 data
channels
~ 400 Readout
memories
EVENT BUILDER.
500 Gigabit/s
SWITCH NETWORK
A large switching network (400+400
ports) with total throughput ~ 400Gbit/s
forms the interconnection between the
sources (deep buffers) and the
destinations (buffers before farm
CPUs).
~ 400 CPU farms
EVENT FILTER.
100 Hz
FILTERED
EVENT
A set of high performance commercial
processors organized into many farms
convenient for on-line and off-line
applications.
5 TeraIPS
Computing
Services
Gigabit/s
Petabyte ARCHIVE
SERVICE LAN
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
1 GHz of Input
Interactions
Beam-crossing
every 25 ns
with ~17
interactions
produces over
1 MB of data
Archival
Storage at
about 100 Hz of
1 MB events
SLHC Trigger, DAQ, Electronics - 3
LHC Trigger Levels
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 4
ATLAS Trig & DAQ for LHC
Overall Trigger & DAQ Architecture: 3 Levels:
Level-1 Trigger:
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 5
CMS Level-1 Trigger & DAQ
USC UXC
Overall Trigger & DAQ Architecture: 2 Levels:
Level-1 Trigger:
• 25 ns input
• 3.2 s latency
Interaction rate: 1 GHz
Bunch Crossing rate: 40 MHz
Level 1 Output: 100 kHz (50 initial)
Output to Storage: 100 Hz
Average Event Size: 1 MB
Data production 1 TB/day
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 6
Level 1 Trigger Operation
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
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Level 1 Trigger Organization
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 8
SLHC Level-1 Trigger @ 1035
Occupancy
• Degraded performance of algorithms
• Electrons: reduced rejection at fixed efficiency from isolation
• Muons: increased background rates from accidental coincidences
• Larger event size to be read out
• New Tracker: higher channel count & occupancy  large factor
• Reduces the max level-1 rate for fixed bandwidth readout.
Trigger Rates
• Try to hold max L1 rate at 100 kHz by increasing readout bandwidth
• Avoid rebuilding front end electronics/readouts where possible
• Limits: readout time (< 10 µs) and data size (total now 1 MB)
• Use buffers for increased latency for processing, not post-L1A
• May need to increase L1 rate even with all improvements
• Greater burden on DAQ
• Implies raising ET thresholds on electrons, photons, muons, jets and use of
less inclusive triggers
• Need to compensate for larger interaction rate & degradation in algorithm
performance due to occupancy
Radiation damage -- Increases for part of level-1 trigger located on detector
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 9
SLHC Trigger @ 12.5 ns
Choice of 80 MHz
• Reduce pile-up, improve algorithm performance, less data volume
for detectors that identify 12.5 ns BX data
• Retain front-end electronics since 40 MHz sampling in phase
• Not true for 10 ns or 15 ns bunch separation -- large cost
• Be prepared for LHC Machine group electron-cloud solution
• Retain ability to time-in experiment
• Beam structure vital to time alignment
• Higher frequencies ~ continuous beam
Rebuild level-1 processors to use data “sampled” at 80 MHz
• Already ATLAS & CMS have internal processing up to 160 MHz and
higher in a few cases
• Use 40 MHz sampled front-end data to produce trigger primitives
with 12.5 ns resolution
• e.g. cal. time res. < 25 ns, pulse time already from multiple samples
• Save some latency by running all trigger systems at 80 MHz I/O
• Technology exists to handle increased bandwidth
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 10
SLHC Trigger Requirements
High-PT discovery physics
• Not a big rate problem since high thresholds
Completion of LHC physics program
• Example: precise measurements of Higgs sector
• Require low thresholds on leptons/photons/jets
• Use more exclusive triggers since final states will be
known
Control & Calibration triggers
• W, Z, Top events
• Low threshold but prescaled
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 11
SLHC Level-1 Trigger Menu
ATLAS/CMS Studies in hep-ph/0204087:
•inclusive single muon pT > 30 GeV (rate ~ 25 kHz)
•inclusive isolated e/ ET > 55 GeV (rate ~ 20 kHz)
•isolated e/ pair ET > 30 GeV (rate ~ 5 kHz)
•or 2 different thresholds (i.e. 45 & 25 GeV)
•muon pair pT > 20 GeV (rate ~ few kHz?)
•jet ET > 150 GeV.AND.ET(miss) > 80 GeV (rate ~ 1-2 kHz)
•inclusive jet trigger ET > 350 GeV (rate ~ 1 kHz)
•inclusive ET(miss) > 150 GeV (rate ~1 kHz);
•multi-jet trigger with thresholds determined by the
affordable rate
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 12
Trig. Primitives: CMS
Calorimeter
HF:Quartz Fiber: Possibly replaced
• Very fast - gives good BX ID
• Modify logic to provide finer-grain information
• Improves forward jet-tagging
HCAL:Scintillator/Brass: Barrel stays but endcap replaced
• Has sufficient time resolution to provide energy in correct 12.5 ns BX with
40 MHz sampling. Readout may be able to produce 80 MHz already.
ECAL: PBWO4 Crystal: Stays
• Also has sufficient time resolution to provide energy in correct 12.5 ns BX
with 40 MHz sampling, may be able to produce 80 MHz output already.
• Exclude on-detector electronics modifications for now -- difficult:
• Regroup crystals to reduce  tower size -- minor improvement
• Additional fine-grain analysis of individual crystal data -- minor improvement
Conclusions:
• Front end logic same except where detector changes
• Need new TPG logic to produce 80 MHz information
• Need higher speed links for inputs to Cal Regional Trigger
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 13
Trig. Primitives: ATLAS Calor.
LAr: Increase in pileup @ 1035
- F.E. Taylor
• Electronics shaping time may need change to optimize
noise response
Space charge effects present for ||>2 in EM LAr
calorimeter
• Some intervention will be necessary
BC ID may be problematical with sampling @ 25 ns
• May have to change pulse shape sampling to 12.5 ns
Tilecal will suffer some radiation damage LY< 20%
• Calibration & correction – may be difficult to see Min-I
signal amidst pileup
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 14
Trig. Prim.: ATLAS Muons
- F.E. Taylor
Muon Detector issues:
• Faster & More Rad-Hard trigger technology needed
• RPCs (present design) will not survive @ 1035
• Intrinsically fast response ~ 3 ns, but resistivity increases at high
rate
• TGCs need to be faster for 12.5 BX ID…perhaps possible
• Gaseous detectors only practical way to cover large area of
muon system (MDT & CSC) Area ~ 104 m2
• Better test data needed on resol’n vs. rate
• Bkg.  and neutron efficiencies
• Search for faster gas  smaller drift time
• Drive technologies to 1035 conditions
Technologies:
• MDT & CSC & TGC will be stressed – especially high || ends of
deployment, RPCs will have to be replaced
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 15
@ 1035 (100 nb-1 s-1) Trig Rate ~
104 Hz & mostly ‘real’ if accidental
rate nominal – higher thresholds ~
larger fraction of accidentals
ATLAS µ Trig. Resolution & Rate
Accidentals
X 10
Accidentals
6 GeV
20 GeV
20 GeV
6 GeV
- F.E. Taylor
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 16
Trig. Prim.: CMS Endcap Muon
4 stations of CSCs: Bunch Crossing ID at 12.5 ns:
- D. Acosta
• Use second arriving segment to define track BX
• Use a 3 BX window
• Improve BX ID efficiency to 95% with centered peak, taking 2nd Local
Charged Track, requiring 3 or more stations
• Requires 4 stations so can require 3 stations at L1
• Investigate improving CSC performance: HV, Gas, …
• If 5 ns resolution  4 ns, BX ID efficiency might climb to 98%
Occupancy at 80 MHz: Local Charged Tracks found in each station
•
•
•
•
Entire system: 4.5 LCTs /BX
Worst case: inner station: 0.125/BX (others 3X smaller)
P(≥ 2) = 0.7% (spoils di- measurement in single station)
Conclude: not huge, but neglected neutrons and ghosts may be underestimated need to upgrade trigger front end to transmit LCT @ 80 MHz
Occupancy in Track-Finder at 80 MHz:
• Using 4 BX window, find 0.5/50 ns in inner station (every other BX at 25 ns!)
• ME2-4 3X smaller, possibly only need 3 BX
• Need studies to see if these tracks generate triggers
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 17
Trig Primitives: CMS DT & RPC
DT:
• Operates at 40 MHz in barrel
• Could produce results for 80 MHz with loss of
efficiency…or…
• Could produce large rate of lower quality hits for 80
MHz for combination with a tracking trigger with no
loss of efficiency
RPC:
• Operates at 40 MHz
• Could produce results with 12.5 ns window with some
minor external changes.
• Uncertain if RPC can operate at SLHC rates, particularly
in the endcap
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 18
CMS SLHC L-1 Tracking Trigger
Ideas & Implications for L-1
Additional Component at Level-1
• Actually, CMS could have a rudimentary L-1 Tracking Trigger
• Pixel z-vertex in    bins can reject jets from pile-up
• SLHC Track Trigger could provide outer stub and inner track
• Combine with cal at L-1 to reject 0 electron candidates
• Reject jets from other crossings by z-vertex
• Reduce accidentals and wrong crossings in muon system
• Provide sharp PT threshold in muon trigger at high PT
• Cal & Muon L-1 output needs granularity & info. to combine w/ tracking trig.
Also need to produce hardware to make combinations
Move some HLT algorithms into L-1 or design new algorithms reflecting
tracking trigger capabilities
MTC Version 0 done
• Local track clusters from jets used for 1st level
trigger signal  jet trigger with sz = 6mm!
• Program in Readout Chip track cluster
multiplicity for trigger output signal
• Combine in Module Trigger Chip (MTC) 16 trig.
signals & decide on module trigger output
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 19
Detector Luminosity Effects
HZZ  ee, MH= 300 GeV for different luminosities in CMS
1032 cm-2s-1
1033 cm-2s-1
1034 cm-2s-1
1035 cm-2s-1
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 20
Expected Pile-up at Super LHC
in ATLAS at 1035
• 230 min.bias collisions per 25 ns. crossing Nch(|y|0.5)
• ~ 10000 particles in ||  3.2
• mostly low pT tracks
• requires upgrades to detectors
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 21
CMS ideas for trigger-capable
tracker modules -- very preliminary
• Use close spaced stacked pixel layers
• Geometrical pT cut on data (e.g. 5 GeV):
• Angle () of track bisecting sensor
layers defines pT ( window)
• For a stacked system (sepn. ~1mm), this
is ~1 pixel
• Use simple coincidence in stacked
sensor pair to find tracklets
• More on implementation next slide
Mean pT distribution for
charged particles at SLHC
cut here
-- C. Foudas &
J. Jones
A track like this wouldn’t trigger:
<5mm

Search
Window
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
w=1cm ;
l=2cm
rL
y
rB
x
SLHC Trigger, DAQ, Electronics - 22
CMS Tracker Readout/Trig. Ideas
(very preliminary)
Diode+’Amp’
Column-wise
readout
Comparator
Local Address
Reset/Transfer
Logic
Pipe cell
Data passes
through cell
in each pixel
in column
Bias generator
Timing (DLL)
At end of column, column address is added to each data element
•Data concatenated into column-ordered list, time-stamp attached at front
•
Inner Sensor
c1
Outer Sensor
• If c2 > c1 + 1, discard c1
• If c2 < c1 – 1, discard c2
c2
Column compare
• Else copy c2 & c1 into L1 pipeline
Use sorted-list comparison
•
L1A
Pipeline
L1T
Pipeline
All hits stored for readout
•
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
(lowest column first)
This determines your search window
In this case, nearest-neighbour
SLHC Trigger, DAQ, Electronics - 23
Use of CMS L1 Tracking Trigger
- D. Acosta
Combine with L1  trigger as is now done at HLT:
•Attach tracker hits to improve PT assignment precision
from 15% standalone muon measurement to 1.5% with
the tracker
•Improves sign determination & provides vertex constraints
•Find pixel tracks within cone around muon track and
compute sum PT as an isolation criterion
•Less sensitive to pile-up than calorimetric information if
primary vertex of hard-scattering can be determined
(~100 vertices total at SLHC!)
To do this requires  information on muons
finer than the current 0.052.5°
•No problem, since both are already available at 0.0125
and 0.015°
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 24
CMS Muon Rate at L = 1034
From CMS
DAQ TDR
Note limited
rejection power
(slope) without
tracker information
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 25
CMS SLHC Calorimeter Trigger
Electrons/Photons:
- S. Dasu
• Report on finer scale to match to tracks
-jets:
• Cluster in 2x2 trigger towers with 2x2 window sliding by 1x1 with
additional isolation logic
Jets:
• Provide options for 6x6, 8x8, 10x10, 12x12 trigger tower jets,
sliding in 1x1 or 2x2
Missing Energy:
• Finer grain geometric lookup & improved resolution in sums
Output:
• On finer-grain scale to match tracking trigger
• Particularly helpful for electron trigger
Reasonable extension of existing system
• Assuming R&D program starts soon
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 26
CMS SLHC e// object
clustering
e// objects cluster within a tower or two
• Crystal size is approximately Moliere radius
• Trigger towers in ECAL Barrel contain 5x5 crystals
• 2 and 3 prong  objects don’t leak much beyond a TT
• But, they deposit in HCAL also
ET scale: 8-bits
HCAL
0.087 
e/ ET = 1 x 2 or 2 x 1 sum
e/ H/E cut for all 9 towers
e/ isolation patterns:
0.087 
ET = 3 x 3 sum of E + H
 isolation patterns include E & H:
ECAL
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 27
CMS SLHC e /  /  object track
correlation
Use e /  /  objects to seed tracker readout
• Track seed granularity 0.087 x 0.087  1 x 1
• Track seed count limited by presorting candidates
• e.g., Maximum of 32 objects?
Tracker correlation
• Single track match in 3x3 with crude PT (8-bit ~ 1 GeV)
• Electron (same for muons)
• Veto of high momentum tracks in 3x3
• Photon
• Single or triple track match
• Tau
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 28
CMS SLHC Jet Clustering
Cluster jets using 2x2 primitives: 6x6, 8x8, 10x10
• Start from seeds of 2x2 E+H (position known to 1x1)
• Slide window at using 2x2 jet primitives
• ET scale 10-bits, ~1 GeV
Jet Primitive is sum of ET in E/HCAL
Provide choice of clustering?
10x10 Jet
8x8
Jet
6x6 Jet
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 29
CMS tracking for electron
trigger
Present CMS electron HLT
- C. Foudas & C. Seez
Factor of 10 rate reduction
: only tracker handle: isolation
• Need knowledge of vertex
location to avoid loss of efficiency
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 30
CMS tracking for -jet isolation
-lepton trigger: isolation from pixel tracks
outside signal cone & inside isolation cone
Factor of 10 reduction
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 31
CMS L1 Algorithm Stages
Current for LHC:
TPG  RCT  GCT  GT
Proposed for SLHC (with tracking added):
TPG  Clustering  Correlator  Selector
Trigger Primitives
e /  clustering
2x2, -strip ‘TPG’
Jet Clustering
µ track finder
DT, CSC / RPC
Missing ET
Tracker L1 Front End
Regional Track
Generator
Seeded Track Readout
Regional Correlation, Selection, Sorting
Global Trigger, Event Selection Manager
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 32
CMS SLHC Trigger Architecture
LHC:
• Level 1: Regional to Global Component to Global
SLHC Proposal:
• Combine Level-1 Trigger data between tracking,
calorimeter & muon at Regional Level at finer granularity
• Transmit physics objects made from tracking,
calorimeter & muon regional trigger data to global trigger
• Implication: perform some of tracking, isolation & other
regional trigger functions in combinations between
regional triggers
• New “Regional” cross-detector trigger crates
• Leave present L1+ HLT structure intact (except latency)
• No added levels --minimize impact on CMS readout
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 33
CMS Level-1 Latency
CMS Latency of 3.2 sec becomes 256 crossings @ 80 MHz
• Assuming rebuild of tracking & preshower electronics will store
this many samples
Do we need more?
• Yield of crossings for processing only increases from ~70 to ~140
• It’s the cables!
• Parts of trigger already using higher frequency
How much more? Justification?
• Combination with tracking logic
• Increased algorithm complexity
• Asynchronous links or FPGA-integrated deserialization require
more latency
• Finer result granularity may require more processing time
• ECAL digital pipeline memory is 256 40 MHz samples = 6.4 sec
• Propose this as CMS SLHC Level-1 Latency baseline
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 34
CMS SLHC L-1 Trigger Summary
Attempt to restrict upgrade to post-TPG electronics as much
as possible where detectors are retained
• Only change where required -- evolutionary -- some possible preSLHC?
• Inner pixel layer replacement is just one opportunity.
New Features:
• 80 MHz I/O Operation
• Level-1 Tracking Trigger
• Inner pixel track & outer tracker stub
• Reports “crude” PT & multiplicity in ~ 0.1x 0.1   
• Regional Muon & Cal Triggers report in ~ 0.1 x 0.1   
• Regional Level-1 Tracking correlator
• Separate systems for Muon & Cal Triggers
• Separate crates covering    regions
• Sits between regional triggers & global trigger
• Latency of 6.4 sec
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 35
SLHC DAQ
SLHC Network bandwidth at least 5-10 times LHC
• Assuming L1 trigger rate same as LHC
• Increased Occupancy
• Decreased channel granularity (esp. tracker)
Upgrade paths for ATLAS & CMS can depend on
present architecture
• ATLAS: Region of Interest based Level-2 trigger in
order to reduce bandwidth to processor farm
• Opportunity to put tracking information into level-2
hardware
• Possible to create multiple slices of ATLAS present RoI
readout to handle higher rate
• CMS: scalable single hardware level event building
• If architecture is kept, requires level-1 tracking trigger
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 36
CMS DAQ: Possible structure
upgrade
LHC DAQ design:
- S. Cittolin
A network with Terabit/s aggregate bandwidth is
achieved by two stages of switches and a layer of
intermediate data concentrators used to optimize the
EVB traffic load.
RU-BU Event buffers ~100GByte memory cover a
real-time interval of seconds
SLHC DAQ design:
A multi-Terabit/s network congestion free and scalable
(as expected from communication industry).
In addition to the Level-1 Accept, the Trigger has to
transmit to the FEDs additional information such as the
event type and the event destination address that is the
processing system (CPU, Cluster, TIER..) where the
event has to be built and analyzed.
The event fragment delivery and therefore the event
building will be warranted by the network protocols
and (commercial) network internal resources (buffers,
multi-path, network processors, etc.)
Real time buffers of Pbytes temporary storage disks will
cover a real-time interval of days, allowing to the
event selection tasks a better exploitation of the
available distributed processing power.
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 37
New SLHC Fast Controls,
Clocking & Timing System (TTC)
80 MHz:
• Provide this capability “just in case” SLHC can operate at 80 MHz
• Present system operates at 40 MHz
• Provide output frequencies close to that of logic
Drive High-Speed Links
• Design to drive next generation of links
• Build in very good peak-to-peak jitter performance
Fast Controls (trigger/readout signal loop):
• Provides Clock, L1A, Reset, BC0 in real time for each crossing
• Transmits and receives fast control information
• Provides interface with Event Manager (EVM), Trigger Throttle System
• For each L1A (@ 100 kHz), each front end buffer gets IP address of node to
transmit event fragment to
• EVM sends event building information in real time at crossing frequency using TTC
system
• EVM updates ‘list’ of avail. event filter services (CPU-IP, etc.) where to send data
• This info.is embedded in data sent into DAQ net which builds events at destination
• Event Manager & Global Trigger must have a tight interface
• This control logic must process new events at 100 kHz  R&D
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 38
SLHC DAQ: Readout
Front End: more processing, channels, zero
suppression
• Expect VLSI improvements to provide this
• But many R&D issues: power reduction, system
complexity, full exploitation of commercial datacommunications developments.
Data Links: Higher speeds needed
• Rx/Tx available for 40G, electronics for 10G now, 40G
soon, accepted protocols emerging: G-ethernet, Fibre
Channel, SDH/Sonet
• Tighter integration of link & FE --R&D on both should
take place together
Radiation tolerance: major part of R&D
• All components will need testing
• SEU rate high: more error detection & correction
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 39
SLHC Front End Electronics
Power
- A. Marchioro
• Key problem -- for everyone!
- K. Einsweiler
• Major difficulties: power density & device leakage
• Power impact on services (cooling)
Radiation -- Example: 130 nm Deep Sub-Micron CMOS
• Total Integrated Dose
• Enclosed transistor circuits do well, linear layout some problems
• Single Event Upset
• Higher sensitivity but enclosed transistors give rate ~ 250 nm DSM
• Single Event Lockup
• Not observed and not expected for careful designs
• Tentative Conclusion: better than 250 nm DSM
Complexity
• Modes involve more neighbors due to capacitive cross-couplings
Cost
• Per IC cost is lower but cost of mask set over 0.5 M$ !
• Wafer cost much higher but more IC’s per wafer
• Engineering run: 0.25 m: 150 k$, 0.13 : 600 k$
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 40
SLHC Electronic Circuits
ADC’s -- benefit from technology development
• Today: CMS ECAL in 0.25 m: 11.1 bit @ 40 Ms/s @ 125 mW
• SLHC: Design in 65 nm, apply scaling: 6 bit @ 80 MS/s @ 2.5 mW
Technology Choice
• Tradeoff between power and cost (SiGe BiCMOS vs. CMOS DSM)
• Evaluate 90 nm, 65 nm: long & expensive process (need access to design rules)
Power regulators
• Distribute regulation over many small regulators to save power
• Local DC-DC converters & “Serial powering”: build regulators into chips
Need new designs to save power in digital circuits
• Reduce voltage where possible
• Design architecture to reduce power
• # FF’s, Inverters/FF, Capacitance/Inverter
• Turn off digital blocks when results not needed
• Gate input or clocks to blocks
• Turn off entire chips when not needed (temp monitor)
• Use data compression wherever possible
• If occupancy remains low, transmit hit channels
• For calorimeter data, try Huffman encoding on differences?
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 41
SLHC Link Electronics
Faster link electronics available
- F. Vasey
• Si-Ge & Deep Sub-Micron
Link electronics has become intrinsically rad-tolerant
More functionality incorporated
• Controls, diagnostics, identification, error correction, equalization
Link electronics now available up to 10G
Industrial development mostly digital
• Easier to store, buffer, multiplex, compress
For now all links use LHC crossing clock as timing ref.
• Possible to run with other clocks with buffers (latency)
Optical Links:
•
•
•
•
Transmitters & Receivers available up to 10G & 40G
Variety of fibers available
Variety of packages are available
Possibility to use frequency mult. to better use bandwidth
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 42
FPGA Technology
Available Now:
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8M Usable Gates
1500 Fine Pitch Ball Grid Array Pacakges
1200 (Altera) or 1100 (Xilinx) I/O pins
Core Voltage 1.5 V
Flexible internal clock management
Built in Multi-Gigabit Transceivers: 0.6 - 11 Gbps
Built-in I/O serializer/deserializer (latency)
Upgrade:
• Logic Speed, Usable Gates, Logic Volume plenty
• Use of these devices becomes difficult, limiting factor
• Packaging, routing, mounting, voltages all difficult
• Need to explore new I/O techniques - built in serdes?
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 43
Data Link Technology
Integration:
• Discrete deserializers vs. integration in FPGAs
• Issue: deserializer latency (improving)
Connections:
• CAT6,7,8 cables for 1G and 10G Ethernet
• Parallel Optical Links
• Parallel LVDS at 160 MHz
Backplanes:
• Use cable deserializer technology
• Exploit new industry standard full-mesh and dual-star serial
backplane technology & PCI Serial Express:
• Each serial link operates at 2.5 GHz bit rate (5 GHz in development)
8B/10B encoding  2.0 (4.0) Gbps data rate.
• Issues: latency for deserialization & circuitry for synchronization
Power:
• Providing power & cooling infrastructure a challenge
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 44
SLHC Trigger, DAQ, Electronics
Summary
Significant Challenges:
•Occupancy: degraded algorithms, large event size*
•High trigger rates: bandwidth demands on DAQ*
•Radiation damage: front end electronics
•Increased channel counts, data volume: electronics power
Promising directions for development:
•Use of tracking & finer granularity in Level-1 Trigger
•More sophisticated calculations using new FPGAs
•Higher speed data links & backplanes
•FPGA link/serializer integration
•New DAQ architecture to exploit commercial developments
•Smaller feature size Deep Sub-Micron CMOS for front ends
•Good radiation tolerance with appropriate design rules
•Designs for lower power electronics
•Lower voltages, architecture, shut-off when not needed
W. Smith, U. Wisconsin, CERN Academic Lecture, March 16, 2006
SLHC Trigger, DAQ, Electronics - 45