Transcript chip - ET

5 Packaging Intro
•Ken Gilleo PhD
•ET-Trends LLC
44%
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Package
Chip to PCB
Compatibility
Rerouting
JOINING
WIRING
WIRING
DEVICE
DEVICE
PROTECTION
MEMS
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Thermal
Management
Performance
Enhancement
Reworkability
Enable
repair
PROTECTION
Easy
Assembly
Easy
Testability
Low
Stress
Selective Access
to Environment
Automated
Handling
Standardization
Enable
Mechanical
Movement
Packaging Change Drivers
1. Miniaturization
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Area
Height
Weight
2. Performance
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High lead count
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High frequency; processors, RF
3. MEMS/MOEMS/Nano;
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a new technology cluster
Devices
Nano
~50 Years
PERFORMANCE
~50 Years
MOEMS
Vacuum
MEMS
Solid State
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TIME
Basic Package Elements
• Base; platform; chip carrier
• 1st Level Interconnect (to chip)
• Routing (can be optional)
• 2nd Level Interconnect (to substrate/PCB)
• Enclosure; encapsulant
• Special features
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Thermal management
Ports, windows, other
Packages Element – cont.
• Substrate/Platform/Enclosure
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Rigid organic; BT, etc.
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Flexible organic; polyimide
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Ceramic/glass
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Metal with insulation
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Protection; enclosure, encapsulation, passivation
DIELECTRICS
• Chip Connections (1st level)
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Wire bond
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TAB
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Integrated TAB
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DCA; Flip Chip
DIE
CONDUCTORS
• PCB Assembly (2nd level)
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Fusible: solder spheres/balls/bumps
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Non-fusible: leads, pins, pads
CONDUCTORS
Lead Frames
• Metal – free standing or pre-inserted into dielectric
• Framing structure removed later
• Ceramic hermetic; used for MEMS
• Plastic Near-hermetic; limited use for MEMS
• Finishes for die attach/bonding
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Ag
Pd
Au
Ni
Multiple
Chip Carriers
Chip Carrier: a packaging system for electronic chips (IC’s) that
provides protection and a practical means of connecting to
circuitry.
Fan Out: 2nd Level interconnect
fans outward from 1st level
Conductor and Dielectric
Fan In:
First - 1964
A flex-based package
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Area Array Packages
• Flip Chip
• LGA (Land Grid Array); leadless chip carrier, QFN
• PGA (Pin Grid Array)
• BGA (Ball Grid Array)
• Micro-BGA (CSP)
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Advanced Packaging Types
• Advanced BGAs
• Flex-Based
• MultiChip
• CSP
• Array Molded
PRODUCTIVITY
• Wafer-Level CSP and FC
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Flip Chip
• Perimeter for small I/O count
• Area Array is much more effective
MEMS
MEMS potential
Selective underfill
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Ceramic Packages
• Cofired
Used for MEMS
Hermetic
moderately expensive
• Cast
• Molded
• Open (non-hermetic); chip carrier
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Organic Substrate
• Rigid; mostly epoxies (resin-glass)
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FR4 conventional
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FR4 type non-halogenated
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BT (Bismaleimide-triazine)
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New non-epoxy halogen-free products
• Flexible
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Polyimide
LCP
Limited use for
MEMS
Non-hermetic
Lowest cost
MultiChip Packages
Single-Plane
Cavity type used
MEMS + ASIC, other
Infineon MEMS mic + ASIC chip
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Traditional Stacked
Packaging Steps
• Bond die (chip) to base; die attach)
• 1st Level connect chip; wire bonding
• Enclosure; encapsulant
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Wire Bonding (WB)
• Most common connection
• Gold ball bonding dominants (~ 93%)
• Features
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
Programmable; handles die and package change
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Very versatile
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Universal method
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Fast, automatic, equipment makers keeping pace
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Fully mechanical process
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Clean; no pollution, waste, hazardous materials
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Well-suited for MEMS/MOEMS
Package Protection
• Fabricated cavity enclosure; metal, plastic, ceramic
• Transfer Molding Compounds (solids)
• Glob Top; free flow encapsulant
DIE
• Dam & Fill encapsulants
• Cavity fill encapsulants
• Underfill; 4 basic classes
• Underfill + encapsulant
• Injection molded cavity packages; near-hermetic
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BGA
encapsulants: for protection & handling
DIE
Only suitable for capped MEMS
CAP
MEMS
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Session Summary
• Packaging is very dynamic today
• The package is all about metal & dielectrics
• Challenges are greater than ever
• Chip advances push performance
• WLP is finally gathering momentum
• MEMS is opening up a new packaging industry
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