Transcript Introduction to Nanoelectronics - School of Materials and Mineral

Introduction to
Nanoelectronics and
Fabrication
Dr. Sabar D. Hutagalung
School of Materials and Mineral Resources
Engineering, Universiti Sains Malaysia,
14300 Nibong Tebal, Penang, Malaysia
Nanoscience –
working small,
thinking big
Nano:
From the Greek nanos meaning "dwarf”,
this prefix is used in the
metric system to mean
10-9 or
1/1,000,000,000.
What is Nanotechnology?
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Nanotechnology is the creation of functional
materials, devices, and systems through control of
matter on the nanometer (1 to 100 nm) length scale
and the exploitation of novel properties and
phenomena developed at that scale.
A scientific and technical revolution has begun that
is based upon the ability to systematically organize
and manipulate matter on the nanometer length
scale.
Is this technology new?
In one sense there is nothing new…


Whether we knew it or not, every piece of
technology has involved the manipulation of
atoms at some level.
Many existing technologies depend crucially on
processes that take place on the nanometer
scale.
Ex: Photography & Catalysis
Nanotechnology, like any other branch of science, is
primarily concerned with understanding how nature works.
Why is this length scale so important?
There are five reasons:
 The wavelike properties of electrons inside matter are
influenced by variations on the nanometer scale. By
patterning matter on the nanometer length, it is possible
to vary fundamental properties of materials (for instance,
melting temperature, magnetization, charge capacity)
without changing the chemical composition.
 The systematic organization of matter on the nanometer
length scale is a key feature of biological systems.
Nanotechnology promises to allow us to place artificial
components and assemblies inside cells, and to make
new materials using the self-assembly methods of nature.
Why is this length scale so important?
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Nanoscale components have very high surface areas,
making them ideal for use in composite materials,
reacting systems, drug delivery, and energy storage.
The finite size of material entities, as compared to the
molecular scale, determine an increase of the relative
importance of surface tension and local electromagnetic
effects, making nanostructured materials harder and less
brittle.
The interaction wavelength scales of various external
wave phenomena become comparable to the material
entity size, making materials suitable for various optoelectronic applications.
How Small We can make the grains?
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
Because of high surface areas conventional
powders methods reach their limits at 10-6 m
(1 micron)
Smaller particles can be made but special
methods are needed!
Working at the nanoscale
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Working in the nanoworld was first proposed by
Richard Feynman back in 1959.
But it's only true in the last decade.
The world of the ultra small, in practical terms, is
a distant place.
We can't see or touch it.
Because, optical microscopes can't provide
images of anything smaller than the wavelength
of visible light (ie, nothing smaller than 380
nanometres).
From “There’s Plenty of Room at the Bottom”, Dec 29, 1959
This image was written using Dip-Pen Nanolithography, and imaged using lateral force
microscopy mode of an atomic force microscope.
What is Nanoelectronics

Nanoelectronic device?
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A very small devices to ovecome limits on scalability
Examples:

Single-Electron Transistors


controlled electron tunneling to amplify current
Resonance Tunneling Device

quantum device use to control current
Problem of Making More
Powerful Chips


The number of
transistors on a chip
will approximately
double every 18 to 24
months (Moore’s
Law).
This law has given
chip designers greater
incentives to
incorporate new
features on silicon.
Problem of Making More
Powerful Chips

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Moore's Law works
largely through
shrinking transistors,
the circuits that carry
electrical signals.
By shrinking
transistors, designers
can squeeze more
transistors into a chip.
Problem of Making More
Powerful Chips
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However, more
transistors means
more electricity and
heat compressed into
a smaller space.
Furthermore, smaller
chips increase
performance but also
create the problem of
complexity.
Problem of Making More
Powerful Chips
Band diagram when on
A basic MOSFET
Problem of Making More
Powerful Chips
Quantum and coherence
effects, high electric fields
creating avalanche dielectric
breakdowns, heat dissipation
problems in closely packed
structures as well as the nonuniformity of dopant atoms and
the relevance of single atom
defects are all roadblocks along
the current road of
miniaturization.
Problem of Making More
Powerful Chips
Problem 1:
 Carrier mobility
decreases as
channel length
decrease and
vertical electric
fields increase.
Problem of Making More
Powerful Chips
Problem 2:
 Tunneling through
gate oxide (off
state current).
Eox
Problem of Making More
Powerful Chips
Problem 3:
 Wattage/Area
increases as
density
increases
Single-Electron Transistors (SETs)
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To solve these problem, the
single-electron tunneling
transistor - a device that
exploits the quantum effect of
tunneling to control and
measure the movement of
single electrons was
developed.
Experiments have shown that
charge does not flow
continuously in these devices
but in a quantized way.
Fig. A single-electron transistor
Single-Electron Transistors (SETs)
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SET consists of a gate
electrode that electrostaticaly
influences electrons traveling
between the source and drain
electrodes.
The electrons in the SET need
to cross two tunnel junctions
that form an isolated
conducting electrode called
the island.
Fig. A single-electron transistor
Single-Electron Transistors (SETs)
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Electrons passing through the
island charge and discharge it,
and the relative energies of
systems containing 0 or 1
extra electrons depends on
the gate voltage.
The key point is that charge
passes through the island in
quantized units.
Fig. A single-electron transistor
Single-Electron Transistors (SETs)
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For an electron to hop onto the
island, its energy must equal
the Coulomb energy, e2/2C.
When both the gate and bias
voltages are zero, electrons do
not have enough energy to
enter the island and current
does not flow.
Fig. A single-electron transistor
Single-Electron Transistors (SETs)
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As the bias voltage between
the source and drain is
increased, an electron can
pass through the island when
the energy in the system
reaches the Coulomb energy.
This effect is known as the
Coulomb blockade, and the
critical voltage needed to
transfer an electron onto the
island, equal to e/2C, is called
the Coulomb gap voltage.
Fig. A single-electron transistor
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Left: Equivalent circuit of an
SET
Center: Energy states of an
SET. Top Coulomb blockade
regime, bottom transfer regime
by application of VG=e/2CG
Right: I-V characteristic for
two different gate voltages.
Solid line VG= e/2CG, dashed
line VG =0
Here n1 and n2 are the number of
electrons passed through the tunnel
barriers 1 and 2, respectively, so
that n = n1 - n2, while the total island
capacitance, C∑, is now a sum of
CG, C1, C2, and whatever stray
capacitance the island may have.
Coulomb Blockade
The Coulomb blockade is a single-electron phenomenon, which originates
in the discrete nature of electric charge that can be transferred from a
conducting island connected to electron reservoirs through thin barriers.
The CB allows a precise control of small number of electrons, with
important application in switching devices with low power dissipation and a
corresponding increased level of circuit integration.
Single-electron devices based on the Coulomb blockade.
Tunneling & Q Blockade in
SET
DOT
Q transport by single-electron
tunneling, but essentially
suppressed by Coulomb charging
energy:

Ec > kbT (Ec = e2/2CΣ)

Tunneling resistance, Rt > Rk
(Junction resistance,
Rk = h/e2 = 25.8 K)
I-V curve controlled by gate
voltage, showing region of QB
Silicon SET
Silicon nanowire transistors
Enhanced Channel Modulation in Dual-Gated Silicon
Nanowire Transistors
Nano Letters Vol. 5, 2005, 2519-2523
(a) Schematic of a NW FET, and (inset)
FE-SEM image of a GaN NW FET.
(b) Gate-dependent I–Vsd data recorded on
a 17.6 nm diameter GaN NW. The gate
voltages for each I–Vsd curve are
indicated;
(c) I–Vg data recorded for values of Vsd.
(Inset) Conductance, G, vs gate voltage
C.N.R. Rao et al. / Progress in Solid State Chemistry 31 (2003) 5–147.
ZnO nanorod FETs
(a) Schematic side view and
(b) field-emission scanning
electron microscopy (FESEM)
image of a ZnO nanorod FET
device.
ZnO nanorod FETs with backgate
geometry were fabricated on SiO2/Si by
deposition of Au/Ti metal electrodes for
source-drain contacts on nanorod
ends.
Park et al., APL, 85 (2004) 5052-5054
(a) Typical Isd–Vsd characteristic
curves as a function of Vg for ZnO
nanorod FETs. The linear and
symmetric Isd–Vsd curves were
obtained under different Vg,
indicating the low resistant ohmic
contact formation between ZnO
and Ti metal layers.
(b) Isd–Vg curves of ZnO nanorod
FETs show that the devices
operate in an n-channel depletion
mode with gm of ~140 nS for Vsd =
1.0 V.
Park et al., APL, 85 (2004) 5052-5054
FET fabricated based on
In2O3 nanowires:
(a) I–V curves recorded
on an In2O3 nanowire of
10 nm diameter,
(b) I–Vg data of the same
device at Vds = 10 mV.
Inset shows the SEM
image of the nanowire
between the source and
drain electrodes.
Direct Integration of Metal Oxide Nanowire in Vertical
Field-Effect Transistor
Nano Letters Vol. 4, 2004
Carbon Nanotube Transistor
Nanoelectronic
Fabrication
Nanofabrication
Top-down
Approach
Bottom-up
Approach
Top-down vs Bottom-up
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Top-down techniques take a bulk material, machine it, modify it into the
desired shape and product

classic example is manufacturing of integrated circuits using a sequence of steps
sush as crystal growth, lithography, deposition, etching, CMP, ion implantation…
(Microelectronic/Nanoelectronics Fabrication Approach)
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Bottom-up techniques build something from basic materials
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
assembling from the atoms/molecules up
not completely proven in manufacturing yet
Examples:
 Self-assembly
 Sol-gel technology
 Deposition (old but is used to obtain nanotubes, nanowires, nanoscale
films…)
 Manipulators (AFM, STM,….)
Top-down
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From large items to smaller ones.
The most common method are
electron beam lithography (EBL) and
scanning probe lithography (SPL).
The approach involves molding or etching materials
into smaller components.
Making IC?
Starting with a thin sheet Si wafer,
cleaned, coated, preferentially
etched using highly focused optics in
as many as 100 separate operations
before the final IC is complete.
Bottom-up
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A general approach
going from small items
to bigger ones.
Building larger, more
complex objects by
integration of smaller
building blocks or
components.
• The sketch shows the essence of
bottom-up manufacturing.
• Self-assembly from the gaseous
phase.
• Two principle vapor-phase
technologies that are useful and
widely practiced:
molecular beam epitaxy (MBE) and
vapor-deposition (PVD, CVD).
Fabrication of SET
SET with a nano particle
SET with a nano particle connected
by SWCNs
Fabrication of SET
FIG. (a) Sketch of the SOI
nanowire: a metallic top gate
is separated from the SiNW
by a 55 nm silicon oxide.
(b) SEM micrograph of the
nanowire with a width below
10 nm and a length of 500
nm.
PHYSICAL REVIEW B 68, 075311 (2003)
Fabrication of SET
Non-Lithographic Positional Control
of SiNWs
Fig. Patterning of
SiNWs.
(A) Overview and (B)
zoomed in image of
patterned lines of
vertical SiNWs grown
from lines of single
nanoparticle catalysts
deposited onto a Si
substrate.
(C) A crosssection SEM
image of nanowires that
were positionally
aligned into lines.
The scale bar in images (A), (B), and (C) correspond to 100 µm, 1 µm, and 1µm.
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
Vertically Integrated Nanowire Field
Effect Transistors (VINFET)
Fig. Si VINFET fabrication. (A) SiNWs are grown vertically from a Si(111)
substrate. (B) Thermal oxidation of the Si nanowire is used to form the gate
dielectric. (C) The Cr gate material is then sputtered onto the nanowires to
achieve a conformal coating.
Blue corresponds to the Si substrate and the SiNWs channel, grey is SiO2 dielectric
material, and red corresponds to the Cr gate metal.
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
Fig. Si VINFET fabrication. (A) Conformal LPCVD oxide is deposited around the
nanowire. (B) The Cr-coated nanowire tips are exposed via chemomechanical
polishing and plasma etching of the SiO2 dielectric. (C) The Cr gate material is
etched-backed using a Cr photomask etchant. (D) An SEM image taken after the
SiO2 deposition. (E) An SEM image showing the exposed Cr-coated tips. (F) an
SEM image of the device after the Cr etch back procedure.
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
Fig. Si VINFET fabrication. (A) Another layer of LPCVD SiO2 is deposited
onto the nanowire. (B) The nanowire tips are exposed via plasma etching of
the SiO2 dielectric. (C) Ni / Pt contacts are sputtered onto the sample to form
the drain electrode. Cr gate material is then sputtered onto the nanowires to
achieve a conformal coating.
Yellow corresponds to the Ni drain material.
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
Threshold Voltage Analysis
In the case for our system (p-type nanowires) with a Cr gate electrode, the
threshold voltage (Vt);
Where VFB is the flatband voltage, NA is the acceptor concentration in Si, C is the
oxide capacitance, εs is the oxide permittivity, and φs is the surface potential.
Since the onset of accumulation for an metal-oxide-semiconductor system occurs
when the surface potential is zero, the threshold voltage is equal to the flatband
potential. VFB can be deduced by the following equation;
Where ΦM is the gate work function, χ is the electron affinity of Si, and Eg is the
band gap of silicon. ΦF is given by the formula;
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
Threshold Voltage Analysis
Where ni is the intrinsic carrier concentration in Si.
More accurate analyses of the influence of carrier concentration on
threshold voltage at these small length scales can be derived using
drift-diffusion simulations.
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
Fig. Ultra-thin body VINFET.
(A) Cross-sectional SEM image. The
scale bar is 200 nm. Blue is Si
source, grey SiO2 dielectric, red the
gate material, and yellow the drain
metal. The SiNW is not colored, due
to the inability of resolving this
feature via SEM.
The Cr coverage on the front of the
wire was likely stripped during
cleavage.
(B) Ids vs Vgs with Vds ranging from -1.0 V to -0.2 V in 0.2 V steps, from top to
bottom, respectively, measured from a device with 48 nanowires in parallel.
(C) TEM image of a 6.5 nm SiNW, obtained from the device used in (A).
Scale bar is 100 nm. A typical device has a ~6-7 nm SiNWs diameter,
surrounded by a ~30- 35 nm thick shell of SiO2, and a Cr metal gate length of
~300-350 nm.
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
Fabrication Approaches to Nanowires
Devices

Removing the nanorods/nanowires from the initial growth susbtrate
is by sonification in a solvent such ethano.
Fig. shows ZnO nanorods after
growth on the Si substrate (left)
and after 5 min sonification in
ethanol (right).
The acoustic energy supplied
to the solvent is enough to
dislodge a large fraction of the
nanorods and disperse them
into the solution.
It was found that >90% of the
nanorods could be harvested in
this manner.
Mater. Sci. Eng. R 47 (2004) 1–47
Transfer of the nanorods from the ethanol solution to a new
substrate is by dispersing the solution onto the new
substrate, followed by evaporation of the ethanol.
The advantage of this approach is simplicity but the main
drawback is the random nature of where the nanorods are
placed.
The approach
The approach is to initially prepare an SiO2-coated Si wafer and etch alignment
marks into the SiO2.
Once the NWs are on this new substrate, a mask design for the particular device
being fabricated using software on an e-beam writer and then transferred
lithographically so that the ends of the NWs are covered by Ohmic contact pads.
Fig. Schematic of ZnO nanowire depletionmode FET.
Fig. SEM micrographs of structure for transport measurements of ZnO
nanowires (top) and close-up of central region (bottom).
SET Fabrication Using EBL
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Wafer Cutting (sample size 15 mm X 15 mm)
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Wafer Cleaning (Standard Cleaning 1)

Substrate Heating Up (200ºC, 30 minutes)
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Spin Coating (3000 rpm spin speed, 30 seconds)
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Pre-bake Hotplate (90ºC, 2 minutes)
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E-beam Exposure (Exposure e-beam doses variation)
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Development (ma-D 532, 25 seconds)

Rinse in Stopper (De-Water, 5 minutes)
Uda Hashim et al, UniMAP
Source-Drain & Quantum Dot Design Mask
SET Mask Design using GDSII
Editor
SET Mask design schematic
Uda Hashim et al, UniMAP
Nanodevices Patterned
Using SPL
(Scanning Probe Lithography)
Scanning probe microscope (SPM):
from STM to AFM
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SPM was originated from the scanning tunneling
microscopy (STM).
SPM is a relatively new family of microscope that
can
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
measure surface morphology down to atomic resolution,
3D imaging, and
Metal Tip
make nanopatterns (line or dot arrays).
e- cloud
STM uses the tunneling current flowing
between tip and sample to map the
topography.
STM is limited to conductive samples.
Tunneling Current
Sample
Scanning probe microscope (SPM):
from STM to AFM
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Atomic Force Microscopy (AFM) extended the
applications of SPM
For conductive & non-conductive samples, even in
solutions.
AFM measures the attractive or repulsive forces
between the tip and sample.
Many surface/interface properties (mechanical,
magnetic, electric, optical, thermal, chemical properties)
can be measured using AFM.
AFM also used for fabrication of various nanostructures
patterns (AFM-based nanolithography).
Comparison of SPM and other Microscope
10 mm
SEM
Z Resolution
15 um
10 um
Optical
Microscope
TEM
10 nm
SPM
10 pm
10 nm
0.2 nm
10 um
800 um 10 mmX,Y Resolution
Applications of Multi-function SPM
Semi- Ferroelectric
conductor
device
Ｓｉ
ＧａＡｓ
Topography
Mechanical
Electric
Magnetic
Optical
Processing
Memory
Thin film
Storage Inorganic Polymer Biotechnology
device
Glass
Plastic
Protein
HD
ＣＤ・ＤＶＤ
Memory
Ceramics
Metal
Rubber
Cell
ＤＮＡ
Ra ・ Particle & grain analysis ・ Pitch & height measurement
VE ・ Friction ･ Adhesion ･ Hardness（Nano-indentation）
Leak Current ･ Polarization ・ Dielectric constant ・ Surface Potential
Magnetic Force ・ Magnetic Domain & Flux
Fluorescence ・ Spectrum ･ Optical Transition ･Optical Record
Lithography ・ Manipulation ･ oxidization ･ Scratch
Scanning Probe Lithograpy (SPL)

One of the most methods is local anodic
oxidation (LAO) by AFM
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

where the application of a +ve voltage to the
surface with respect to the tip
in humidity atmosphere.
By controlling the certain condition between
the AFM tip and the sample, desired
nanopatterns can be created.
Experimental Method
SPI3800N Series
with SPA-300HV
Silicon wafer
(n-type 100)
RCA Cleaning
(RCA 1 & RCA 2)
Passivated
(5 % HF 10 s)
NanoNavi (vector & raster scan),
conductive AFM tip (coated Rh,
TIP  20 – 30 nm)
NanoPatterning
(by AFM)
Surface Analysis
(by AFM)
Vector Scan
Cantilever
Scan
0.2μm
Before
Electrolyte Oxidation
After
AFM Lithography (Si wafer) by electrolyte oxidation
Raster Scan
BMP file of design
- Fine fabrication by Raster Scan -
Recall BMP file
Nano dots
After fabrication（２０μｍ□）
Symbol
on Si wafer
image by
sample
Raster scan
（D: ６０ｎｍ）
200nm
500nm
By：Nano function Project team NITS Nano Tech. depart.
Vector Scan、 Raster Scan
- Influence of absorbed water layer
Fabrication by
Raster scan
Measurement
area 2μm
Apply 5V
Voltage to 1μm
area
200nm
200nm
Air
Vacuum（4×10-6Torr）
Scratch and Oxide Line
SCRATCH LINE
OXIDIZED DOT
OXIDIZED LINE
Single dot, double dots, and triple dots patterned on silicon surface
at -8V tip bias voltage with different oxidation time.
3 ms
8 ms
5 ms
1 ms
Dot Oxide Array on Si (100) wafer
( h  10 nm and w  200 nm )
Oxide Dot Array (Surface Profile)
Line Oxide
Line Oxide (With Profile)
LAO Mechanism
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Schematic diagram of localanodic-oxidation (LAO)
process performed by AFM.
The oxides grow on substrate
by the application of a voltage
between a conductive tip
(cathode) and a substrate
(anode).
Water molecules adsorbed on
a substrate dissociates into
fragments (e.g. H+, OH-, and
O2-) and acts as electrolyte.
Cervenka et al., Appl. Surf. Sci., 253 (2006) 2373.
T.-H. Fang, Microelectronics Journal, 35 (2004) 70.
LAO Mechanism
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Schematic diagram of localanodic-oxidation (LAO)
process performed by AFM.
At the Si/SiO2 interface, OHreact with holes h+ as follow:
Si + 4h+ + 2OH− 
SiO2 + 2H+
The proton concentration
increases after long pulse
times, with the
H+ + OH−  H2O
neutralization reaction.
Cervenka et al., Appl. Surf. Sci., 253 (2006) 2373.
T.-H. Fang, Microelectronics Journal, 35 (2004) 70.
SET Pattern
SET Pattern
SET Pattern (Profile)
SET Pattern (Profile)
SET Pattern (Profile)
USM letter Oxide on Si (100) wafer
Summary
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Nanoelectronics is not only about size but also
phenomena, mechanism, etc.
Nanoelctronics is a wide open field with vast
potential for breakthroughs coming from
fundamental research.
Some of the major issues that need to be addressed
are:



Understand nanoscale transport (theory & experimental).
Develop/understand self-assembly techniques to do
conventional things cheaper.
Find new ways of doing electronics and find ways of
implementing them (e.g. quantum computing; hybrid Sibiological systems; cellular automata).