Transcript Tunable Sensors for Process-Aware Voltage Scaling

Tunable Sensors for
Process-Aware Voltage Scaling
Tuck-Boon Chan‡ and Andrew B. Kahng†‡
CSE† and ECE‡ Departments, UCSD
[email protected], [email protected]
http://vlsicad.ucsd.edu
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Outline
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•
•
•
•
Intro: Adaptive Voltage Scaling (AVS)
Overview of Proposed Method
Voltage Scaling Properties
Designing the Circuit
Results
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Adaptive Voltage Scaling
Maximum
frequency
reduce voltage  meet
performance with less power
a typical chip
margin
worst-case scenario
(e.g, due to process variation)
f target
Voltage
Vnominal
• Circuits are designed to guardband for
performance variation
• There is margin for typical chips
• Adaptive voltage scaling (AVS) adjusts
voltage to reduce power
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Taxonomy of AVS Techniques
AVS classes
Power
Open-Loop
AVS
approaches
Freq. & Vdd LUT
AVS
Pre-characterize LUT [Martin02]
Post-silicon
characterization
Process-aware AVS
Post-silicon characterization [Tschanz03]
Generic monitor
ClosedLoop AVS
Error
Tolerance
AVS
Design dependent
replica
Process and temperature-aware AVS
Generic on-chip monitor [Burd00]
Design-dependent monitor [Elgebaly07,
Drake08, Chan12]
In-situ
monitor
In-situ performance monitor
Measure actual critical paths [Hartman06,
Fick10]
Error Detection
System
Error detection and correction system
Vdd scaling until error occurs
[Das06,Tschanz10]
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Motivation for Closed-Loop AVS
[Hartman06]
• Closed-loop AVS saves up to 62% dynamic power
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Classes of Closed-Loop AVS
ClosedLoop AVS
Generic monitor
Design-dependent
replica
• Does not capture
design-specific
performance variation
In-situ
monitor
• Critical path may be difficult to identify
(IP from 3rd party)
• Calibrating monitors at multiple
modes/voltages requires long test time
This work: Tunable monitor for closed-loop AVS
• Can be applied as a generic monitor
• Or tuned to capture design-specific performance
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Outline
•
•
•
•
•
Intro: Adaptive Voltage Scaling (AVS)
Overview of Proposed Method
Voltage Scaling Properties
Designing the Circuit
Results
7
Voltage Scaling Key Concepts
Max. freq.
f target
Process
distance
k
SS
f
Scaling rate =
V
Vmin_path (k )
Vnom Voltage
• Process distance: process-induced frequency shift
relative to target frequency
• Scaling rate: frequency shift (f) per unit voltage
difference (V)
• Vmin= Minimum Vdd to meet target frequency
• Calculated from process distance and scaling rate
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Monitor Design Concept
• Use Vmin of ring-oscillator (RO) as a reference
• Design ROs with worst-case voltage scaling
properties  an arbitrary circuit will meet
target frequency at Vmin_ro
Process corner A
Critical
paths
Freq.
Process corner B
Critical
paths
RO
Freq.
RO
f target
f target
V
V
Max. Vmin of ROs
> Max. Vmin of paths
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Proposed Method: Tunable Monitor
Scenario 1: Without circuit information
• Configure RO for worst-case Vmin
• Guardband for arbitrary circuits
Scenario 2: With chips at process corners
• Extract Fmax and Vmin of chips
• Tune voltage scaling properties of ROs
so that Vmin_ro > Vmin_chip
• Recover margin with one calibration
Store
config.
• Our focus is on voltage scaling property
 analyze worst-case voltage scaling
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Problems
• Goal: Vmin_ro > Vmin_path
• Questions:
Vmin of arbitrary
 Given a process
critical paths
technology, what is the
freq.
range of the Vmin that is
Path A Path B
Path C
defined by process
distance and scaling rate
f target
for arbitrary critical paths?
V
 What circuit techniques
Vmin = ?
can “tune” Vmin?
Also, V changes at
min
different process corners 11
Outline
•
•
•
•
•
Intro: Adaptive Voltage Scaling (AVS)
Overview of Proposed Method
Voltage Scaling Properties
Designing the Circuit
Results
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Vmin Analytical Derivation
(1) Vmin
proce ssdistance
 Vnom 
scalingrate
f path (k ,Vnom )  ftarget
 Vnom  Scaling
f path (k ,Vnom Process
 V )  f path (k ,Vnom )
rate
distance
(2) fpath = inverse of average delays of NMOS & PMOS
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f path (k ,Vnom ) 
Dnmos (k ,Vnom )  Dpmos (k ,Vnom )
(3) Calculate delays with
• Elmore delay model
• Effective currents of transistors
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Normalized Vmin
Vmin Sensitivity
1.020
1.010
1.000
0.990
0.980
0.970
fanout
Ron NMOS
lwire length
Ron PMOS
beta

0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8
Normalized value of circuit parameters
Vmin for
PMOS only
Vmin for
NMOS only
• Vmin is not very sensitive to fanout, interconnect load, etc.
• Empirically, bounds on Vmin determined by NMOS and
PMOS
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Effects of Fanout and Series Resistance
Vmin (V)
SS
TT
FF
SF
FS
1.00
0.90
0.80
0.70
0.60
FO1
SS
FO2
FO4
FO8
Fanout
TT
FF
SF
FS
Vmin (V)
1.00
0.90
0.80
0.70
0.60
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• Fanout has little effect
on Vmin
High series resistance
reduces Vmin
 But, need long wires
100 200 400 800 1600
Series resistance (ohm)
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Effects of Cell Type
SS
TT
FF
SF
FS
Vmin(V)
1.10
1.00
0.90
0.80
0.70
0.60
0.50
Cell type
• Cell type affects Vmin
• Maximum Vmin at different corners are determined
by different cell types
• Stacking causes cell delay biased to PMOS or NMOS
 changes device characteristics and Vmin
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Effects of Cell Strength
1.10
1.00
0.90
0.80
0.70
0.60
0.50
TT
FF
SF
FS
SS
TT
FF
SF
FS
1.10
1.00
0.90
0.80
0.70
0.60
0.50
Vmin (V)
Vmin (V)
SS
X1 layout
X2
X3
Cell
changes device
X0
X1
X2
X3
NAND3 cell strength
INV. cell strength
characteristics and Vmin
X0
• Vmin does not increase from X1 to X3
• But increases from X0 to X1
• X1 to X3  {1,2,3} fingers, same device characteristic
• X0 to X1  Both 1 finger but different diffusion area
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Outline
•
•
•
•
•
Intro: Adaptive Voltage Scaling (AVS)
Overview of Proposed Method
Voltage Scaling Properties
Designing the Circuit
Results
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Design of RO with Tunable Vmin
• Identified two circuit knobs to tune Vmin
• Series resistance
• Cell types (INV, NAND, NOR)
• Proposed circuit
• ROs with different cell types (worst-case Vmin are
determined by different cells at different process corners)
• Tune Vmin  a configurable series resistance at each stage
Control pins
1 bit
1 bit
1 bit
High resistance
Low resistance
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Tunability
Vmin(V)
• Vmin decreases linearly with % high-resistance
passgates
• ROs with different gate types have similar trend
1.100
1.000
0.900
0.800
0.700
0.600
0.500
INVX3
SS
TT
FF
SF
FS
0% 12% 24% 36% 48% 61% 73% 85% 100%
High resistance passgates (%)
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Outline
•
•
•
•
•
Intro: Adaptive Voltage Scaling (AVS)
Overview of Proposed Method
Voltage Scaling Properties
Designing the Circuit
Results
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Experiment Methodology
• Goal: Validate PVS ROs in simulation
• Check Vmin of ROs vs. Vmin of paths
• with arbitrary circuits and process variation
• Experiment setup:
• 65nm industrial technology
• Implement 3 testcases (arbitrary circuits)
• Implement 3 tunable ROs (INV, NAND, NOR)
Power (mW)
Area (mm2)
Freq. target
FPU
4.1
0.015
710
TLU
438.0
0.098
507
MUL
19.8
0.050
1042
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Process Variation Setup
• Simulate critical paths and ROs with SPICE
 200 Monte Carlo samples (global variation)
• 4 variation sources, Gaussian distributions
Variation sources
NMOS Vth
PMOS Vth
Channel length
Gate oxide thickness
mean
0
+/- 3 sigma
30mV
0
0
0
30mV
5nm
0.06nm
• Difference between slow and fast corners
define +/- 3 sigma values of variation sources
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Vmin Extraction and Comparison
• Define ftarget of chip and ROs at
 “slow-slow” process corner
 nominal voltage = 1.0V
• Vmin_chip = max. Vmin of critical paths of a testcase
• Vmin_est = max. Vmin of 3 ROs
• For each testcase, calculate Vmin_est - Vmin_chip of
every Monte Carlo sample
• A chip is safe when Vmin_est - Vmin_chip > 0
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Scenario 1: Guardband for Arbitrary Circuit
• Vmin_est - Vmin_chip > 0 under
process variation
• Similar results for different
testcases
• Small difference between
normal and tunable ROs
 due to series passgates
TLU
testcase
FPU
testcase
MUL
testcase
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Scenario 2: Tune ROs for Margin Reduction
• Extract Vmin_chip at different process corners
• Configure % high-resistance passgates
min. :
{V
min_est
(k )  Vmin_chip (k )}
k
s.t. :
Vmin_est (k )  max {Vmin_ro (k , i, c)}
i
Vmin_est (k )  Vmin_chip (k ),k
Ensures Vmin_est guided by ROs is always safe
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Experiment Result on Tunability
Aggressive config.
 Vmin_est < Vmin_chip
 Some chips will fail
Optimized config.
• Increase % high
resistance passgates
• Vmin_est ≈ Vmin_chip
Default config.
• Low resistance
passgates
• Guardband for
worst-case
• Vmin_est > Vmin_chip
• 13mV margin
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Experiment Result on Tunability
Aggressive config.
 Vmin_est < Vmin_chip
 Some chips will fail
Optimized config.
• Increase % high
resistance passgates
• Vmin_est ≈ Vmin_chip
Default config.
• Low resistance
passgates
• Guardband for
worst-case
• Vmin_est > Vmin_chip
• 13mV margin
Benefits of tunability
• Recover voltage margin
• Compensate for difference between
SPICE model vs. silicon
• Recover margin when chip performance
variation is reduced due to
improvements in chip manufacturing
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Summary
• Monitor design based on voltage scaling properties
• Estimate the worst-case voltage scaling property
across different process corners
 Does not require information about critical paths
 Can be used as an IP for arbitrary circuits
• Recover margin if fmax of sample silicon is available
• Future works
 Proof of concept silicon
 Account for performance variation due to layout
context
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Thank you!
[email protected], [email protected]
http://vlsicad.ucsd.edu
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Backup Slides
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Effects of Pass Gates
• Pass gate is equivalent to large resistance
• Vmin decreases with fewer parallel pass gates
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Effects of Cell Type and Strength
• Key observations: Vmin is affected by cell types
Use NAND, NOR type ROs
• Cell strength changes Vmin
 Use cells with large Vmin
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