Transcript The new challenge of hybrid pixel detectors at CPPM

USTC, April 11, 2013
Patrick Pangaud - CPPM-IN2P3-CNRS
CURRENTLY AND
ADVANCED PIXEL
DESIGNS FOR HEP
Patrick Pangaud
Centre de Physique des Particules de Marseille
C.P.P.M
163, avenue de Luminy
Case 902
13288 Marseille cedex 09
France
[email protected]
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Patrick Pangaud - CPPM-IN2P3-CNRS
HYBRID PIXELS SENSOR
FOR HIGH ENERGY PHYSICS
IBM 130nm : FEI4 development
TSMC 65nm : FEI5 develpment
TEZZARON 3D 130nm: FETC4 developments
HVCMOS development
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Hybrid Pixels Detector
for LHC/HL-LHC at CERN
Whatever will be discovered in next years
at LHC, need much data to understand
what has been discovered.
Higher luminosity allows extending
discovery/studies to
• higher masses
• processes of lower cross-section
LHC has plans of upgrade by increasing
luminosity to collect ultimately ~ 3000 fb-1 .
This will open new physics possibilities.
LHC : Luminosity of 1034 cm-2.s-1
HL-LHC expected 10 times more luminosity, more
pixels, more ionizing particles, more … !!!
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Patrick Pangaud - CPPM-IN2P3-CNRS
Inner Tracking ATLAS detector
Straw tubes
Silicon strip
Silicon pixel
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LHC and ATLAS upgrade
Possible upgrade timeline
→14 TeV
→ 5x1034cm-2s-1
luminosity leveling
∫ L dt
7 TeV
1x1034 →
~2x1034cm-2s-1
3000 fb-1
phase-2
→ 1x1034cm-2s-1
1027 →
2x1033cm-2s-1
~300 fb-1
phase-1
~50 fb-1
phase-0
~10 fb-1
2013/14
Now
T. Kawamoto, TIPP2011, Chicago, USA
2018
~2022
Year
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Patrick Pangaud - CPPM-IN2P3-CNRS
ATLAS upgrade
• LHC improves, bulk of luminosity with instantaneous luminosity beyond the
nominal luminosity for which the ATLAS detector was designed and built.
• Technology improves, can build better performing detector now.
• Detectors age, after the nominal integrated luminosity has been collected,
leading to deterioration of performance during the runs at higher luminosity.
• It will take long time to study and build new detector
• Installation has to be done during the limited number of long shut downs
• Installation has to be planned to be prepared to the new running condition
T. Kawamoto, TIPP2011, Chicago, USA
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HYBRID PIXELS SENSOR
FOR HIGH ENERGY PHYSICS
IBM 130nm
FE-I4 DEVELOPMENT
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50 μm
Hybrid Pixels Sensor for HEP
The FE-I4 readout chip
FE-I3 CMOS
technology : 250 nm
Done : ATLAS/LHC
(2008/2009)
50 μm
400 μm
FE-I4 CMOS
technology : 130 nm
250 μm
Under Production
ATLAS/LHC upgrade project
(2013-2014)
• Participating institutes:
FE-I3
18
160
FE-I4
Bonn: D. Arutinov, M. Barbero, T. Hemperek,
A. Kruth, M. Karagounis.
CPPM: D. Fougeron, M. Menouni.
Genova: R. Beccherle, G. Darbo.
LBNL: S. Dube, D. Elledge, M. Garcia-Sciveres,
D. Gnani, A. Mekkaoui.
Nikhef: V. Gromov, R. Kluit, J.D. Schipper
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FE-I4 : Motivation for Redesign of FE
• Need for a new FE?
FE-I3FE-I4
• Smaller b-layer radius + potential luminosity increase
architecture saturated.
FE-I3 at r=3.7 cm!
FE-I4 new digital architecture:
EOC
sLHC
80
IBL
FE-I3 column-drain
100
60
40
20
LHC
Inefficiency [%]
higher hit rate.
0
0
local regional memories,
stop moving hits around (unless RO).
FE-I4 has smaller pixel
0.25 μm130 nm
(reduced cross-section).
1
2
3
4
5
6
7
8
9
10
Hit prob. / DC
The “inefficiency wall”
• New technology: Higher integration density for digital circuits, rad-hard, availibility.
M. Backhaus, FEI4 course, Desy, Germany
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Future FE-I4-Based Module
and Consequences for FE-I4
Flex
MCC
1
FE-Chip
Sensor
3
4
FE-Chip
5
Sensor
2
1
3 FE-Chip
4
2
1) Big chip (periphery on one side of module).
2) Reduce size of periphery (2.8 mm2 mm).
3) Thin down FE chips (190 μm90 μm).
4) Thin down the sensor (250 μm 200 μm)?
5) Less cables (powering scheme)?
• Increased active area: from less than 75 % to ~90 %:
 Reduced periphery; bigger IC; cost down for sLHC (main driver is flip-chip costs per chip).
• No MCC:
 More digital functionality in the IC.
challenging: power (routing, start-up), clk.
distrib., simulation / management, yield
• Power:
 Analog design for reduced currents; decrease of digital activity (digital logic sharing for
neighbor pixels); new powering concepts. 8 metal layers [2 thick Alu.]  power routing.
M. Backhaus, FEI4 course, Desy, Germany
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Motivation for Redesign of FE
• Need for a new FE?
• Accommodate higher hit rate (smaller b-layer radius + luminosity increase) 
•
•
•
•
Architecture based on local memories (no column-drain mechanism).
Smaller pixel size: enhanced granularity and reduced cross-section.
Reduced periphery & bigger chip: higher active area fraction (<75%  ~90%);
cost down for sLHC (main driver is flip-chip, costs per chip).
Big chip a challenge: power (routing, start-up), clk. distrib., yield…
Simple module: No Module Controller  More digital functions into the FE.
Power efficient design & new concepts: Analog design for reduced currents;
decrease of digital activity (digital logic sharing for neighbor pixels); new
powering concepts. 8 metal layers [2 thick Alu.]  Power routing.
• New technology:
• Higher integration density for digital circuits, radiation-hardness (no Enclosed
Layout Transistor), availability on timescales of our experiments.
M. Backhaus, FEI4 course, Desy, Germany
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FE-I4 : architecture
4-pixel region
analog 1-pix
pixel array:
336×80 pixels
digital 4-pix
DDC
EODCL
EOCHL
DOB
CMD DCD
periphery
CLKGEN
Power
Pads
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FE-I4 : Digital Region (simplified)
- Hit Processing
- ToT Counter
- ToT Memory
- Latency Counter
- Triggering/Readout
M. Backhaus, FEI4 course, Desy, Germany

Receiving hit

Generate leading edge

Start ToT counter

Assign first free memory
and latency counter

Generate trailing edge

Store ToT value

Check for trigger when
latency counter finished

Indicate ready to read status
(release token)

Read memory

Release memory after read
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HYBRID PIXELS SENSOR
FOR HIGH ENERGY PHYSICS
TSMC 65NM
FE-I5 DEVELOPMENT
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65nm motivations
• For the HL-LHC (Phase 2) a new pixel detector is planned
• 2 removable internal layers are planned ( 3.9 cm – 7.5 cm)
• The event rate is high and the FE-I4 architecture is not adapted
• The Total Dose is ~ 1GRad
• A new design is required
• Reduction of the pixel size for the inner layers
• R&D : CMOS 65 nm, 3D, Monolithic design
CMOS 65 nm is an attractive solution for the development of high-density
readout IC.
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65nm prototyping



TSMC 65 nm process allows good tolerance to SEU.
However the tolerance of TSMC-ARM digital cells have to be
investigated for high dose level : 1000 Mrad
Dose effect : Simulations are in progress to check if there are
“sensitive” devices inside the Library DFF cell.
New designs are in development :



different structures of configuration memories,
IP blocs : ADC, Voltage reference
First submission of 65nm CMOS IP blocks (plus individual
narrow test transistors) is foreseen at CPPM in June or
September 2013.
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HYBRID PIXELS SENSOR
FOR HIGH ENERGY PHYSICS
TEZZARON 3-D 130nm
FE-TC4 DEVELOPMENT
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3-D motivations for
ATLAS read-out chip upgrades
• Improve spatial resolution
Decrease pixel size
•50 μm
• Deal with an increasing counting rate
FE-I3 ,
250 nm
400 μm
Vertical stacking
FE-I4 ,
130nm
•50 μm
•50 μm
Technology shrinking
250 μm
ANALOG
DIGITAL
FE-TC4 ,
130 nm
125 μm
First MPW run for High Energy Physics organized by
FNAL with a consortium of 15 institutes.
The proposed 3-D process combines :
GLOBAL FOUNDRY 130nm technology
TEZZARON 3D technology
3-D benefits :
Pixel size reduction
Functionalities splitting
Technologies mixing
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Context : Pixel trackers for high luminosity
• HL LHC : high luminosity, high pile up, high dose
To keep the tracker performance one need to improve pixel granularity :
• reduce occupancy , improve resolution (and 2 tracks separation) , reduce
inefficiencies in the readout.
Several ways for hybrid pixels detectors
•
• move to higher density technologies like 65 nm (shrinking technology )
• move to 3D electronics with in-pixel TSVs
(vertical stacking)
• move to CMOS HV (where the sensor can be in the same circuit as the analog
50 μm
amplification)
250 μm

Needs in-pixel communication
between the 2 tiers  small TSV

Main 3D advantage : Adequate
techno selection for the various
functions

Main 3D drawback : Not so easy at
the moment
50 μm
FE-I4 CMOS 130 nm
3D goal : Reduce pixel area without
shrinking technology by association of
2 or more layers staked by 3D
technologies.
125 μm
FE-TC4 CMOS 130 nm 2 layers
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3D-IC Integration
The Other Path for Scaling
Source IBM
http://www.research.ibm.com/journal/rd/526/knickerbocker.html
• Moore’s law by scaling conventional CMOS involves huge investments.
• 3D IC processes : An opportunity for another path towards continuing the scaling, involving less investments.
• Like for conventional CMOS, infrastructures are needed to promote 3D-IC integration, making it available for
prototyping at “reasonable” costs.
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Why 3-D ?
More than Moore…
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3-D methods : Through Silicon Vias
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3-D methods : Bonding Choices
1) Bonding between Die/Wafers
a) Adhesive bond
Polymer
(BCB)
b) Oxide bond (SiO2 to SiO2)
c) CuSn Eutectic
Sn
Cu
d) Cu thermocompression
SiO2
bond
Cu3Sn
(eutectic bond)
Cu
bond
Cu
e) DBI (Direct Bond Interconnect)
Metal
Oxide
bond
Metal bond
For (a) and (b), electrical connections between layers are
formed after bonding. For (c), (d), and (e), the electrical
and mechanical bonds are formed at the same time.
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Understanding the
Basic Principles of 3-D Integration
• Vias
• Via First – done at foundry, lowest cost
• Via last – after wafers are made, often done by third party vendors.
• General movement in industry toward via first approach
• Bonding options
• Mechanical bond only, electrical connections later
• Oxide to oxide bonding
• Adhesive such as BCB
• Mechanical and electrical connection formed together
• CuSn Eutectic
• CuCu Fusion
• Direct Bond Interconnect – combination of oxide bonding and metal fusion
• Thinning
• Alignment
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3-D methods : Areas of Interest to HEP
• Major Markets being pursued by Industry for 3D
integration
• Pixel arrays for imaging
• Memory
• Microprocessors
• FPGAs
• …
• 3-D Pixel arrays with high functionality and smaller form
factor for particle tracking
• 3-D bonding technology to replace bump bonds in hybrid
pixel assemblies.
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3-D integration : Via First Approach

Through silicon Via formation is done either before or
after CMOS devices (Front End of Line) processing
Form vias before transistors
IBM, NEC,
Elpida, OKI,
Tohoku, DALSA….
Tezzaron, Ziptronix
Chartered, TSMC,
RPI, IMEC……..
Form transistors before vias
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3-D integration : Via Last Approach

Via last approach occurs after wafer fabrication and
either before or after wafer bonding
Zycube, IZM,
Infineon, ASET…
Samsung, IBM,
MIT LL, RTI,
RPI….
Notes: Vias take space away from all metal layers. The assembly process
is streamlined if you don’t use a carrier wafer.
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3-D project steps
FEI4_P1 design : IBM 130nm, 8 metals
14x61 "analogue" pixel matrix
Pixel size : 50x166µm
Rad-hard and SEU tolerance
FEC4_P1 circuit : 2D Chartered 130nm, 8 metals
Submission / Test
March 08 / Summer 08
February 09 / April 09
Pixel structure : identical to FEI4_P1
(due to schedule no optimization has been
done)
Objectives : test Chartered technology (functionalities,
performances, radiation…)
FEC4_P2 circuit : 2D Chartered, 8 metals
Nov 09 / Jan 10
Based on FEC4_P1 circuit, plus :
Optimization of transistors
New latches for irradiation tests
New PadRing strategy and ground/substrate separation
FEC4_P3 : 2D Chartered, 8 metals but only 5 are used)
Smaller pixel size : 50µm x 125µm
Design of new sub-circuits and functionalities :
Analogue multiplexor and Triple redundancy memory
Calibration (pulse generator)
PLL
LVDS and ESD I/O Pads
Nov 10 / Nov 11
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3-D project steps
Submission / Test
First 3-D design (MPW organized by FNAL)
FE-TC4_P1 project
• Global Foundries 130 nm (5 metal levels)
+ Tezzaron
• One Tier for the analogue pixel part :
• 14x61 pixel matrix
• Pixel size : 50x166µm
• One Tier for the digital part
• Two versions have been designed :
• one dedicated for test, (FE-TC4-DS)
• one “FE-I4-like”.,(FE-TC4-DC)
July 09 / now
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Tezzaron-Chartered
3-D technology
Main characteristics :

2 wafers (tier 1 and tier 2) are
stacked face to face with CuCu thermo-compression bonding

Via Middle technology :
Super-Contacts (Through
Silicon contacts) are formed
before the BEOL of Chartered
technology.

Wafer is thinned to access
Super-Contacts

Chartered 130nm technology
limited to 5 metal levels

Back-side metal for bonding
(after thinning)
10µm
5µm
Wafer to wafer bonding
Bond interface
layout
Bond
M6
Interface
M5
M4
M3
M2
M1
1.2µm
12µm
2.5µm min
One tier
SuperContact
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Tezzaron-Chartered (130nm) 3D run
• 3D consortium created in 2008 (with MAPS and Hybrid
pixels communities) and 3D MPW run in 2009
sensor
Back Side
Metal
Main technology features

Large reticle (≈26 x 30 mm)

6 metal levels (M6 is the bond
interface)

Wafer to wafer, face to face bonding

TSV Vias 1.2 µm diameter with 3.8
µm recommended pitch (Via Middle
Techno)

Bond interface : copper (regular
pattern)

Upper tier thinned down to 10 µm
Tier 1
(thinned
wafer)
130 nm
M1
M2
M3
M4
M5
M6
M6
M5
M4
M3
M2
M1
Super
Contact
Bond
Interface
Tier
2

Super
Contact
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Fermilab 3-D Multi-Project Run



Fermilab has planned a dedicated 3-D multi project run using Tezzaron for
HEP during 2009
There are 2 layers of electronics fabricated in the Chartered 0.13 um
process, using only one set of masks. (Useful reticule size 15.5 x 26 mm)
The wafers are bonded face to face.
ATLAS/SLHC
Sub-part
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FE-TC4-P1 Bonn/CPPM reticles
• The reticles contains :
• the analog tier : FE-TC4-AE : Pixel matrix of 14 x 61 pixels , pixel size
50x166 µm.
Analog tier is very close to FE-C4-P1 (GF version of FE-I4-P1)
• 2 flavors of digital tier :
• FE-TC4-DS : digital tier with simple read-out (one-bit latch/ pixel),
dedicated for studying coupling between tiers
• FE-TC4-DC : digital tier with complex readout “a la FEI4” (Bonn)
• SEU3D : SEUless memory blocks
• General Test structures :
TSV + BI Daisy chain ,
transistors, etc…
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Delay due to production difficulties
First 3D wafers
with defects visible
to the naked eye

First 3D assemblies AEDC and AE-DS arrived in
September 2011 with
damages.

First tests in 2011 :
Analog tier, DC tier, DS tier
tested separately in standard
thicknesses (February 2011)

+ misalignment of bond
interface between two tiers
Analog tier
completely
removed
during thinning
First 3D working chips in
2012 !
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FE-TC4-AE analogue tier
Based on FE-C4_P1 chip + all adds for 3-D connection
Additional
switch for
read-out
Input signal from
sensor via the
Super-Contacts
Bonding pad in
Back-side metal
2 possible ways for discriminator
output read-out:
With the simple read-out part
existing yet into the pixel
With the tier 2 (via the Bond
Interface)
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3D Test results : FETC4_AE results
The analogue Tier is thinned. The output of the comparator can be read
directly in the analog tier or in the digital tier via the bond interface (in the
same time!)
Mean Noise versus dose

The 10 µm thick analog pixel behaves
as un-thinned one .
Mean Noise (e-)
60
50
FE-C4_P1
40
FE-TC4_AE_2
FE-TC4_AE_1
FE-TC4_AE_3
30
20
10
0
0,1
1
10
Dose (MRad)
Noise < 100 e- rms
100
1000
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FE-TC4-DS digital tier for test
 Analogue tier and digital tier are face to
face (sensitive part facing digital part).
ANALOGUESuperContact
M1
M2
M3
M4
M5
 FE-TC4-DS : dedicated for parasitic
coupling studies between the 2 tiers.
M6
M6


Read the discriminator output
Generate noise (digital commutations)
in front of 11 specific areas of the
analogue pixel (preamplifier, feed-back,
amplifier2, DAC…)
Test different shielding configurations.
Analogue pixel layout :
11 specific areas
Tier 1
(thinned
wafer)
Bond Interface
M5
M4
M3
M2
M1
 3 functions :

Back Side
Metal for
bonding
Tier 2
DIGITAL
SuperContact
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3D Test results : FE-TC4-AEDS chip
Analogue and Digital Simple tiers communicate !
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3D Test results : FE-TC4-AEDS chip
Shielding studies with Digital Simple
• The DS chip contains :
• a simple readout system (one-
bit latch/ pixel), a counter,
• 11 DRUM cells (noise
generators to study the
coupling between tiers) which
can be activated individually.

Each DRUM cell layout is facing one specific
area (sub-part) of the analog pixel.

To test the
intra-pixel
sensitivity.
A simple way to
generate noise and
test the influence on
the analogue Tier.
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3D Test results : FE-TC4-AEDS chip
Shielding studies with Digital Simple
• Moreover, to determine the best shielding strategy, different metal shielding
have been implemented on the DS chip :

Col 6, 7, 8 => no shield

Col 9 and 10 => shield in Metal 3

Col 11, 12, 13 => no shielded
No Shield
Col 2, 3, 4, 5 => shield in Metal 5
Shield Metal 3

No Shield
Col 0 and 1 => shield in Metal 3
and Metal 5
Shield Metal 5

Shield Metal 3 and Metal 5
Shielding configuration depending on
column numbers :
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3D Test results : FE-TC4-AEDS chip
Shielding studies with Digital Simple
• First try  Comparison No Drums / All Drums
• S curves measurements

A shielding
is necessary.

Shielding
with only M3
is not
enough
efficient.

Metal 5
appears to
be the best
solution.
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3D Test results : FE-TC4-AEDS chip
Shielding studies with Digital Simple
Studying the intra-pixel sensitivity
 Each drum is separately activated. The noise is measured on
column 7 (without any shield) (noise of 116e- with all drum OFF).
124 e-
119 e-
120 e-
400 e-
119 e-

120 e-
121 e-
200 e-
350 e-
500 e-

119 e-
The most sensitive parts are those directly connected to the input
(bump area, injection capacitor) : Not a big surprise but it confirms
that the others parts are not sensitive to the digital tier.
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3D Test results : FE-TC4-AEDC chip
• Digital Complex chip offers a complex
read-out "A la FE-I4” (with 4 pixel regions).
• The FE-TC4-AEDC is fully tested by Bonn University :



The AE tier and DC tier
communicates wells.
The analogue performances
are as expected.
The readout with TOT
information has been tested
and works as expected.
Threshold~2400e-
Noise~94e- The tuned threshold
can reach a
dispersion of 50e-.
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3D Test results : FE-TC4-AEDC chip
Study of crosstalk between pixel
• Test procedure:
• Inject charge to two pixels and read out only the pixel in between.
• Cover the matrix with a 16 Step mask.
• Configuration : Tuned threshold around ~ 2800 electrons (for the pixel in
the middle)
• The injection is increased until reach the crosstalk threshold for which the
middle pixel is affected.
Crosstalk threshold = Normal Threshold / Threshold Measured with crosstalk
mask
Inject
Read
Inject
16 Step Mask
First step
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3D Test results : FE-TC4-AEDC chip
Study of crosstalk between pixel
Read analog tier
Threshold ~31680 eCrosstalk threshold ~ 4,42%
Read digital tier
Threshold ~31810 eCrosstalk threshold ~ 4,40%
• The crosstalk threshold is the same if the readout is done via the analog
shift register or the digital shift register :
• The main crosstalk path is on the analog tier only.
• No addition of crosstalk through the digital tier is observed.
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3D Project : test structures
• From the first 3D prototype made for the ATLAS Project,
some test were done to measure TSV and Bond-Interface
performance.
• The TSV (Through Silicon Via) consists of a vertical
conductor, often referred to as “nail” or “plug”, entirely
crossing the Si substrate of the stacked dies.
Measure the TSV
daisy chain(51520
tsv), to understand
its electrical
properties.
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Patrick Pangaud - CPPM-IN2P3-CNRS
FE-TC4-P1 TSV and BI test
• We measured 19 chips, which show good tsv daisy chain
interconnection. Yielding ~84%.
• Single tsv resistance is 603  24 m . Agree with
reference value <600mohm(Tezzaron report)
• Single tsv capacitance(metal-insulator-semiconductor) in
inversion region is around 5.5fF. The calculated value is
3.6fF. In addition, we cannot measure accumulation
region capacitance because ESD diodes limit bias voltage.
• The BI test results reveal some problems. Only 1 chip
shows good interconnection. Perhaps the alignment
issues and chip surface irregularities lead to these
problems.
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Patrick Pangaud - CPPM-IN2P3-CNRS
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Single 2D FE-C4_Px test results
All prototypes showed excellent results
• Un-tuned FEC4_P1 threshold dispersion around 200 e• FEC4_P1 Noise lower than 100 e- rms
• FEC4_P1 Power consumption 27µA/pixel
Control room
Irradiation
performed at
CERN/PS facility
(24 GeV protons)
Synchronization signals
from the machine
USB
link
DE2 board
Irradiation zone
LVDS to LVTTL translator
LVDS signals
Intermediate board
Power Supply
~20 meters
Single ended
~4 meters
Outside the beam
Irradiated
Sample
In the beam
USTC, April 11, 2013
Patrick Pangaud - CPPM-IN2P3-CNRS
FEC4-P3 test results under radiation
• Third 2D chip in Chartered 130nm ( submitted in 2011) :
• Smaller pixel size (50µm x 166µm => 50µm x 125µm)
• Design of new sub-parts : analogue buffer, analogue multiplexor ….
• Radiation Hardness improvement (optimized latches, substrate separation,
guard-ring…)
• Tests under radiation at CERN/PS :
• The test was made up to 650 MRads.
• The chip resists well :
• up to 300 MRads for the Analog Part
• and up to the end of the campaign for the Digital Part.
• The chip is not broken after irradiation, and works.
• The Analog Part shows a good annealing recovering after 6 months (after
irradiation: 78% of dead pixels, after 6 months of annealing: 18% of dead
pixels).
• The new small analog pixel is now completely ready for a next 3D
integration.
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USTC, April 11, 2013
Patrick Pangaud - CPPM-IN2P3-CNRS
FEC4-P3 : Analog behavior before protons beam
At 0 Mrad
Sigma Threshold = 674 eMean Noise
= 339 eThe nominal noise is 100e-, but we ever detected some excess noise by using the USBPix card (200e-)
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USTC, April 11, 2013
Patrick Pangaud - CPPM-IN2P3-CNRS
FEC4-P3 : Analog behavior under protons beam
At 594Mrads
Sigma Threshold = ?????
Mean Noise
= ?????
Beam Fluence
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USTC, April 11, 2013
Patrick Pangaud - CPPM-IN2P3-CNRS
FEC4-P3 : Analog behavior after 203 days annealing
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USTC, April 11, 2013
Patrick Pangaud - CPPM-IN2P3-CNRS
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The FE-TC4 ATLAS full-scale chip
• FE-TC4,
FE-I3
• Very large matrix size : 336 x 160
18
160
FE-TC4
run 3-D
160
pixels
Chip size of 18.8 x 20.1 mm.
1.95 mm End Of Column width.
• Small pixel size : 125µm x 50µm
• Bump bond pads compatible with
250 µm sensor pitch (FE-I4 project)
• The FE-TC4 re-uses main blocks of FEI4 to be compatible for sensors, bump
bonding , module/stave integration,
testing tools, software, mechanics
USTC, April 11, 2013
Patrick Pangaud - CPPM-IN2P3-CNRS
Conclusions and prospects
• The Global Foundry 130nm is a good candidat with good
electrical performance under protons radiation
• Despite the (very) poor yield the Tezzaron-Chartered
technology is finally working and gives very good results.
• Substantial efforts have to be made by vendors to improve yield and
delivery schedule.
• Next step : Hybridization of a sensor in such a 3D wafer
• If the sensor hybridization on a 10µm thinned tier works, this 3D
process will be a success.
• In parallel, we work with HV-CMOS technology which can

allow to perform 3D stacking without the sensor hybridization
step (reduce of cost, time and complexity).
• We are working firstly with the Chartered HV technology (BCDlite) in
view of a Chartered-Tezzaron 3D processing (2D MPW run in May
2012). But if this technology would appear to be not suitable, we
could try to use Tezzaron process with another HV technology (as
allowed in 3D process).
Sensor layout :
Anna Macchiolo, MaxPlanck-Institut für
Physik, Munich
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USTC, April 11, 2013
Patrick Pangaud - CPPM-IN2P3-CNRS
HYBRID PIXELS SENSOR
FOR HIGH ENERGY PHYSICS
HVCMOS DEVELOPMENT
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USTC, April 11, 2013
Patrick Pangaud - CPPM-IN2P3-CNRS
SMART Diode in CMOS technology
P-substrate
Pixel electronics in the deep n-well
Ivan Peric, FEE2011, Bergamo, Italy
Deep n-well
The sensor is based on
the “deep” n-well in a
p-substrate
NMOS transistor
in its p-well
PMOS transistor
E-field
Particle
The CMOS signal processing electronics are placed inside the deep-n-well. PMOS are placed directly
inside n-well, NMOS transistors are situated in their p-wells that are embedded in the n-well as well.
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A new 3D approach for HEP community
Can we mix the smart diode and the 3D Integrated technology?
• The BCDLite include the Low
•
•
•
•
power option plus the High
Voltage option.
Bond Interface : regular
Redistribution Layer made with
last thick Cu Top Metal (1µm)
6 metal levels
Large reticle (≈26 x 30 mm)
Upper tier thinned down
Electrical field
Smart Sensor
Back Side Metal
Tier 1
(thinned wafer)
middle or first)
• GlobalFoundries 0,13µm
BCDLite technology
particle
TSV
M1
M2
M3
M4
M5
M1
M2
M3
M4
M5
M6
M6
M5
M4
M3
M2
M1
M5
M4
M3
M2
M1
Bond
Interface
Tier 2
• TSV technologies (Via last or
Global Foundries BCDLite technology 0,13µm
The HV-CMOS technology allows to perform 3D stacking without the sensor hybridization step
(reduce of cost, time and complexity). Because the Tezzaron-Chartered technology is a good radhard candidate, we will use the enhanced GlobalFoudry BCDLite technology to design a new chip in
spring 2013
USTC, April 11, 2013
Patrick Pangaud - CPPM-IN2P3-CNRS
IBM 130nm: Possible well-substrate
Nwell
Pwell
configuration
Nwell
Pwell
Deep Nwell
P- (1-2 Ohm-cm)
P- (1-2 Ohm-cm)
Deep Nwell: more flexible - sub can be biased
Conventional
Nwell
Pwell
PT3 “Burried n”
VSUB 0 to -10V
P- (1-2 Ohm-cm)
T3: True isolation. NMOS and PMOS on top of sensor. Substrate can be biased.
Proposed prototype to study such a sensor!
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USTC, April 11, 2013
Patrick Pangaud - CPPM-IN2P3-CNRS
Conclusion
• Time to R&D, between LHC phases
• Several approach for the same goal : Compactness information on less
mass material.
• Using the 3-D electronic integration approach
• Using very deep submicronic technology (65nm technology…)
• Using the HVCMOS
• …. Or all in one
• We need to create, design and test to qualify these new approaches
• New technologies (deeper submicronic, 3D ways, Smart pixels…)
• New industrial, academic partners, new alliances
• Novel architecture (analog detection and digital post-processing)
• Radiation hardness ( protons beam, Gamma ray, etc…)
• Robustness by test
• We would like to thank the fruitful collaboration with
Wei Wei, Lei Zhao, Luo Jianping, Wang Zheng
Na Wang, Jiang Xiaoshan, Fu Wei, Jian Lu
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