Transcript Latch 3 - indico in2p3

Test results of the SEU tolerant latches
M. Barberoa,*, D. Arutinova, R. Beccherleb, P. Breugnond, R. Elyc, D. Fougerond, M. Garcia-Sciveresc, D. Gnanic, T. Hempereka, M.
Karagounisa, R. Kluite, V. Kostioukhineb, A. Mekkaouic, M. Menounid, J.-D. Schippere, A. Rozanovd
aPhysikaliches
bINFN
cLawrence
Genova,via Dodecaneso 33, IT - 16146 Genova, Italy
Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 United States of America
dCPPM,
eNIKHEF,
Institut Universität Bonn,Nussallee 12, 53115 Bonn, Germany
Université de la méditerranée, CNRS/IN2P3, Marseille, France
National Institute for Subatomic Physics, Kruislaan 409, 1098 SJ Amsterdam, The Netherlands
22 sept 2008
1
Introduction

The requirement for total dose tolerance for the ATLAS pixel detector is estimated to 50 Mrad.

Because of this high level of irradiation, the B-layer performance will start degrading after 2-3 years of LHC working. So it is proposed to
upgrade the B-layer detector.

Improvements in the electronic design of the pixel front end are under study. This design development is using the 130 nm process.

For the B-Layer upgrade, the luminosity is 3 times higher than at the start of the LHC.

The radiation tolerance is estimated to 150-200 Mrad

In principle, the commercial 130 nm process used to design the front end chip is more tolerant to radiation dose than older process
generations.

However, we have to consider carefully the Single Event Effects for this highly scaled process.

The device dimensions are small

The capacitance of storage nodes is low

The supply voltage is low (1.0 V to 1.4 V)

The critical charge needed to crate an upset becomes lower than in older processes.

Some hardened by design (HBD) approaches are used to reduce the effect of single bit upsets. Particularly, D flip flop based on the
Dual Interlocked Cell (DICE) latches have redundant storage nodes and restores the original state when a SEE error is introduced in
one node.

However, As the device size shrinks, the space between critical nodes becomes more relevant for SEE because of the charge sharing
between sensitive nodes.

A 130 nm test chip has been designed in order to study the effect of layout techniques on the tolerance to single event upsets.

This work will allow to develop a library of tolerant cells to be used in the new design of the FE IC developed for the B-layer replacement.
2
PS/CERN Facility
 Irradiation tests were carried out using IRRAD3 beam line of the Proton
Synchrotron (PS) facility at CERN. The test beam provides a beam of
24 GeV protons.
 The structure of the beam is defined by the operation cycle of the PS
accelerator. It contains several spills of particles and it is distributed to the
experiments sharing the beam.
 The duration of each spill is 400 ms and the intensity can be tuned typically
from 5 1010 to 1.5 1011 protons/spill.
 A secondary emission chamber (SEC) monitors the proton beam intensity.
However, the proton fluency is most accurately measured by irradiating thin
foils of Aluminium. This method allows fluency measurement with higher
accuracy (error less than 10 %).
 For this test, the total proton fluencies provided to the chip is around
1.7 1015/cm2.
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Test set up
 The chip is controlled and read out by a DAQ system based on a PCMCIA
card from National Instruments. It is controlled via a laptop PC.
 An interface board located in the computing area converts 5V TTL signals to
LVDS signals.
 Differential buffers drive a 20 meters twisted pair cable to transmit and
receive pattern data and control signals in differential mode.
 An intermediate board located in the irradiated zone is connected with a 5
meters flat cable to the board under test.
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Test set up
Control room
Irradiation zone
Irradiated
Sample
In the beam
LVDS to LVTTL translator
TTL to LVDS translator
LVDS signals
~20 meters
PCMCIA Acquisition Card
LabWindows software
Power Supply
5
Single ended
~4 meters
Outside the beam
The test chip

2 principal latches structures are implemented in this chip :

Latch 5 and Latch 3 (The best latches from the LBL chip)

3 versions for latch 5
•
Latch A : reference design ; the same layout as in the LBL chip
•
Latch B : modified layout for node pairs separation (nMOs)
•
Latch C : interleaved structure in the triple redundancy cell


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4 versions for latch 3
•
Latch 3.0 : reference cell and uses enclosed nmos and pmos. The
same nWell for all pmos transistors
•
Latch 3.1 : enclosed transistors are replaced with linear transistors.
We are using the same W/L as in the reference latch .
•
Latch 3.2 : uses enclosed nMos and linear pMOS. Each cell in the
DICE latch has its own nWell
•
Latch 3.3 : uses linear devices with minimal dimensions to reduce the
area
Each bloc consists of near 200 triple-redundant latches
corresponding to 600 latches and the exact number of latches in
each bloc depends on the physical size of each memory cell

Shift registers are connected in parallel and use the same
clock and control signals as reset, load and read-back.

The same mask of data is applied to all blocs of latches.

Each bloc of registers have it’s own error flag, parity flag
and output data.
Dice latch description
MP1
MP3
X1
MN1
MP4

The dice latch is based on the conventional cross
coupled inverter latch structure. The 4 nodes X1X4 store data as 2 pairs of complementary values.

When the stored data is 0, X1-X2-X3-X4 = 0101
and particularly X1=0 and X2=1 . If we assume a
positive upset pulse on the node X1, the transistor
MP2 is blocked avoiding the propagation of this
perturbation to the node X2. In the same time the
transistor MN4 will propagate a negative pulse to
the node X4 to avoid perturbation on the node X3.

If 2 sensitive nodes of the cell storing the same
logic state (X1-X3) or (X2-X4) are flipped due to
the effect of a single particle impact, the immunity
is lost and the Dice latch is upset.

We will show that the probability of the occurrence
of this event could be reduced by layout
considerations and essentially if the transistor drain
areas corresponding to a sensitive node pair are
spaced in the layout.
MP2
X3
X4
MN3
MN4
X2
MN2
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Compared layout structures
In order to validate the importance of the layout for the SEU tolerance, 3 different layout were implemented for the
same latch schematic. The cells have identical schematic and use the same devices dimensions. The main
difference between the 3 cells is the separation length between the drain area of the sensitive nodes pair.
Dice latch A is the baseline design where sensitive pmos
separation is 8µm and nmos separation is only 2.4 µm. All
pmos devices are located in the same nWell and no guard
contact separation is used
Dice latch B where sensitive pmos are separated by 4 µm
and nmos by 8 µm and different nWell are used for sensitive
pmos devices
Dice latch C is an interleaved layout. It can be easily
implemented for example in triple redundancy structure.
pmos are separated by 9 µm and sensitive nmos area
separated by 5.4 µm
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Compared layout structures
Latch type
Size
area
nmos drain
separation
Latch A
16µm × 3µm
48 µm²
2.4 µm
8µm
No
No
Latch B
12µm × 4µm
48 µm²
8 µm
4 µm
Yes
Yes
Latch C
12µm × 4µm
48 µm²
9 µm
5.4 µm
Yes
Yes
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pmos drain
guard ring
separation
separated
nWell
Cross section (cm²/bit) for 1->0 SEU
Data Mask 11111….111
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
The latch A is less tolerant to “1to 0”
upsets

The latch C is 5 times tolerant than the
latch A

The “1 to 0” upsets is the consequence
of the impact on the n+ drain diffusion
(nmos).

Separating sensitive nmos devices
increases the 1 to 0 upsets tolerance.
Cross section for 0->1 SEU
Data Mask 000…0
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
The latch A is more tolerant to upsets
from “0 to 1”

The charge collected in the p+ drain
(pmos) reduces the potential in this
point and it is responsible for “1 to 0”
upsets

The separation of sensitive pmos
devices increases the 1 to 0 upsets
tolerance
Cross section for 0->1 and 1->0 SEU
Data = 0101…01
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
Globally, the layouts of latch B and C
are more efficient to SEU than the latch
A

The latch C is 2.5 times tolerant than
the latch A
Cross section compare
Cross section cm²/bit
Latch type
area
1->0
0->1
1->0 and 0->1 (*)
Latch A
48 µm²
(1.5 ± 0.1).10-15
(2.2 ± 0.3).10-16
(5.9 ± 0.5).10-16
Latch B
48 µm²
(3.4 ± 0.6).10-16
(4.2 ± 0.4).10-16
(3.6 ± 0.5).10-16
Latch C
48 µm²
(3.0 ± 0.6).10-16
(3.3 ± 0.3)10-16
(2.4 ± 0.5).10-16
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Dice Latch3

X1
Q1
X2
Sensitive node pairs :

Node Q1-Q2

Node X1- X2

The initial layout takes in account this
consideration

The latch 3 has an area 4 times larger than
the latch 5
Q2

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
More transistors

It uses enclosed transistors for all transistors
We implement a version of this latch with
linear nmos and pmos in order to reduce the
area
Latch3 : Reference Design
 Dice latch 3.0 is the reference design
 It uses enclosed nmos and pmos. The same nWell for all pmos transistors
 The area is 207 µm² (23µm × 9µm)
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Latch3 : design 3.1
 Latch 3.1 : enclosed transistors are replaced with linear transistors. We are
using the same dimensions (W/L) as in the reference design
 The area is 180 µm² (18µm × 10µm)
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Latch 3 : Design 3.2
 Latch 3.2 : uses enclosed nMos and linear pMOS. Each cell in the DICE
latch has its own nWell
 The same area as the reference design (23µm × 9µm)
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Latch 3 : Design 3.3
 Latch 3.3 : uses linear devices with minimal dimensions to reduce the area
 The area is 94 µm² (18µm × 5.2µm)
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Cross section (cm²/bit) for 1->0 SEU
Masque 11111….111
19
Cross section for 0->1 SEU
Masque 000…0
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Cross section for 0->1 and 1->0 SEU
Masque 0101…01
Masque 1010101…………1010
SEU 0->1 & 1->0
Data is taken on an other
device
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Comparative table
Latch type
number of
Transistors
size
area
Cross section cm²/bit
1->0
0->1
1->0 and 0->1
(*)
Reference
design
34
23µm × 9µm
207 µm²
2.4E-16
4.2E-16
3.0E-16
Latch 3.1
34
18µm × 10µm
180 µm²
6.5E-16
9.9E-16
9.0E-16
Latch 3.2
34
23µm × 9µm
207 µm²
1.8E-16
1.3E-15
7.6E-16
Latch 3.3
34
18µm × 5.2µm
94 µm²
6.6E-16
1.0E-15
7.0E-16
(*) : The test is made for another device (device number 3) (We are waiting for Aluminium dosimeter to have a
more precise value of the fluency)

The reference design still the best SEU tolerant design

For this structure, enclosed devices allow more tolerance against SEU


For a device with the same W/L, the drain diffusion area is lower for the Enclosed device
The layout is very important in the tolerance to SEU
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Conclusion
 The charge collection on multiple nodes is the principle cause of SEU in the
DICE latches
 The layout has a great importance in the charge sharing and so on the
tolerance of Dice latches to SEU
 We showed the influence of spatial separation of sensitive nodes on the
tolerance to SEU
 With reorganizing the layout of the studied latches, we obtain an
improvement of the SEU tolerance by a factor 2 to 3
 In the future, we will continue this work in order to measure the effect of the
triple redundancy
 The test set up will be improved in order to test latch structures at 40 MHz
and evaluate the variation of the cross section with frequency
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