Transcript Memory interfacing

Interface Design
Memory Modules
Omid Fatemi
([email protected])
University of Tehran 1
Outline
• Memory variations
• The memory cell
University of Tehran 2
Processor Timing Diagram
for any memory read machine cycle
T1
T2
T3
CLOCK
___
IOR
____
IOW
_____
MEMR
______
MEMW
Address
Bus
Data Bus
memory address
data
in
University of Tehran 3
Processor Timing Diagram
for any memory write machine cycle
T1
T2
T3
CLOCK
___
IOR
____
IOW
_____
MEMR
______
MEMW
Address
Bus
Data Bus
memory address
data out
University of Tehran 4
Memory Terms
• Capacity
– Kbit, Mbit, Gbit
• Organization
– Address lines
– Data lines
• Speed / Timing
– Access time
• Write ability
– ROM
– RAM
University of Tehran 5
ROM Variations
• Mask Rom
• PROM – OTP
• EPROM – UV_EPROM
• EEPROM
• Flash memory
University of Tehran 6
RAM Variations
• SRAM
• DRAM
• NV-RAM
– SRAM – CMOS
– Internal lithium battery
– Control circuitry to monitor Vcc
University of Tehran 7
Memories in General
• Computers have mostly RAM
• ROM (or equivalent) needed to boot
• ROM is in same class as Programmable Logic
Devices (PLDs), in which are also FPGAs
– Lots of memories in these devices
University of Tehran 8
Simple View of RAM
•
•
•
•
•
•
Of some word size n
Some capacity 2k
k bits of address line
Maybe have read line
Have a write line
Have a CS (chip select)
University of Tehran 9
1K x 16 memory
• Variety of sizes
– From 1-bit wide
• Issue is no. of pins
• Memory size specified in bytes
– This would be 2KB memory
• 10 address lines and 16 data lines
University of Tehran 10
Writing
• Sequence of steps
–
–
–
–
Setup address lines
Setup data lines
Activate write line (maybe a pos edge)
Usually latch on the next edge
University of Tehran 11
Reading
• Steps
– Setup address lines
– Activate read line
– Data available after specified amt of time
University of Tehran 12
Chip Select
• Usually a line to enable the chip
University of Tehran 13
Writing
University of Tehran 14
Reading
University of Tehran 15
Minimum Mode
A7 - A0
DEN
E
DT / R
DIR
AD7 - AD0
OE
LE
A15 - A8
OE
LE
A19/S6 - A16/
S3
GND
ALE
RD
Q7 - Q0
74LS373
D7 - D0
GND
8088
A7 - A0
A15 - A8
A19 - A16
Q7 - Q0
MEMORY
74LS373
D7 - D4
Q7 - Q4
D3 - D0
Q3 - Q0
OE
LE
D7 - D0
74LS245
D7 - D0
GND
B7 - B0
74LS373
RD
IO / M
WR
WR
University of Tehran 16
Minimum Mode
D7 - D0
D7 - D0
A19 - A0
A19 - A0
Simplified
Drawing of
8088 Minimum
Mode
MEMORY
MEMR
RD
MEMW
WR
When Memory is selected?
University of Tehran 17
Minimum Mode
220 bytes or 1MB
D7 - D0
D7 - D0
A19 - A0
A19 - A0
Simplified
Drawing of
8088 Minimum
Mode
MEMORY
MEMR
RD
MEMW
WR
CS
University of Tehran 18
What are the memory locations of a
1MB (220 bytes) Memory?
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
FFFFF
1111
1111
1111
1111
1111
Example: 34FD0
0011 0100 11111 1101 0000
University of Tehran 19
Interfacing a 1MB Memory to the 8088 Microprocessor
AX
BX
CX
DX
3F1C
0023
0000
FCA1
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
BP
SP
XXXX
XXXX
SI
DI
XXXX
XXXX
IP
XXXX
FFFFF
FFFFE
FFFFD
A19
:
A0
D7
:
D0
A19
:
A0
D7
:
D0
MEMR
RD
MEMW
WR
CS
:
:
36
25
19
:
:
20023
13
20022
20021
20020
7D
12
29
:
:
:
:
10008
10007
8A
F4
10006
10005
10004
10003
10002
10001
10000
07
88
42
39
27
98
45
:
:
00001
00000
:
:
95
23
University of Tehran 20
Instead of Interfacing 1MB, what will happen if
you interface a 512KB Memory?
University of Tehran 21
What are the memory locations of a
512KB (219 bytes) Memory?
A18 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
7FFFF
0111
1111
1111
1111
1111
University of Tehran 22
Interfacing a 512KB Memory to the 8088 Microprocessor
AX
BX
CX
DX
3F1C
0023
0000
FCA1
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
BP
SP
XXXX
XXXX
SI
XXXX
DI
XXXX
IP
XXXX
A19
A18
:
A0
D7
:
D0
What do we do with A19?
A18
:
A0
7FFFF
7FFFE
7FFFD
:
:
36
25
19
:
:
D7
:
D0
20023
20022
13
7D
MEMR
RD
20021
20020
12
29
MEMW
WR
CS
:
:
00001
00000
:
:
95
23
University of Tehran 23
What if you want to read physical address A0023?
AX
BX
CX
DX
3F1C
0023
0000
FCA1
CS
XXXX
SS
DS
ES
XXXX
A000
XXXX
BP
SP
XXXX
XXXX
SI
XXXX
DI
XXXX
IP
XXXX
A19
A18
:
A0
D7
:
D0
A18
:
A0
7FFFF
7FFFE
7FFFD
:
:
36
25
19
:
:
D7
:
D0
20023
20022
13
7D
MEMR
RD
20021
20020
12
29
MEMW
WR
CS
:
:
00001
00000
:
:
95
23
University of Tehran 24
What if you want to read physical
address A0023?
A19 to
A0
(HEX)
A0023
AAAA
1111
9876
1010
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
0010
0011
A19 is not connected to the memory so
even if the 8088 microprocessor
outputs a logic “1”, the memory
cannot “see” this.
University of Tehran 25
What if you want to read physical
address 20023?
A18 to
A0
(HEX)
20023
AAAA
1111
9876
0010
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
0010
0011
For memory it is the same as previous
one.
University of Tehran 26
Interfacing two 512KB Memory to the 8088 Microprocessor
AX
BX
CX
DX
3F1C
0023
0000
FCA1
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
BP
SP
XXXX
XXXX
SI
XXXX
DI
XXXX
IP
XXXX
A19
A18
:
A0
A18
:
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
CS
A18
:
A0
D7
:
D0
RD
WR
CS
7FFFF
7FFFE
7FFFD
:
20023
20022
36
25
19
:
13
7D
20021
20020
:
00001
00000
12
29
:
95
23
7FFFF
12
7FFFE
7FFFD
:
20023
20022
20021
20020
98
2C
:
33
45
92
A3
:
00001
00000
:
D4
97
University of Tehran 27
Interfacing two 512KB Memory to the 8088 Microprocessor
• Problem: Bus Conflict. The two memory
chips will provide data at the same time when
microprocessor performs a memory read.
• Solution: Use address line A19 as an
“arbiter”. If A19 outputs a logic “1” the upper
memory is enabled (and the lower memory is
disabled) and vice-versa.
University of Tehran 28
Interfacing two 512KB Memory to the 8088 Microprocessor
AX
3F1C
A19
BX
0023
A18
CX
0000
:
DX
FCA1
A0
A0
D7
D7
CS
XXXX
SS
XXXX
DS
2000
ES
XXXX
BP
XXXX
SP
XXXX
SI
XXXX
DI
XXXX
IP
XXXX
:
7FFFF
36
A18
7FFFE
25
:
7FFFD
19
:
:
20023
13
20022
7D
20021
12
20020
29
:
D0
D0
MEMR
RD
:
:
MEMW
WR
00001
95
CS
00000
23
7FFFF
12
A18
7FFFE
98
:
7FFFD
2C
:
:
20023
33
20022
45
20021
92
20020
A3
RD
:
:
WR
00001
D4
CS
00000
97
A0
D7
:
D0
University of Tehran 29
What are the memory locations of two
consecutive 512KB (219 bytes) Memory?
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
7FFFF
0111
1111
1111
1111
1111
80000
1000
0000
0000
0000
0000
FFFFF
1111
1111
1111
1111
1111
University of Tehran 30
Interfacing two 512KB Memory to the 8088 Microprocessor
AX
BX
CX
DX
3F1C
0023
0000
FCA1
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
BP
SP
XXXX
XXXX
SI
XXXX
DI
XXXX
IP
XXXX
A19
A18
:
A0
7FFFF
7FFFE
7FFFD
:
36
25
19
:
20023
20022
13
7D
20021
20020
:
00001
00000
12
29
:
95
23
7FFFF
12
A18
:
7FFFE
7FFFD
98
2C
A0
:
20023
20022
20021
20020
:
00001
00000
:
33
45
92
A3
:
D4
97
A18
:
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
CS
When the P outputs
an address between
80000 to 7FFFF,
00000
FFFFF,
this memory is
selected
D7
:
D0
RD
WR
CS
University of Tehran 31
Interfacing two 512KB Memory to the 8088 Microprocessor
AX
BX
3F1C
0023
A19
A18
CX
DX
0000
FCA1
:
A0
:
A0
CS
SS
XXXX
XXXX
D7
:
D7
:
DS
2000
D0
D0
ES
XXXX
MEMR
MEMW
BP
SP
XXXX
XXXX
SI
DI
IP
7FFFF
7FFFE
36
25
7FFFD
:
20023
19
:
13
20022
20021
7D
12
20020
29
RD
WR
CS
:
00001
00000
:
95
23
XXXX
XXXX
A18
7FFFF
7FFFE
12
98
XXXX
:
A0
7FFFD
:
2C
:
20023
33
RD
20022
20021
20020
:
45
92
A3
:
WR
CS
00001
00000
D4
97
A18
D7
:
D0
University of Tehran 32
Interfacing two 512KB Memory to the 8088 Microprocessor
AX
BX
3F1C
0023
A19
A18
CX
DX
0000
FCA1
CS
SS
XXXX
XXXX
DS
2000
ES
XXXX
BP
SP
XXXX
XXXX
SI
DI
IP
A19
A18
7FFFF
7FFFE
36
25
A18
:
A0
:
A0
:
A0
7FFFD
:
20023
19
:
13
D7
:
D7
:
D7
:
20022
20021
7D
12
D0
D0
D0
20020
29
MEMR
MEMW
RD
WR
RD
WR
CS
:
00001
00000
:
95
23
XXXX
XXXX
A18
7FFFF
7FFFE
12
98
XXXX
:
A0
7FFFD
:
2C
:
20023
33
RD
20022
20021
20020
:
45
92
A3
:
WR
CS
00001
00000
D4
97
D7
:
D0
University of Tehran 33
What if we remove the lower memory?
AX
BX
CX
DX
3F1C
0023
0000
FCA1
A19
A18
:
A0
A18
:
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
CS
7FFFF
7FFFE
7FFFD
:
36
25
19
:
20023
20022
13
7D
20021
20020
:
00001
00000
12
29
:
95
23
7FFFF
12
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
BP
SP
XXXX
XXXX
SI
XXXX
DI
XXXX
A18
:
7FFFE
7FFFD
98
2C
IP
XXXX
A0
:
20023
20022
20021
20020
:
00001
00000
:
33
45
92
A3
:
D4
97
D7
:
D0
RD
WR
CS
University of Tehran 34
What if we remove the lower memory?
AX
BX
CX
DX
3F1C
0023
0000
FCA1
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
BP
SP
XXXX
XXXX
SI
XXXX
DI
XXXX
IP
XXXX
A19
A18
:
A0
A18
:
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
CS
When the P outputs
an address between
80000 to 7FFFF,
00000
FFFFF, no
this memory
memory
chipisis
selected
7FFFF
7FFFE
7FFFD
:
36
25
19
:
20023
20022
13
7D
20021
20020
:
00001
00000
12
29
:
95
23
!
University of Tehran 35
Full and Partial Decoding
• Full Decoding
– When all of the “useful” address lines are connected the
memory/device to perform selection
• Partial Decoding
– When some of the “useful” address lines are connected
the memory/device to perform selection
– Using this type of decoding results into roll-over
addresses
University of Tehran 36
Full Decoding
AX
BX
CX
DX
3F1C
0023
0000
FCA1
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
BP
SP
XXXX
XXXX
SI
XXXX
DI
XXXX
IP
XXXX
A19
A18
:
A0
A18
:
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
CS
7FFFF
7FFFE
7FFFD
:
36
25
19
:
20023
20022
13
7D
20021
20020
:
00001
00000
12
29
:
95
23
University of Tehran 37
Full Decoding
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
80000
AAAA
1111
9876
1000
0000
0000
FFFFF
1111
1111
1111
1111
1111
A19 should be a logic “1” for the
memory chip to be enabled
University of Tehran 38
Full Decoding
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
7FFFF
0111
1111
1111
1111
1111
Therefore if the microprocessor
outputs an address between 00000 to
7FFFF, whose A19 is a logic “0”, the
memory chip will not be selected
University of Tehran 39
Partial Decoding
AX
BX
CX
DX
3F1C
0023
0000
FCA1
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
BP
SP
XXXX
XXXX
SI
XXXX
DI
XXXX
IP
XXXX
A19
A18
:
A0
D7
:
D0
A18
:
A0
7FFFF
7FFFE
7FFFD
:
:
36
25
19
:
:
D7
:
D0
20023
20022
13
7D
MEMR
RD
20021
20020
12
29
MEMW
WR
CS
:
:
00001
00000
:
:
95
23
University of Tehran 40
Partial Decoding
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
7FFFF
0111
1111
1111
1111
1111
80000
1000
0000
0000
0000
0000
FFFFF
1111
1111
1111
1111
1111
The value of A19 is INSIGNIFICANT to the
memory chip, therefore A19 has no bearing
Universityor
of Tehran
whether the memory chip will be enabled
not 41
Partial Decoding
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
7FFFF
0111
1111
1111
1111
1111
80000
1000
0000
0000
0000
0000
FFFFF
1111
1111
1111
1111
1111
ACTUAL ADDRESS
University of Tehran 42
Partial Decoding
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
7FFFF
0111
1111
1111
1111
1111
80000
1000
0000
0000
0000
0000
FFFFF
1111
1111
1111
1111
1111
ACTUAL ADDRESS
University of Tehran 43
Interfacing two 512K Memory Chips to
the 8088 Microprocessor
A19
A18
:
A0
A18
:
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
CS
8088
Minimum
Mode
512KB
#2
A18
:
A0
D7
:
D0
512KB
#1
RD
WR
CS
University of Tehran 44
Interfacing one 512K Memory Chips to
the 8088 Microprocessor
A19
A18
:
A0
A18
:
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
CS
8088
Minimum
Mode
512KB
University of Tehran 45
Interfacing one 512K Memory Chips to
the 8088 Microprocessor (version 2)
A19
A18
:
A0
A18
:
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
CS
8088
Minimum
Mode
512KB
University of Tehran 46
Interfacing one 512K Memory Chips to
the 8088 Microprocessor (version 3)
A19
A18
:
A0
A18
:
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
CS
8088
Minimum
Mode
512KB
University of Tehran 47
Interfacing four 256K Memory
Chips to
the 8088 Microprocessor
A17
:
A0
D7
:
D0
RD
WR
A19
A18
CS
A17
A17
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
256KB
#4
:
A0
D7
:
D0
RD
WR
256KB
#3
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#2
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#1
University
CS
of Tehran 48
Interfacing four 256K Memory
Chips to
the 8088 Microprocessor
A17
:
A0
D7
:
D0
RD
WR
A19
A18
CS
A17
A17
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
256KB
#4
:
A0
D7
:
D0
RD
WR
256KB
#3
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#2
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#1
University
CS
of Tehran 49
Interfacing four 256K Memory
Chips to
the 8088 Microprocessor
A17
:
A0
D7
:
D0
RD
WR
A19
A18
CS
A17
A17
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
256KB
#4
:
A0
D7
:
D0
RD
WR
256KB
#3
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#2
CS
A17
:
A0
D7
:
D0
RD
WR
CS
256KB
#1
University of Tehran 50
Interfacing four 256K Memory
Chips to
the 8088 Microprocessor
A17
:
A0
D7
:
D0
RD
WR
A19
A18
I1
I0
O3
A17
CS
A17
:
:
A0
D7
A0
D7
:
:
D0
MEMR
MEMW
8088
Minimum
Mode
256KB
#4
D0
RD
WR
O2
256KB
#3
CS
A17
:
A0
D7
:
D0
RD
WR
O1
256KB
#2
CS
A17
:
A0
D7
:
D0
RD
WR
O0
CS
256KB
#1
University of Tehran 51
A12
:
Interfacing several
8K Memory Chips to
the 8088 P
A19
A18
A17
A16
A15
A14
A13
A0
D7
:
D0
RD
WR
8KB
#?
CS
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
8KB
#2
CS
A12
:
A0
D7
:
D0
RD
WR
8KB
#1
CS
University of Tehran 52
A12
:
Interfacing 128
8K Memory Chips to
the 8088 P
A19
A18
A17
A16
A15
A14
A13
A0
D7
:
D0
RD
WR
8KB
#128
CS
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
8KB
#2
CS
A12
:
A0
D7
:
D0
RD
WR
8KB
#1
CS
University of Tehran 53
A12
:
Interfacing 128
8K Memory Chips to
the 8088 P
A19
A18
A17
A16
A15
A14
A13
A0
D7
:
D0
RD
WR
8KB
#128
CS
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
8KB
#2
CS
A12
:
A0
D7
:
D0
RD
WR
8KB
#1
CS
University of Tehran 54
Memory chip#__ is mapped to:
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
-----
----
----
----
----
----
-----
----
----
----
----
----
University of Tehran 55
Memory Chip
• 8K SRAM
• to be specific:
– 8Kx8 bits SRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
6264
OE
WE
CS1
CS2
University of Tehran 56
6264 Block Diagram
University of Tehran 57
6264 Function Table
University of Tehran 58
Memory Chip
• 8K EPROM
• to be specific:
– 8Kx8 bits EPROM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2764
G
P
C
VPP
University of Tehran 59
2764 Block Diagram
Chip enable
Output enable
University of Tehran 60
Operating Modes
University of Tehran 61
Programming 2764
• after each erasure for UV-EPROM):
– all bits of the M2764A are in the “1" state.
• The only way to change a “0" to a ”1" is by
ultraviolet light erasure.
• Programming mode when:
– VPP input is at 12.5V
– E and P are at TTL low.
• The data to the data output pins.
• The levels required for the address and data
inputs are TTL.
University of Tehran 62
A12
:
Interfacing 128
8K Memory Chips to
the 8088 P
A19
A18
A17
A16
A15
A14
A13
A0
D7
:
D0
RD
WR
8KB
#128
CS
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
8KB
#2
CS
A12
:
A0
D7
:
D0
RD
WR
8KB
#1
CS
University of Tehran 63
When interfacing memory chips to a
microprocessor, consider the following:
•
•
•
•
•
TAVDV – address access time
TRLDV – read access time
TDVWH – memory setup time
TWHDX – data hold time
TWLWH – write pulse width
Refer to 8088 data manual
University of Tehran 64
HM6264B Series Read Timing
Diagram
tAA, tOE
University of Tehran 65
HM6264B Series Write Timing
Diagram
tDW, tDH, tWP
University of Tehran 66
Timing Requirements for 6264 SRAM
•
•
•
•
•
TAVDV = tAA
TRLDV = tOE
TDVWH = tDW
TWHDX = tDH
TWLWH = tWP
University of Tehran 67
HM6264B Series Read TIMING
REQUIREMENTS
Symbol
Parameter
HM6264B-8L
Min
Max
HM6264B-10L
Min
Max
Units
tRC
Read cycle time
tAA
Address access time
85
100
ns
tCO1
Chip select access time (CS1’)
85
100
ns
tCO2
Chip select access time (CS2’)
85
100
ns
tOE
Output enable to output valid
45
50
ns
tLZ1
tLZ2
Chip selection to output in low-Z
(CS1)
Chip selection to output in low-Z
(CS2)
tOLZ
Output enable to output in low-Z
tHZ1
tHZ2
Chip deselection in to output in
high-Z (CS1’)
Chip deselection in to output in
high-Z (CS2’)
tOHZ
tOH
85
100
ns
10
10
ns
10
10
ns
5
5
ns
0
30
0
35
ns
0
30
0
35
ns
Output disable to output in high-Z
0
30
0
35
ns
Output hold from address change
10
10
ns
University of Tehran 68
HM6264B Series Write TIMING
REQUIREMENTS
Symbol
Parameter
HM6264B-8L
Min
Max
HM6264B-10L
Min
Max
Units
tWC
Write cycle time
85
100
ns
tCW
Chip selection to end of write
75
80
ns
tAS
Address setup time
0
0
ns
tAW
Address valid to end of write
75
80
ns
tWP
Write pulse width
55
60
ns
tWR
Write recovery time
0
0
tWHZ
WE’ to output in high-Z
0
tDW
Data to write time overlap
40
40
ns
tDH
Data hold from write time
0
0
ns
tOW
Output active from end of write
5
5
ns
tOHZ
Output disable to output in high-Z
0
30
30
0
0
35
35
ns
ns
University of Tehran 69
Comparing Timing Requirements of
8088 (using 4 Mhz clock) and HM6264B-8L
8088 using 4MHz clk
610 ns
555 ns
400 ns
88 ns
440 ns
Timing Req.
TAVDV or tAA
TRLDV or tOE
TDVWH or tDW
TWHDX or tDH
TWLWH or tWP
HM6264B-8L
85 ns
45 ns
40 ns
0 ns
55 ns
University of Tehran 70
Timing Requirements for HM6264B-8L
•
•
•
•
•
TAVDV = tAA = 85 ns
TRLDV = tOE = 45 ns
TDVWH = tDW = 40 ns
TWHDX = tDH = 0 ns
TWLWH = tWP = 55 ns
University of Tehran 71
Can we interface a 2764 to the 8088
chip which uses a 4MHz clock?
University of Tehran 72
M2764A Read Mode AC
Characteristics
Symbol
Alt
tAVQV
tACC
tELQV
tCE
tGLQV
tOE
tEHQZ
tDF
tGHQZ
tDF
tAXQX
tDH
Parameter
Address Valid to Output
Valid
Chip Enable Low to
Output Valid
Output Enable Low to
Output Valid
Chip Enable High to
Ourput Hi-Z
Output Enable High to
Output Hi-Z
Address Transition to
Output Transition
-3
Min
-4
Max
Min
Max
Units
180
200
ns
180
200
ns
65
75
ns
0
55
0
55
ns
0
55
0
55
ns
0
0
ns
University of Tehran 73
M2764A Read Mode Timing
Diagram
University of Tehran 74
Timing Requirements for 2764 EPROM
•
•
•
•
•
TAVDV = tAVQV
TRLDV = tGLQV
TDVWH = N/A
TWHDX = N/A
TWLWH = N/A
University of Tehran 75
Timing Requirements for 2764 EPROM
•
•
•
•
•
TAVDV = tAVQV = ?
TRLDV = tGLQV = ?
TDVWH = N/A
TWHDX = N/A
TWLWH = N/A
University of Tehran 76
M2764A Read Mode AC
Characteristics
Symbol
Alt
tAVQV
tACC
tELQV
tCE
tGLQV
tOE
tEHQZ
tDF
tGHQZ
tDF
tAXQX
tDH
Parameter
Address Valid to Output
Valid
Chip Enable Low to
Output Valid
Output Enable Low to
Output Valid
Chip Enable High to
Ourput Hi-Z
Output Enable High to
Output Hi-Z
Address Transition to
Output Transition
-3
Min
-4
Max
Min
Max
Units
180
200
ns
180
200
ns
65
75
ns
0
55
0
55
ns
0
55
0
55
ns
0
0
ns
University of Tehran 77
Timing Requirements for M2764A-3
•
•
•
•
•
TAVDV = tAVQV = 180 ns
TRLDV = tGLQV = 65 ns
TDVWH = N/A
TWHDX = N/A
TWLWH = N/A
University of Tehran 78
Comparing Timing Requirements of
8088 (using 4 Mhz clock) and M2764A-3
8088 using 4MHz clk
610 ns
555 ns
Timing Req.
TAVDV or tAVQV
TRLDV or tGLQV
HM6264B-8L
180 ns
65 ns
University of Tehran 79
What if we need to interface a
“slow” memory to the 8088?
University of Tehran 80
Comparing Timing Requirements of
8088 (using 4 Mhz clock) and a certain “slow” memory chip
8088 using 4MHz clk
610 ns
555 ns
400 ns
88 ns
440 ns
Timing Req.
TAVDV or tAA
TRLDV or tOE
TDVWH or tDW
TWHDX or tDH
TWLWH or tWP
memory chip
85 ns
45 ns
40 ns
0 ns
500 ns
University of Tehran 81
A12
:
A19
A18
A17
A16
A15
A14
A13
READY
A0
Q7
:
M2764A-3
Q0
G
C
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
SLOW
MEMORY
CS
A12
:
A0
D7
:
HM6264B-8L
D0
OE
WE
CS1
CS2
5V
University of Tehran 82
T1
T2
T3
T4
CLOCK
__
DT/R
ALE
D7 - D0
from 74LS245 to m e m ory
AD7 - AD0
A7 - A0
A7 - A0
A15 - A8
A19/S6 - A16/S3
A19 - A0
from 74LS373 to m e m ory
D7 - D0 (to memory)
D7 - D0 (to 74LS245)
A15 - A8
A19 - A16
S6 - S3
A19 - A0 from 74LS373
__
IO/M
_____
WR
______
DEN
TWLWH
2TCLCL
Recall:Write Pulse Width /
Write-Time (TWLWH)
University of Tehran 83
T1
T2
TW
T3
T4
CLOCK
READY
__
DT/R
ALE
D7 - D0
from 74LS245 to m em ory
AD7 - AD0
A7 - A0
D7 - D0 (to memory)
A7 - A0
D7 - D0 (to 74LS245)
A15 - A8
A15 - A8
A19/S6 - A16/S3
A19 - A16
A19 - A0
from 74LS373 to m em ory
S6 - S3
A19 - A0 from 74LS373
__
IO/M
_____
WR
______
DEN
TWLWH
Write Pulse Width / Write-Time (TWLWH)
w/ 1 wait state
University of Tehran 84
Comparing Timing Requirements of
8088 (using 4 Mhz clock) and a certain memory chip
8088 using 4MHz clk
610 ns
555 ns
400 ns + 250 ns
88 ns + 250 ns
440 ns + 250 ns
Timing Req.
TAVDV or tAA
TRLDV or tOE
TDVWH or tDW
TWHDX or tDH
TWLWH or tWP
memory chip
85 ns
45 ns
40 ns
0 ns
500 ns
caused by 1 wait state during a memory
write on the “slow” memory chip
University of Tehran 85
How do we produce a wait
state?
• By turning the READY input of the 8088
microprocessor to LOW
University of Tehran 86
A12
:
A19
A18
A17
A16
A15
A14
A13
READY
A0
Q7
:
M2764A-3
Q0
G
C
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
SLOW
MEMORY
CS
A12
:
A0
D7
:
HM6264B-8L
D0
OE
WE
CS1
CS2
5V
University of Tehran 87
T1
T2
TW
T3
T4
CLOCK
READY
__
DT/R
ALE
D7 - D0
from 74LS245 to memory
AD7 - AD0
A7 - A0
D7 - D0 (to memory)
A7 - A0
D7 - D0 (to 74LS245)
A15 - A8
A19/S6 - A16/S3
A19 - A0
from 74LS373 to memory
A15 - A8
A19 - A16
S6 - S3
A19 - A0 from 74LS373
__
IO/M
_____
WR
______
DEN
30 ns
(min)
119 ns
(min)
Requirements for the READY input of the 8088
University of Tehran 88
T1
T2
TW
T3
T4
CLOCK
RDY1
READY
35 ns
(min)
Requirements for the RDY of the 8284
University of Tehran 89
Memory - Global Organisation
Address
decoder
Memory
2 n x m Bit
n - Bit
Address
m - Bit Data
University of Tehran 90
Static vs Dynamic RAM
• SRAM vs DRAM
• DRAM stores charge in capacitor
– Disappears over short period of time
– Must be refreshed
• SRAM easier to use
– Faster
– More expensive per bit
– Smaller sizes
University of Tehran 91
Structure of SRAM
• Control logic
• One memory cell per bit
– Cell consists of one or more transistors
– Not really a latch made of logic
• Logic equivalent
University of Tehran 92
16 X 1 RAM
What is this?
University of Tehran 96
Tri-State
• Have three states: H, L, and Hi-Z
– High impedance
– Behaves line no output connection if in Hi-Z state
– Allows connecting multiple outputs
University of Tehran 97
Multiplexed with Hi-Z
• Normal behavior is blue area
Smoke
University of Tehran 98
Row/Column
• If RAM gets large, there is a large decoder
• Also run into chip layout issues
• Larger memories usually “2D” in a matrix
layout
University of Tehran 99
16 X 1 as 4 X 4 Array
• Two decoders
– Row
– Column
• Address just
broken up
• Not visible from
outside
University of Tehran 100
Change to 8 X 2 RAM
• Minor change in
logic
• Also pinouts
• Address 011 (for
example)
University of Tehran 101
Memory - Internal Organisation
n/ 2
2
Lines
(Word Lines)
m Level
Memory cell
n / 2 - Bit
Row Address
Quadratic
Row
Address
Decoder
W/E
CS
OE PGM
Memory Matrix
n - Bit Address
Control Logic
2
Column Address Decoder
Column selection
n/ 2
Lines (Bit Lines)
m - Bit Data
n / 2 - Bit Column Address
University of Tehran 102
SRAM Performance
• Current ones have cycle times in low
nanoseconds (say 2.5ns)
• Used as cache (typically offchip secondary
cache)
• Sizes up to 8Mbit or so for fast chips
• SRAMs:
– Asynchronous
– Synchronous
University of Tehran 104
Micron SRAMs
• SyncBurst
• ZBT
• QDR
• DDR (common IO)
• DDR (separate IO)
• Synchronous
• Control inputs are captured at clock edges
University of Tehran 105
SRAM Categories
• SYNCBURST
–
–
–
–
–
Internal 2-bit burst counter
Appropriate for cache line size of four
Two bus master support (CPU and cache controller)
ADV# controls number of words
Not suited for more frequent bus turnaround applications
• ZBT (Zero Bus Turnaround)
– Internal 2-bit burst counter
– FLOW-Through ZBT
» One clock cycle delay
» Less data latency and less frequency
– Pipelined ZBT
» While data is delivered the memory array is free for the next
data access
» Higher frequency
University of Tehran 106
Pentium Cache System
University of Tehran 107
SRAM QDR
• QDR (Quad Data Rate)
– Low latency, higher frequency (network applications)
– Less ASIC pin count
– Separate read and write busses simultaneous read and
write
– Clock pair (K,K#)
University of Tehran 108
SRAM DDR
• DDR (common IO)
– In cases like 16 read then 16 write QDR is half wasted
– Common IO busses for input and output
• DDR (separate IO)
– Hybrid of DDR and QDR
University of Tehran 109