Transcript 1.0 um CMOS Process Integration

CMOS Process Integration
Silicon Type
i.
ii.
iii.
Silicon planes of (100) crystal orientation
produced the lowest number of charges and
states. This the main reason that MOS devices
are made on (100) silicon wafers.
Silicon planes (100) has less atom concentration
at the surface and also has better surface quality.
Interface characteristic between SiO2 and Si is
better with less/lower atom density. Good
characteristic for CMOS device.(111) has a higher
growth rate as a result is difficult to control.
Epi-Layer
i. P epi-layer is used to reduce a
latch-up problem.The thickness of
the epi-layer is 5.5 um.P substrate
has a better device performance.
Pad Oxide
i. The function of the pad oxide is to
prevent silicon surface from damage
during nitride deposition.
ii. Oxide under nitride is for LOCOS
process.
Field Oxide
i. 1st field oxide is a mask for
implantation. i.e. self –align
implantation.
ii. 2nd field oxide is a real field oxide.It
is to isolate 2 adjecent transistor.
Well Formation
i. N well doping concentration is much
higher than P well doping
concentration. Reason is to reduce
short channel effect.
Oxidation
i. If the PN junction are already
present, their location and
properties may change because of
diffusion of donor and/or acceptor
dopants during the oxidation
treatment.
LOCOS
i.
ii.
LOCOS for defining of the device areas and silicon
gates for definition of the gate,source and drain
regions within those region.In general LOCOS is used
for well formation and field oxide.
Bird bead; Advantage are plannarization and smooth
topography.Disadvantage is linewidth reduction.Width
of active area on mask is 2 um but due to bird bead
width of active area on Si is < 2 um.How to reduce bird
bead is by reducing the pad oxide thickness but it
increase stress problem to the Si.Defect in Si due to
stress lead to leakage current problem.
iii.
KOOI or white ribben effect in LOCOS due to Nitride
rich SiO2.This residue need to be removed by making
a sacrificial oxide (pad oxide).
Nitride
i.
ii.
iii.
iv.
LPCVD nitride has a better quality than PECVD nitride.
Mask oxidation.
Diffusion barrier for O2 to penetrate underneath layer and
also for any dopants.Nitride pattern not only as an oxidation
mask but also as a mask for donor and acceptor diffusion.
There are 2 nitride deposition process step in 1.0 um
CMOS i.e.
1st Nitride – for n-well formation
2nd Nitride – field oxide formation and N field implant
v.
vi.
vii.
2nd Nitride layer should be little bit thicker than the first
nitride.This nitride is used to prevent active layer during
implantation.
PECVD nitride is applied after the aluminium
interconnection pattern have been made.Si3N4 protects
aluminium lines from corrosion.
Hot phosphoric acid as well as plasma may etch into silicon
substrate after the nitride is removed.The attack of silicon
can be prevented by applying a thin SiO2 film under the
nitride (pad oxide).It also function to reduce the effects of
mechanical stress occuring in LOCOS processes.
Diffusion
i.
Diffusion factor are;
-
Size of the atoms
Temperature
Dopands concentration
(P has higher concentration
level than B).Another drive
force.It will force to diffuse
faster and finally the depth of
P & B is equal.
Field Implant
i.
ii.
iii.
Impurities segregation at a silicon surface due to thermal
oxidation.As examples,concentration of phosphorus (Ph) and
boron are depleted.Phosphorus tends to pile up at the silicon
surface; boron on the other hand,tend to be absorbed in the
growing oxide,thus causing depletion in the silicon near the
surface.
During oxidation or thermal or furnace process,boron will
diffuse up to the SiO2 layer but P is not.That why boron
concentration become less and need additional boron to form
a parasitic transistor at high threshold voltage while P is not
necessary because P can not penetrate SiO2 layer.
N field implant is introduce into P well substrate.N field implant
is perform before grow the field oxide.
Gate Oxide
i.
ii.
iii.
iv.
IMS measure on process wafer.Reason for better control.In
production,measurement is performed on dummy
wafer.Another reason is better to proceed immediately to
polysilicon deposition after gate oxide growth.To avoid
moisture for example to attack poly.The shorter the time
different the better it is.
The tolerence thickness of gate oxide is very small i.e. +/- 1
nm.Thickness variation will affect the electrical
characteristic of transistor.
Gate oxide thickness for 1.0 um is nm.
After poly etching process the thickness of gate oxide
reduce to 15 nm due to HF dip to remove polymer at poly
side wall.
Polysilicon
i.
ii.
iii.
The advantage of polysilicon over aluminium for gate
electrode is that the poly-Si electrodes can withstand
higher temperature and may therefore be patterned
before the dopants are diffused into the source and
drain regions.
Poly define the channel length and can perform self
align S/D implant.
4 major components that affect the sheet resistance of
polysilicon i.e. time,dopant concentration, temperature
and poly thickness.The most effective component is
temperature.Poly layer resistivity decrease when the
thickness decrease.
iv.
Poly thickness measurement is not important and not
critical.The most important is poly sheet resistance.It
indirectly tell the thickness of poly.(Poly sheet
resistance decrease when poly thickness
decrease).Poly sheet resistance decrease after
POCL3 dope.POC13 concentration in poly is influence
by temperature and dopand concentration.
Square Sheet Resistance
i.
It used to measure sheet resistance on
poly,metal and dopant concentration
using 4 point probe.
Poly Oxide
i.
ii.
Is required to protect polysilicon during S/D implantation.More
critical for PMOS.This is because in NMOS the type of dopant
used for S/D implant and the poly dope is the same type i.e. n
type (poly –P, S/D-As).But for PMOS implant,the dopant used
for S/D is boron (p-type) while dopant for poly is P(n-type).It
will change the behaviour of poly.That another reason why
need thickner oxide on poly.
There are 2 process step for poly oxide i.e.
1st poly oxide – to protect poly during LDD implant
- to avoid channeling effect
- to form shallow junction
2nd poly oxide – to protect poly during S/D implant
- to protect poly from diffusion of B and P from
BPSG layer.
LDD Implant
i.
To reduce high field effect & control
transistor stability.
ii. 0 degree implant – symmetry implant & 7
degree implant is to avoid channeling
effect.
Spacer
i.
Function as a mask for NMOS S/D
implantation.
ii. Nitride spacer is another alternative to
oxide spacer.It can reduce a charge trap
problem.
iii. Spacer oxide can be measured on
dummy and also on process wafer.
Threshold Voltage
i.
ii.
iii.
iv.
In addition to oxide thickness and substrate doping level, Vt
is also determined by work function different between the
gate electrode material and silicon substrate.Surface states
and oxide charges may play a role too,but these can be
made negligible by using (100) starting material.
Vth of MOS transistors can be increased by making the
oxide layer thicker.
Dopant concentration in both N/P Well increase, Vth
increase.
Vth implant in N – Well Vth decrease.
Vth implant in P – Well Vth increase.
NMOS & PMOS
i.
ii.
Sequence of the process to form NMOS and PMOS;
NMOS Gate oxide,Poly dep & etch,Poly oxide,
LDD implant, Spacer,S/D implant
PMOS Gate oxide,Poly dep & etch,Poly oxide,
No LDD, Spacer,S/D implant
The major different is for PMOS the S/D region (boron)
is not directly under poly due to spacer
formation.Spacer is formed at both NMOS and
PMOS.To form a channel,S/D region should be formed
direct under poly.This condition is necessary because
boron will diffuse faster than P and As.
That is the function of spacer at PMOS.The boron will diffuse and
located under the poly after the following step is performed i.e.
reflow.
Reflow process has 3 function
plannarization
activation
Driving force for
boron in PMOS to
diffuse and
located under
poly.
iii. It possible to skip process step #155 (annealling).Annealing for
NMOS can be performed together with 2nd annealing (reflow).As
diffuse faster than P.
BPSG
i.
ii.
iii.
iv.
BPSG is required for plannarization thru reflow.Plannarization
is extrimely important for metal etching.If a BPSG layer is not
planner metal layer will face a step coverage problem.Metal
thickness at the side of poly will be 2x higher than other
places.As a result,after metal etching process,the metal
residue will left behind.Step coverage is an another issue but
the major problem is metal residue after etching.
BPSG (650nm) is deposited after a thin layer of USG (100nm)
is deposited.It is to avoid dopant to diffuse into the substrate.
Better to perform reflow immediately after BPSG deposition.
B and P is needed for reflow characteristic.
Metal 1 (AISiCu(0.5%))
i.
ii.
iii.
iv.
Good to have higher concentration of Cu to overcome
electromigration problem but bad fot etching.It will
ause a residue problem.
Si in AISi-.- is not necessary only because of historical
reason.It Ok if only use AICu.With barrier Si in AISi is
not necessary but without barrier Si is important.
Ti is adhere good to Si and TiN.
Aluminium spiking can cause short in shallow
junctions.There are 3 ways to avoid spiking problem;
v.
vi.
- Al containing 1% Si is often used to eliminate spiking.
- Barrier layer (Ti/TiN) also can avoid spiking.
- Deep junction can avoid short.
Ti – adhesion layer, improve cantact,barrier layer.
AISi(2%)Cu(4%). With 4% Cu, device life time will be
higher compare to 1% Cu.Cu need to avoid
electromigration.
vii.
viii.
Smaller metal line, lead to higher current density (A/cm2) and
higher electromigration cause metal line open.This is because
mobile e transport the Al atom to other place.When the AISi line is
sandwitch with barrier layer,the open fenomena can occur but the
current still can flow thru barrier layer.This is the advantage of
barrier layer to the electromigration problem.
After metalization process, 2 major things are change namely
cleaning technique and process temperature.Cleaning should be
change from D to C (without piranha – solvent base).With solvent
base processor,cleaning C is not necessary.At this level the
process temperature should be lower that 500 C.The optimum
temperature is 450 C.
ix.
x.
Metal thickness is measured by using step height.But it didn’t tell
the actual thickness of metal.This is because of over etch of
oxide during metal etching.Means step height measure the
thickness of metal and oxide over etch.Again metal thickness is
not important,sheet resistance of the metal is more important.
Annealing after Ti/TiN deposition process-To reduce resistivity
-To staff the properties
of TiN.
Metal 2 (AiSiCu/TiN) Deposition
i.
ii.
The processing step is sputter etch (to remove AI203),
1000nm AISi dep and Ti 40nm (ARC) dep.
Hillock problem can occur – vertically,on top of metal line
laterally,at the edge of metal
line.
In 1.0 um process,hillock cannot occur on top of metal
because of Ti layer on top and only occur at the side of
metal line.If TiN is used for ARC layer probably lateral
hillock can occur but if ARC layer is only Ti lateral hillock is
not occur.IMS case.Ti layer is less heavier compare to TiN.
iii.
iv.
Metal 2 over etch time is little bit longer than metal 1.
After metal 2 etching there is strange polymer form at
side wall.This polymer should be remove.In MIMOS
case plasma resist stripping will be performed in P5000
and continue with solvent base removal to remove
polymer and remaining resist.
Thickness decrease,resistivity increase and conductivity
decrease.Metal 2 has higher conductivity than metal 1.
Plannarization Process
i.
ii.
iii.
Purpose of plannarization is to smooth the surface.
Example : ILD (BPSG layer) and IMD (dep-etch layer).
Why need plannarization?
- Etching process reason.To avoid long over etch due to
thickness variation especially at the edges of the
structure.Also stringer problem.
- Lithography process reason.due to high topography the
thickness of the resist and underlying layer will be more
than DOF.Finally it will affect the CD control.
Process step of ILD layer – USG dep 1 (700 nm), Sputter
Etch, USG dep 2 (2500 nm), Etchback.This kind of
plannarization process is commaly call Global
Plannarization.
iv.
v.
vi.
Others plannarization method namely CMP (chemical
mechanical polishing) and SOG. SOG not as stable as
SiO2. Problem of SOG is outgassing during etching
and can cause Via poisonning.
Etching process step of USG to form a Via is AISiCu
etching and TiN etching.
The major different between ILD plannarization and
IMD plannarization is the influence of temperature.
IMD is a low temperature process while ILD is high
temperature process. IMD has metal. ILD before
metal. Why BPSG for ILD? It is because BPSG has
better reflow characteristic (B&G).
BOE Etching
i. For oxide ecthing.
ii. BOE after BPSG is to remove oxide that
form at the back side of the water after
reflow process.
Lithography Process
i.
ii.
iii.
Resist become hard after DUV, etching and
implantation process.Acetone cannot remove this hard
resist.Asher is required.
Resist thickness cannot be measured on transparent
layer (SiO2, Nitride, poly).If the underlying
(transparent) layer is comparatively thin, it possible to
meassure.
N11 = Z11 – open P well region.
Z11 – N – field implant and NMOS Vth adjust
N11 – LDD implant & NMOS S/D implant.
PSG Deposition (Passivation)
i.
With 2% P gathering or diffusion rate of
sodium and potassium are minimize.
ii. Nitride passivation has better protection
circuit feature than oxide. But for 1 um,
oxide passivation is good enough for
standard application. IMS used nitride
passivation for high power device and
sensor.
H2 Anneal
i.
The purpose of H2 anneal are ;
- improve ohmic contact
- improve daggling