Transcript Capstone 2012-2013 PolarCube CDR

Capstone 2012-2013
PolarCube CDR
December 11, 2012
2
Microwave Sounding
Frequency vs. Zenith Opacity
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PolarCube will use 118.75 GHz, a
resonance frequency of diatomic
oxygen, as a center frequency
Courtesy of Dr. Gasiewski
•
PolarCube Channels have a specified
weights corresponding to altitude
Courtesy of Lavanya Periasamy, University of Colorado
3
ALL-STAR Satellite Bus
4
Block Diagram of the Bus and
Payload
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Block Diagram
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RF Block Diagram
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RF Block Diagram
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RF Block Diagram
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IF Block Diagram
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Function Before Digital
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Function of Radio Frequency (Channel 5)
T=(F-1)T0
P=kTB
Attenuator(
switch)
Isolator
Mixer(Mixer & local Oscillator)
Low noise
amplifier(LNA)
Noise Figure(dB)
0.6
0.6
5.1
1.18
7.08
Noise
Temperature(K)
42.96
42.96
527.3
90.53
1121.59
NP(dBm)
L/G(dB)
Output of
RF
-57.38
L=0.6
L=0.6
L=2.8
G=28.7
Function of Intermediate Frequency
Noise
Figure(dB)
Diplexer
Amplifier(
3)
Attenuator(
2)
1
2.40
3.06
2.5
1.2
213.96
296.67
225.70
92.29
2.81
-3.30
-11.82
-13.02
G=20.4
L=3.06
L=2.5
L=1.2
Noise
Temperature(K)
Noise
Power(dBm)
Loss/Gain(dB)
L=1
Power Splitter
Filter
Tunnel Diode
-13.02
IF System
14
Diplexer Motivation
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Multi-channel radiometer needs
channel separation in order to
measure different frequency
band
The diplexer splits the signal
from RF Receiver into two
bands
15
Diplexer Design
The design problem is much more difficult than
it might at first seem. If ordinary low-pass
filter and high-pass filter are simply
connected together, interaction effects will
usually disrupt the performance of the
system, unless the filters and their
interconnections are very carefully designed.
To prevent this disruption, the complementary
structure is very correct technique to design a
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diplexer.
Complementary Structure
We construct diplexer with
LPF and HPF to have
complementary input
admittances and connects
them in parallel. The
complementary input
admittances means that the
sum of the input admittance
of the low pass and high
pass filter are real and
constant for all frequencies.
Hypothetical input
admittances of LPF and
HPF is shown in the figure.17
Schematic of Diplexer
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Idea Value VS. Real Value
None of
component
manufacturer
produces ideal
component
value. They
produce limited
discrete value
and various size
19
ADS Test Bench
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Performances
Ideal Value
Real Value
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Sum of Imaginary Part of
Impedance
Ideal Value
Real Value
-0.1
1.3
1.3
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Diplexer PCB Layout
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IF System
• Two IF boards, in two carriers
• The diplexer connected to the
IF higher frequency circuit
board(right hand box)
Courtesy of Space Grant Consortium, University of Colorado
24
*
25
*
IF System Risk Management
•
•
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Physical constraint (shrink down the size of
PCB boards)
Pre-amp signal oscillation problem
(old design)
Fit in the video-amp board
26
Pre-Amp board and Oscillations
3-Amp Board
Spectrum Analyzer Plot
Have the peak in plot with 0 RF input signal
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2-Amp & 3-Amp board
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Video-Amp Layout
Video Amp Board
Signal Video Amp
IF Board
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IF Block Diagram
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Digital Board Block Diagram
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Digital Hardware
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Provides capability for communication over
SPI with the ALL-STAR bus, for transmitting
data and accepting/sending commands
Flash memory as needed for data queuing
and workspace before transfer to ALL-STAR
Provides capability to sample the analog
output of the IF system
Includes voltage regulators to provide
necessary voltages to digital components
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Software
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Responsible for initiating and collecting
samples from the output of the ADCs,
communicating with ALL-STAR, and
switching necessary components off during
low-power availability
ALL-STAR server
Must compress data for transmission during
downlink window
Manage power for components via control
input to voltage regulators
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SLOC
34
Digital Risk Management
•
Utilizing established Atmel SPI APIs to
interact with digital hardware for quicker
development
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SVN SCM for distributed development and
change tracking
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Incremental hardware design strategy
Familiarization with software while hardware
is being developed
35
Xplained Board
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Risk mitigation strategy
Has allowed for familiarization with Atmelprovided SPI and GPIO APIs while test
hardware is still being designed and ordered
Have used to verify the needed steps in
getting one of the SPI interfaces to interact
with Aardvark protocol analyzer
Familiarized with GPIO API for potential
future use during power management
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Modular Test Board Designs for
Memory and ADCs
Memory Test Board
ADC Test Board
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Digital Board Physical Constraints
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Power Constraints
Power Supply Lines to Active Components in the Payload
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Power Constraints and Preliminary
Power Budget
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Payload Power Supply: Nominally 4 - 5 W
Oscillator: 4.875W
Full Power Draw All Components: ~11W
40
Power Modes FSM
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Data Budget
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Monetary Budget
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Timeline
44
Acknowledgements
Special Thanks to:
Dr. Gasiewski
Brian Sanders and the team at Space Grant
Lavanya Periasamy
Kyuil Hwang
45
Questions?