Transcript Case iac 25

FTFC2003, Paris, May 15 2003
Trends in Low-Voltage RAM Circuits
Kiyoo Itoh, Hitachi Ltd.
Outline
1. Introduction
2. Trends in RAMs
3. Challenges to Low-Voltage(LV) RAMs
4. Subthreshold-Current Reduction
RAM Cells / Peripheral Circuits
5. Perspectives
6. Conclusion
2
Trends in RAM Developments (R&D)
16 G
10,000
Full CMOS
1G
72
64 M
32
18
DRAM
4M
256 K
SRAM
16 K
Memory Cell Area (mm2)
Memory Capacity/chip (bits)
ISSCC/VLSI
Stand-alone RAMs
Poly-Si load
1,000
100
ISSCC/VLSI
Stand-alone RAMs
Planar
capacitor
SRAM
TFT
load
10
1
Full
CMOS
3-D capacitor
DRAM
0.1
1K
1970
1980
Year
K. Itoh, Hitachi
1990
2000
1970
1990
1980
2000
Year
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001
3
Challenges to LV RAMs
RAM Cells
DRAM
Leakage Reductions
Tunnel Current
Subthreshold Current
Shorter tREFmax (DRAM)
Larger retention current (SRAM)
VDD
DL
Reduced Qs (= Cs VDD / 2) SER
Ever-increasing VT / VT
Peripheral Circuits
Leakage Reductions
Compensation for speed variations
due to design parameter variations
 /  VT / (VDD –VT0),
VT =VT0 (mean) + VT,
 Stringent control of VT
Compensations for VT with
internal control of VDD / VSUB
VDD
Qs = Cs VDD/2
WL
Stable Operations
SRAM
"1"
Cs
Qs = Cs VDD/2
Cs
WL
DL
"0"
0
DL
0
(VDD)
VDD
(0)
stand-alone RAM / e-RAM
periph.
RAM cell
array
DRAM
SRAM
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001
K. Itoh, Hitachi
4
Soft Error Rate(SER) of RAM Cells
C at SRAM cell node
ECC with small speed/area penalties
Purification of LSI materials
Shielding of cells with polyimide
Well structure (p+barriers, triple well)
Level keeper.
E. Ibe, The Svedberg Laboratory Workshop on Applied Physics,
Uppsala, May3, 2001
K. Itoh, Hitachi
Cosmic-ray neutron
Alpha-ray
Nuclear reaction
SER Cross Section/chip(cm2)
-particle induced SEs
Cosmic-ray neutron-induced SEs
Neutrons generate ten times as many
charges as -particles.
Impacts of Device Scaling on SEs:
For DRAM; decrease due to a large Cs
and spatial scaling (i.e.less collection).
For SRAM; increase due to decrease
in Cs despite spatial scaling.
Solutions:
Increase in Qs (= Cs·VDD/2)
1E-5
1E-6
DRAM
1E-7
1E-8
1E-9
SRAM
1E-10
0.1
1
10
100
Memory Capacity (Mbit)
1000
5
Challenges to LV RAMs
RAM Cells
DRAM
Leakage Reductions
Tunnel Current
Subthreshold Current
Shorter tREFmax (DRAM)
Larger retention current (SRAM)
VDD
DL
Reduced Qs (= Cs VDD / 2) SER
Ever-increasing VT / VT
Peripheral Circuits
Leakage Reductions
Compensation for speed variations
due to design parameter variations
 /  VT / (VDD –VT0),
VT =VT0 (mean) + VT,
 Stringent control of VT
Compensations for VT with
internal control of VDD / VSUB
VDD
Qs = Cs VDD/2
WL
Stable Operations
SRAM
"1"
Cs
Qs = Cs VDD/2
Cs
WL
DL
"0"
0
DL
0
(VDD)
VDD
(0)
stand-alone RAM / e-RAM
periph.
RAM cell
array
DRAM
SRAM
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001
K. Itoh, Hitachi
6
Gate Tunnel Current
ISSCC, Symp.VLSI Circuits
Leakage increase x 10 / 2 Å (SiO2)
Few circuitry solutions
50
40
30
20
Reducing VG of MOSTs in SRAM cells
Shutting off leakage with power switch
New high-k gate insulator as the final solution
MPU
X 0.175/10y
DRAM
1.5V
2.75V
L
M
2.8
5.4
X 0.35/10y
10
8 Mb
e-DRAM
5
4
5.4
3
2.8
tunnel current
2
1970
1975
1980
1985
Year
1990
1995
2000
Gate Current Density (A/cm2)
Gate-oxide Thickness tox ( nm )
100
106
nFET
105
Measurement
Simulation
104
3
10
102
101
100
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
0.0
0.5
1.0
10 A
15 A
20 A
21.9A
25.6A
29.1A
32.2A
35.0A
36.1A
1.5
2.0
2.5
3.0
Gate Voltage (V)
D. J. Frank, 2002 VSI Circuits Symp. Short Course.
K. Itoh, Hitachi
7
Subthreshold Current
is  W·10 -VT /S
W
iS
S ~100 mV/dec.@100ºC
( x10 with VT = -100mV)
0
IACT of DRAM periphery
Iretention of 1-Mb SRAM
101
102
10A
10-2
10-4
10-6
1.2A
100
Current (A)
Current (A)
10
0
Tj 100C
75C
50C
25C
0C
1mA
IACT
10-1
1.5
IAC
10-2
10-3
Cycle time: 180 ns
T = 75C S = 97mV/dec.
10-4
IDC
10-8
10-5
10-10
10-6
10-12
0
0.5
16M 64M 256M 1G
4G
16G 64G
Capacity (bit)
1.0
Extrapolated VT(V) @25C
3.3
2.5
2.0
1.5 1.2
VDD (V)
0.53 0.40 0.32 0.24
1.0
0.8
0.19 0.16 0.13
Extrapolated VT at 25C (V)
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001
K. Itoh, Hitachi
Decreasing VT
Cells; shorter tREFmax /larger Iretention
 Ever-higher VT to meet spec.
Periphery; Leak dominates ISTB/IACT.
Ever-lower VT for LP/high speed
In principle, dual VT is desired.
Threshold Voltage VT (V)
VDD
DRAM: tREFmax  2/Gen
SRAM: 1mA@75C
1
SRAM Cell
DRAM Cell
0.5
0
F (mm)
tOX(DRAM) (nm)
tOX(SRAM) (nm)
DRAM (bits)
SRAM (bits)
Periphery
ITRS 2001
0.35
10
5
64 M
4M
0.25
7.5
3.75
128 M
8M
0.18
0.13
6.0
4.5
3
2.25
256 M 512 M
16 M
32 M
0.1
4
2
1G
64 M
8
Key to Subthreshold-Current Reduction
High-Speed Scheme applicable to Active Mode
 Reduction in high-speed active mode is difficult due to lack of
time to control the leakage, while in slow-speed standby mode
it is easy because of enough time available.
 Reduction scheme for active mode must be fast enough to
control the leakage within one cycle of active mode.
Such a scheme is also applicable to standby mode.
On the contrary, slow scheme cannot be applied to active mode,
even if it is applicable to standby mode.
 Key to High-Speed Scheme
Don’t swing a large capacitance at a large voltage for fast control.
If capacitance is large, swing it at the smallest voltage possible.
If capacitance is small, a large voltage swing is acceptable.
K. Itoh, Hitachi
9
G-S Self-Backbias (most useful)
SSI (Switched-S impedance,Q2) without SSI circuits with SSI
No matter how large i1’ is,
it is confined to the constant
Q1 W1, VT1
Q1 W1, VT1
0
0
current of Q2 with self-V /S
i1’ = aW110
 i1 = aW110-( +V )/S
adjustment of  .
a: current
Adjustable reduction with
Q2 W2, VT2
density
W2 and VT2.
0
i2 = aW210-V / S
Features;
constant
current
Large reduction with small 
i1 = i2.
Fast recovery due to small 
  = (VT2 – VT1) + (S/ln10) ln(W1/W2)
Automatic reduction due to
self-backbias.
Reduction Ratio  = i1 / i1’ = 10 /S
T1
T1
T2
= W2/W1 for VT2 = VT1
Reduction at  = 0.2V, 0.13-mm MOST;
G-S backbiasing of Q1; 1/100(primary)
Body Effect of Q1; 1/1.5(secondary)
DIBL of Q2; 1/3(secondary) even for W1 = W2  “Stacking Effect”
M. Horiguchi et al., Symp. VLSI Circuits Dig. Tech. Papers, p.47, 1993.
K. Itoh, Hitachi
10
Static/Dynamic High-VT Schemes
In practice combination of low-actual VT and high VT is used
to realize high speed with low VT/ low leakage with high VT.
High-VT realization
from low-actual VT
Static high VT
Implantation
Static VSUB
Dynamic high VT
G-S backbias
Sub-S backbias
G-S backbias
  0.2 V(1/100)
VT = VT0 + 
D
-
D
0
G
Sub
0
S
 = k ( + 2 2 )
k = 0.2 V1/2, 2 = 0.6 V
Sub
S
0
Sub-S backbias
  2.5 V (  0.2V)
VT = VT0 + 
+
0
G
+
D
D
0
G
Sub
S
+
0
-
G
Sub
S
0
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001
K. Itoh, Hitachi
11
Power Switch with Level Holder
“Don’t swing heavily-capacitive loads at a high voltage”
Power switches are off after
the input of low-VT circuit
has been evaluated, and then
the evaluated output has been
held at a high-VT level-holder.
This prevents the output from
discharging, allowing the switch
to quickly turn on at necessary
timing for preparing the next
evaluation.
Drawbacks; large area/large swing of switch
T. Sakata et al., 1993 Symp. VLSI Circuits.
K. Itoh, Hitachi
VDD
IN
power
switch
OUT
high-VT
level
holder
12
Applications to RAM Cells
 A dual-VT/dual-VDD/dual-tox approach for RAM cells
Cells need a high VT, and thus a high VDD/thick tox for a large Qs and
small itunnel.
Periphery needs low-VDD/low-VT, and thus thin-tox for LP/high speed.
However, this has not been widely accepted yet.
 Current status of leakage reduction of RAM-cells
Leakage / SE issues become serious for SRAMs.
DRAM

SRAM
DL
VDH
VDD
0

WL
WL
low VT
VDD
Cs
low-VT +  = high VT
DL
DL
QL
QT
QD
 G-S backbias to low-VT QT cuts
leakage and increases read current.
 High-VT QD/QL reduce leakage.
 Boosted supply VDH offsets highVT/VT of QD/QL, so signal charge
and drivability of QD are preserved.
VDD min at SNM= 0.1V, VT= 0.1V:
0.6 V at VDH –VDD= 0 V
0.3 V at VDH –VDD= 0.1 V
K. Itoh et al., VLSI Circuits Symp., p.132, June 1996
K. Itoh, Hitachi
13
Sub-S Backbias, High-VT SRAM Cell
Raised-S /lowered DL at active-standby transition
WL 0 V
Sub-S backbias
90% reduction of
subthreshold leakage
1.5 V
0.5 V
1.5 V
DL
1.0V
VSS
0.5V
1.5 V
0.0 V
G-S backbias
100% reduction of
subthreshold leakage
Electric-field
relaxation
90% reduction of
gate leakage & GIDL
DL
1.0V Standby
1.5 V Active
K.Osada et al. ISSCC2003 Dig. pp. 302-303
K. Itoh, Hitachi
14
Retention Current per Cell (measured)
Sub. + GIDL 48.5
Conv.
NMOST
Tunnel
46.5
NMOST
PMOST
PMOST
25ºC
95 fA
3 14
Prop.
17 fA
VT (extrap.) = 0.7 V(N), -1 V(P)
tox (electrical) = 3.7 nm
Tunnel 62
Sub. + GIDL
Conv.
NMOST
90ºC
1182
PMOST
NMOST
PMOST
1244 fA
81
Prop.
102 fA
K. Osada et al. ISSCC2003 Dig. pp. 302-303
K. Itoh, Hitachi
15
Sub-S Backbias, High-VT SRAM Cell
1.5-V 27-ns 6.42 x 8.76 mm2 16-Mb SRAM
ECC with 3.2ns/9.7 % speed/area penalties
Active Standby
Conv.
1.5 V
DL
1.0 V
Prop.
WL
VDD(1.5V)
0.5 V Prop.
Conv.
0V
Active Standby
Limitations and Challenges
DL
1. Still large current for power-aware
systems:1.6 mA for 16Mb even if high
VT/thick tox/Sub-S backbias are used.
VT (extrap.) = 0.7 V (N), -1.0 V (P)
tox (electrical) = 3.7 nm
Thus, higher VT/thicker tox are needed.
2. Reduced QS in standby mode restricts
low-voltage operations.
Further lowering VDD with the same
voltage swing increases SER due to
decreased Qs, implying that the scheme
will be less effective at lower VDD.
K. Osada et al. ISSCC2003 Dig. pp. 302-303
K. Itoh, Hitachi
16
Applications to Periphery (Active)
General Features of Periphery:
 Even in active mode, leakage from inactive
circuits will dominate the total leakage of chip,
since inactive circuits overwhelm active
circuits in number, as in all CMOS LSIs.
 Leakage from inactive circuits must be
reduced within one cycle of active mode,
calling for high-speed reduction schemes.
Periphery
active inactive
(selected) (non-selected)
Fortunately, periphery has favorable features to reduction.
K. Itoh, Hitachi
17
Favorable Features of Periphery
Selected WL
Nonselected
VDH
0
Dynamic
NAND
Memory array
Col.
Nondec. selected
tRC
V
WL DH
Nonselected
Selected
CLK
axi
Selected CSL
fX
axi
fP
Nonselected
Reduction Schemes;
 G-S self-backbias
 Multi-static VT with static
VSUB application
 Power switch with level holder
Row
dec. WD
VDH
Selected
(1) Iterative-Circuit Blocks
All circuits except the selected
one are inactive.
(2) Robust Circuits
NAND dec. for X/Y.
No leakage-sensitive NOR.
(3) Input-Predictable Logic
allows to prepare reduction
scheme in advance.
(4) Slow Cycle (tRC =25, 60 ns)
Each circuit is active only for
a short period within “long”
cycle, enabling additional time
for leak control.
Selected
Non-selected
VDD
fY
ayi
Static VDD
NAND
16-Gb DRAM
AC
DC
75
Driver
695
0
1180mA
(Subthreshold) 1105
Decoder
209
SA
drv. Others
132
69
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001.
K. Itoh, Hitachi
18
Applications of G-S Self-Backbias
Iterative Circuit Block
NAND Decoders (4-input)
n MOSTs in inactive circuits equivalent
to one MOST with W1 = nW.
 Reduction ratio  = W2/W1 = W2/nW
W2  W without speed penalty, because
one MOST is selected.    1/n.
With a larger n, leakage/area-penalties
due to Q2 are negligible (  0, W2 « nW).
“Stacking effect” reduces leakage
of non-selected decoders, although
the magnitude of reduction is input
-dependent.
0
1.5
without SSI
#0
with SSI
#n-1
Q W
0
i
W
0
i
=
Q1 W1 = nW
0

i1 = ni
1.5
i1 = ni
1.5
10nA0
0
0
0
1.5
0
1.5
1.7 0

1
0
1
0
0
2
1
0
3
0
1.5
0
Q2 W2
0
i2
VT = 0.25V
K. Roy, Tutorial, 2002 Symp. VLSI Circuits.
K. Itoh, Hitachi
2
0
0
0
0.7
19
Application to NAND Dec. Block
-SSI at NMOS Sourcen decoders divided into m sub-blocks,
n/m decoders each. SSI connected to
select each sub-block.
Standby Mode: All SSIs/dec.; off.
Total leakage  0.
Leakage of each sub-block  0,
if W2 is small.
Active Mode:
Selected SSI/dec.; on. Others; off.
n/m
Total leakage  leakage of
one selected sub-block ( i.e.,1/m).
Leakage of each non-selected
sub-block  0.
Leakage of the selected sub-block
is reduced due to“stacking effect”.
W2  W without speed penalty
because one decoder is selected.
 Small W2 / small  minimize area/
speed penalties.
K. Itoh, Hitachi
m
selected
VDD
non-selected
#0
#1
#m-1
p
a0
a1
a2
W
STB ACT
p
VDD
0
a0
0
a1
1
0
a2
2
 0
W2
SSI
0
0
0


n/m i
0
0
0
0
20
Application to Word-Driver Block
-SSI at PMOS Sourcen drivers divided into m sub-blocks,
n/m drivers each. SSI connected to
select each sub-block.
Standby Mode: All SSIs/drivers;off.
Total leakage  0
Leakage of each sub-block  0
Active Mode:
Selected SSI/driver;on. Others; off.
Total leakage  leakage of
one selected sub-block (i.e.,1/m).
Leakage of each non-selected
sub-block  0.
n/m
W2  W without speed penalty
because one driver is selected.
 Small W2/small  minimize
area/speed penalty.
e.g. 256Mb
 =1.5  10-3 ,  = 0.25V, recovery =1-2ns
with W2/W = 5, n/m = 256, S = 90mV/dec.
K. Itoh, Hitachi
selected
non-selected
VDD
W2
SSI
0
VDD
0
0
VDD
VDD-
W
0
VDD-
VDD
VDD
VDD
VDD
WL0
0
i
STB ACT
i
VDD
n/m i
0
WL7
#1
#0
m
#m-1
21
Active-Current Reduction (16-Gb)
1180mA
AC
DC
(Subthreshold)
75
Drivers
695
Decoder
209
Conventional
1105
SA Others
drv.
69
132
116
Proposed
SSI, dual VT,
power switch
75 41
VT = -0.12V, S = 97mV/dec., 75C
VDH = 1.75V, VDD = 1V, tRC = 180ns
Effectiveness with an actual chip has not been verified yet,
although the scheme was proposed as early as 1993.
T. Sakata et al., 1993 Symp. VLSI Circuits.
K. Itoh, Hitachi
22
Perspectives for RAM Cells
Existing DRAMs/SRAMs
Small cells while maintaining QS at a lower VDD
Gain cells (3-T cell) to maintain vsig at a lower VDD
On-chip ECC (small/fast) to cope with reduced QS
Emerging RAMs (Non-Volatile RAMs)
Attractive at low voltages;
Leakage-/SE-free structures
NDRO/Non-charge-based operations
Challenges;
Scalability/stability remain unsolved, as developments are at early stages.
FRAM; Stability (fatigue/imprint)
MRAM; Reduction of HW that increases with scaling
OUM; Reduction of proximity heating (Ovonic Unified Memories)
K. Itoh, Hitachi
23
Perspectives for Peripheral Circuits
As for memory, subthreshold current in active mode could be
reduced by improving CMOS circuits.
In fast RAMs(fast SRAMs), reduction is extremely difficult
without innovations. (Such is the case for SoC.)
 New devices such as FD-SOI with smaller S-factor
 Innovative LP circuits learned from “old circuits” such as Bip/BiC, E/D,
gate boost, CML, and I2L.
( Memory-rich SoC architectures to reduce no. of random logic gates.)
Percentage of Area ()
100
LSTP/LOP: Low Standby/Operating Power
LSTP
LP-SOC
100mm2, 0.1W
80
On-chip L3 cache in MPU
LOP
Itanium™ MPU
Memory
60
ITRS2001
L3 Cache
40
Logic
LOP
20
0
LSTP
2001
2004
2007
2010
Year
K. Itoh, Hitachi
L3 Cache
2013
L3 Cache
0.18-mm 6-Al metal
ECC/redundancy
24-Mb L3-SRAM
1.5V, 1.2GHz
L3 Cache
2016
Don Weiss, ISSCC2002, p.112.
24
Conclusion
1. Trends in LV RAMs were explained.
2. LV RAM circuits focusing on reducing leakage
current of cells and periphery were discussed.
3. Perspective was given with emphasis on needs
for new devices/circuits for reducing active-mode
leakage currents, and high-speed NV-RAMs.
K. Itoh, Hitachi