Transcript Power Distribution - Indico

Power Distribution
Peter W Phillips
STFC Rutherford Appleton Laboratory
ECFA HL-LHC Workshop, Aix-les-Bains, 1-3 October 2013
Abstract
The power distribution systems of the LHC experiments use a number of stages to convert power
from the 50Hz mains grid to the voltages needed by the front end systems. In many cases a final
linear regulation step takes place in the front end system, but in other cases this step takes place
off-detector, presenting challenges in terms of stability as remote sensing must be used to
maintain the correct voltage at the point of load. In any event, resistive losses in the power
cables are often of a similar magnitude to the delivered power. Considering the low voltages and
high currents needed by contemporary front end designs, reduced tolerance to over-voltage
events and the increased channel counts in some of the proposed detector systems, it is clear
that new power distribution strategies are required.
Two alternate powering schemes are being studied with a view to HL-LHC: DC-DC Conversion and
Serial Powering. Radiation hard DC-DC converters with air-core inductors have been designed
and built, as have the circuit blocks needed to operate a chain of serially connected detector
modules, and both schemes have been shown to perform well in small-scale system tests. In
addition, switched capacitor DC-DC converters have been demonstrated to be a viable, high
efficiency alternative to on-chip linear regulators. The status of this work shall be shown and the
merits and drawbacks of each scheme outlined. The directions of future development shall be
described, as required to deliver reliable, low-mass powering solutions on an appropriate
timescale.
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
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Outline
• Power Distribution at LHC
– Individual Powering
– Parallel Powering
– Motivations for change
• Serial Powering
– Switched Capacitor
• Concept
• Examples
• HV Multiplexing
• Conclusions
– Concept
– Examples
• DC-DC Point of Load
– Buck Converter
• Concept
• Examples
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
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Example: ATLAS SCT (Silicon Strips)
• 4088 Detector Modules
• Independent Powering
–
–
–
–
4088 cable chains
22 PS racks in service caverns
4 crates / rack
(up to) 48 LV and 48 HV channels /
crate
• Longest cable run
– ~130m copper cable (3 gauges)
– ~2m copper/kapton (endcap) or
aluminium/kapton (barrel) power
tapes
– Voltage limiter in line to block
spikes due to sudden drops in load
• Typical overall efficiency ~40%
Peter W Phillips
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Example: CMS Silicon Strip Tracker
• 15000 Detector Modules
• Parallel Powering
–
–
–
–
1944 “detector power groups”
29 racks in main cavern
(up to) 6 crates per rack
CAEN EASY system for “hostile
environments”
• Magnetic field tolerant
• Radiation tolerant
• Typical cable run
• 40m copper + 6m aluminium
• ~48% power lost on cables
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Motivations for Change
More Channels
=> More Power
•
•
•
•
More Power
=> More Copper
Identify alternate powering
schemes which
Increase Efficiency
Reduce Cost
Reduce Material
Reduce Risk
More Copper
 More Money
Lower V
I drops => risk of
damage
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
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Why Serial Powering?
R/2
V
R/2
R/2
LOAD
LOAD
LOAD
R/2
R/2
V
LOAD
V
LOAD
I
LOAD
R/2
R/2
V
LOAD
R/2
Independent
Powering
LOAD
LOAD
R/2
R/2
Parallel
Powering
Serial
Powering
Losses in off-detector cabling of total resistance R for n loads drawing current I:
P = nI2R
P = n 2I2R
P = I 2R
Serial Powering offers higher system efficiency than Independent or Parallel Powering.
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
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More on Serial Powering
• Elements of a serially powered system
R/2
LOAD
I
LOAD
–
–
–
–
Current Source
Shunt regulator / transistor
AC or opto-coupling of control signals
Protection circuit & Bypass shunt
• Shunt current past faulty device in response to overvoltage condition or under DCS control
LOAD
R/2
• Current must be sufficient to power the
biggest load in the chain
– Best suited to chains of devices with same
current demand
• Requires very little additional material
– Can be useful for tracking detectors
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
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Example: ATLAS Pixel Shunt-LDO
• Combined Shunt and LDO (ShuLDO) in FE-I4
– The left part is a standard LDO
– The right part is the shunt circuit
• Benefit wrt standard shunt regulators
– Shunt-LDO regulators generating different output voltages can be
placed in parallel without any problem regarding mismatch and shunt
current distribution
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
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Example: ATLAS Strip Stave (SP)
•
Distributed SP Architecture
–
–
•
Three short (4 module) prototypes built
–
–
•
Shunt transistors within ABCN25 FE ASIC, 20 per hybrid
One control block per hybrid (SPP chip or commercial parts)
Distributed SP Architecture (within the hybrid)
Some with protection circuitry (SPP chip commercial parts)
Good results in “Chain of Modules” Configuration
Longer (12 module) prototype to follow in the coming months
–
With integrated protection from SPP chip
0V
2.5V
Peter W Phillips
5V
7.5V
ECFA HL-LHC Workshop, Aix-les-Bains
10V
10
Synchronous Buck Converter
ON
ON
Output voltage is regulated by adjustment of the duty cycle of the two switch transistors
Losses in off-detector cabling of total resistance R for n loads drawing current I
through individual DC-DC Point of Load converters (one per load):
P = n 2 I2 R / g 2
where g = Vin/Vout
HL-LHC converter specs: Vin typically 10, Vout typically 1.5V, so gain typically 6 to 7
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
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Why not COTS?
• Commercial Point of Load Buck
Converters
– readily available
– cheap & efficient
– small and reliable
• BUT
– ferrite-cored inductors
• 2 – 4 Tesla magnetic field 
– not radiation hard
• ~1 MGy and 1015 1MeV neutrons/cm-2 
• We need custom converters
– air-cored inductors
– radiation hardened ASIC
– for tracker applications: low mass design
Peter W Phillips
Front and Rear views of a Typical
Commercial Point of Load
DC-DC Converter (case removed):
Input 24V, Output 5V 1A, 90% efficiency
ECFA HL-LHC Workshop, Aix-les-Bains
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Custom Buck Converters
•
FEAST, a “production ready” buck converter
ASIC, is now under test at CERN
– Follows on from AMIS5 prototype in same,
commercial 0.35um technology
•
FEAST DC-DC converter Module
–
–
–
–
–
127um thick tinned copper shield (not shown)
Custom 430nH oval air-cored inductor
Vin 5V (6V for AMIS5) to 12V (min Vin = Vout+2V)
Vout 1.2V to 5V, 4A max
EMC compliant with conductive noise
requirements of CISPR11 Class B
– TID above 200Mrad, displacement damage up to
7e14 1MeV neutrons/cm2
– Magnetic field tolerance > 40,000 Gauss
•
AMIS5MP: 3.7cm x 1.7cm
Sample converters with AMIS5 available now
– Includes module to generate –V from +V
•
Converters with FEAST available 2014
– 10,000 units to be made for Phase 1 LHC upgrades
Peter W Phillips
FEAST: Preliminary Efficiency Data @ 1.8MHz
ECFA HL-LHC Workshop, Aix-les-Bains
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Example: Phase 1 Calorimeter
• Information to follow from Federico
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
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Example: CMS Pixel Upgrade
• For installation in 2016-17 shutdown
– x1.9 increase in channel count
• x1.9 increase in power consumption
– Must use existing cable plant
• Even today, 50% power lost in cables
• Use DC-DC converters with AMIS5 / FEAST
– Smaller, round 220nH air-cored inductor
– Converters located 2.2m away from modules
AC_PIX_V8 A: 2.8cm x 1.6cm; ~ 2.0g
– 13 converter pairs (analogue, digital) per bus board
•
Each converter pair serves 1 - 4 pixel modules
– Iout < 3A per converter
• No noise increase due to use of DC-DC converters
Prototype bus board with 24 DC-DC converters
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
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Example: ATLAS Strip Stave (DC-DC)
•
STV-10 Buck Converters from CERN group used on stave
– Based on commercial chip due to high current requirement
•
Three short (8 hybrid) prototypes built
– All with good results
•
Longer (24 hybrid) prototype under construction
H0
H1
H0
H2
H3
H1
H4
H2
H5
H3
H6
H7
H4
H5
H6
H7
Column
0
1
2
3
4
5
6
7
8
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14
15
ENC@
1.0fC
648
620
656
689
651
627
640
673
651
624
632
660
638
612
626
650
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
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DC-DC with Switched Capacitors
Phase 1 – Charge in series
2
1
1
2
2
1
2
Phase 2 – Discharge in parallel
2
1
2
2
1
Load
No inductors – can be implemented on our FE hybrids – even completely in the FE ASICs
• A high efficiency alternative to on-chip LDOs
• Much industrial R&D focussed in this area
• May be used as part of a DC-DC or SP powering scheme
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
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Example: Switched Capacitor DC-DC
circuit in ATLAS Pixel FE-I4A
• Non-overlapping Clock Generator
– generates 3 internal clocks from CLK_IN
– same frequency but different phase & duty
• Charge Pump
– consists of 4 transistors working as switches
– manipulates pump capacitor under control
of clocks
• External Pump Capacitor
– Must be close to ASIC for good results
– No significant impact upon noise
performance when Cpump on top of FE-I4A
•
Missing pixels unstable, not related to DC-DC
• Demonstrates Technique is Viable
– Best results would require access to ASIC
technologies with embedded capacitors
Normal Power
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
DC-DC Power
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HV MUX
• Material of HV cables can also be a concern in
tracking applications
• Could parallel power n sensors
– Lose all n sensors if one sensor fails as a short
• Solution: radiation hard HV transistor switch
200V GaN FET
– Can now disconnect any failed sensors
– Requires control signal near HV potential
• Present phase: Identification of Devices
800 μm
– Study of commercial HV switches
• GaN, Silicon, Silicon Carbide
• Characterisation before and after irradiation
– Study of possible driver circuits
300V Silicon JFET
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
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Conclusions
• Two main power strategies being explored for HL-LHC
– SP circuit blocks built, small scale system tests give
encouraging results
– Radiation hard, air cored DC-DC converters have been
demonstrated
• In addition
– Switched capacitor DC-DC conversion is a viable, high
efficiency alternative to on-chip LDO regulators
– Risks associated with parallel sensor biasing can be
eliminated if suitable HV switch transistors can be
identified
• Continued support needed to deliver suitable parts in
time for HL-LHC
Peter W Phillips
ECFA HL-LHC Workshop, Aix-les-Bains
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