Transcript Introduction to Phase

Phase Lock Loop
EE174 – SJSU
Tan Nguyen
OBJECTIVES
• Introduction to Phase-locked loop (PLL)
• Historical Background
• Basic PLL System
• Phase Detector (PD)
• Voltage Controlled Oscillator (VCO)
• Loop Filter (LF)
• PLL Applications
Introduction to Phase-locked Loop (PLL)
• PLL is also referred as frequency synthesizer.
• PLL is a circuit that locks the phase of the output to the input.
• PLL is a negative feedback control system where fout tracks fin and rising edges of
input clock align to rising edges of output clock
• PLL is a circuit synchronizing an output signal with a reference or input signal in
frequency as well as in phase.
• In the synchronized or “locked” state, the phase error between the oscillator’s
output signal and the reference signal is zero, or it remains constant.
• If a phase error builds up, a control mechanism acts on the oscillator to reduce
the phase error to a minimum so that the phase of the output signal is actually
locked to the phase of the reference signal. This is why it is called a phase-locked
loop.
How Are PLLs Used?
Brief Phase-Locked Loop (PLL) History
1932: Invention of “coherent communication” using vacuum tube, (deBellescize)
1943: Horizontal and vertical sweep synchronization in television (Wendt and
Faraday)
1954: Color television (Richman)
1965: PLL on integrated circuit
1970: Classical digital PLL
1972: All-digital PLL
PLLs today: in every cell phone, TV, radio, pager, computer, …
Clock and Data Recovery
Frequency Synthesis
Clock Generation
Clock-skew minimization
Duty-cycle enhancement
1.people.ee.duke.edu/~mbrooke/defense/Borte.ppt
Basic PLL System
The basic PLL block diagram consists of three components connected in a feedback loop :
• A phase detector (PD) or phase frequency detector (PFD)
• A voltage-controlled oscillator (VCO)
■ The phase detector produces a signal V𝝓
• A loop filter (LF)
proportional to the phase difference between the
incoming signal and the VCO output signal.
■ The output of the phase detector is filtered by a
low-pass loop filter. The filter output voltage Vo
controls the frequency of the VCO.
■ The voltage at the input of the VCO determines
the frequency fosc of the periodic signal Vosc at the
output of the VCO.
A basic property of the PLL is that it attempts to maintain the frequency lock fosc= fi between Vosc and Vi even if the
frequency fi of the incoming signal varies in time.
Suppose that the PLL is in the locked condition, and that the frequency fi of the incoming signal increases slightly.
The phase difference between the VCO signal and the incoming signal will begin to increase in time.
As a result, the filter output voltage Vo increases  the VCO output frequency fosc increases until it matches fin,
thus keeping the PLL in the locked condition.
Locked Range and Capture Range of the PLL
Locked condition: fosc = fi
Unlocked condition: fosc = fo = const
Lock Range of the PLL: The range of frequencies from fi = fmin to fi = fmax where the locked PLL remains in the locked
condition. The lock range is wider than the capture range.
• If the PLL is initially locked, and if fi < fmin, or fi > fmax  the PLL becomes unlocked fi ≠ fosc. When the PLL is unlocked,
the VCO oscillates at the frequency fo called the center frequency, or the free-running frequency of the VCO.
Capture Range of the PLL: The lock can be established again if the incoming signal frequency fi gets close enough to fo.
The range of frequencies fi = fo- fc to fi = fo+ fc such that the initially unlocked PLL becomes locked. Sometimes a
frequency detector is added to the phase detector to assist in initial acquisition of lock.
Locked Range and Capture Range of the PLL
• Once the PLL is in the locked condition, it remains locked as long as the VCO output frequency fosc can be
adjusted to match the incoming signal frequency fi  fmin ≤ fi ≤ fmax.
• When the lock is lost, the VCO operates at the free-running frequency fo,  fmin ≤ fo ≤ fmax.
• To establish the lock again, i.e. to capture the incoming signal again, the incoming signal frequency fi must be
close enough to fo  fo– fc ≤ fi ≤ fo+ fc . The 2fc is called the capture range.
• The capture range 2fc is an important PLL parameter because it determines whether the locked condition can
be established or not. Note that the capture range 2fc < the lock range fmax – fmin.
• The capture range 2fc depends on the characteristics of the loop filter. For the simple RC filter, a very crude,
approximate implicit expression for the capture range can be found as:
where fp is the cut-off frequency of the filter, VDD is the supply voltage, and Ko is the VCO gain.
• If the capture range is much larger than the cut-off frequency of the filter, fc/fp >> 1, the expression for the
capture range is simplified as:
• Lower fp is desirable in order to better attenuate high frequency and improve noise rejection but it cause
capture range smaller as usually desirable to have wider capture range.
Phase Detector (PD)
A simple phase detector is an XOR gate with logic low output
(Vφ = 0V) and the logic high output (Vφ = VDD).
An example below shows the PLL is in the locked condition
where Vi and Vosc are two phase-shifted periodic square-wave
𝟏
signals at the same frequency fosc = fi = T , and with 50% duty
i
ratios. The output of the phase detector is a periodic squarewave signal Vφ(t) at the frequency 2fi , and with the duty ratio
Dφ that depends on the phase difference φ(t) = [φosc(t) - φi(t)]
between Vi and Vosc  Dφ =
φ
𝝅
(for XOR)
The output of the XOR phase detector can be written as the
Fourier series:
The dc component Vo of the phase detector output can be
T
found easily as the average of Vφ(t) over a period 𝟐i
 Vo =
VDD
𝝅
where KD =
φ = KD φ
VDD
𝝅
volts/rad
KD is called PD gain
for 0 ≤ φ ≤ π
V
The average output rise to Vout = πDD ΔΦ = 0 → VDD when ΔΦ goes from 0 → π.
For ΔΦ > π , the average output begins to drop.
Loop Filter
The output Vφ(t) of the phase detector is filtered by the low-pass loop filter. The purpose of the low-pass filter is to
pass the dc and low-frequency portions of Vφ(t) and to attenuate high-frequency ac components at frequencies 2kfi .
The simple RC filter has the transfer function:
F(s) =
𝟏
𝟏+𝒔 𝑹 𝑪
=
1
𝟏
𝟏 + 𝒔/ω𝒑
ω
where ωp = 𝑅 𝐶 and fp = 2𝛑𝑝 is the cut-off frequency of the filter.
If fp << 2fi  the output of the filter Vo is approximately equal to the
dc component V𝝓 of the phase detector output.
In practice, the high-frequency components are not completely eliminated
and can be observed as high-frequency ac ripple around the dc or slowly-varying Vo.
In general, the filter output Vo as a function of the phase
difference. Note that Vo = 0 if Vi and Vosc are in phase (𝝓 = 0),
and that it reaches the maximum value Vo = VDD when the two
signals are exactly out of phase (𝝓 = π).
For 0 ≤ 𝝓 ≤ π, Vo increases, and for 𝝓 > π, Vo decreases. The
characteristic of periodic in 𝝓 with period 2π.
The range 0 ≤ 𝝓 ≤ π is the range where the PLL can operate in
the locked condition.
Voltage Controlled Oscillator (VCO)
In PLL applications, the VCO is treated as a linear, time-invariant system. To obtain an arbitrary output frequency (within
the VCO tuning range), a finite Vo is required. Let’s define φosc– φi = φ.
The XOR function produces an output pulse whenever there is a phase misalignment. Suppose that an output frequency
ω1 is needed. From the upper right figure, we see that a control voltage V1 will be necessary to produce this output
frequency. The phase detector can produce this V1 only by maintaining a phase offset φ at its input. In order to minimize
the required phase offset or error, the PLL loop gain, KD KO, should be maximized, since φ =
𝑽𝟏
𝑲𝑫
=
𝒇𝟏 − 𝒇𝟎
𝑲 𝑫𝑲 𝑶
The VCO gain is defined as:
Ko =
VCO Example
The filter output Vo controls the VCO, i.e., determines the frequency fosc of the VCO output Vosc . From PLL 4046 circuit
below, the voltage Vo controls the charging and discharging currents through capacitor C1. As a result the frequency fosc
of the VCO is determined by the Vo. The VCO output Vosc is a square wave with 50% duty ratio and frequency fosc.
The VCO characteristics are adjustable by three components:
R1, R2 and C1.
When Vo = 0, the VCO operates at the minimum frequency
fmin given approximately by:
fmin =
𝟏
𝑹𝟐(𝑪𝟏+𝟑𝟐 𝒑𝑭)
When Vo = VDD, the VCO operates at the minimum frequency
fmax given approximately by:
𝟏
fmax = fmin+ 𝑹𝟏(𝑪𝟏+𝟑𝟐 𝒑𝑭)
For fmin ≤ fosc ≤ fmax, the VCO output frequency fosc is ideally a
linear function of the control voltage Vo.
Δf
The slope Ko = osc of the fosc(Vo) characteristic is called the
Δ𝑽𝒐
gain or the frequency sensitivity of the VCO, in Hz/V.
Examples
Problem 1.
Determine the change in frequency for a voltage controlled oscillator (VCO) with a transfer function of KO = 2.5KHz/V
and a DC input voltage change of ΔVO = 0.8V.
Solution:
Δf = ΔVO KO  Δf = (0.8 V)(2.5 kHz/V) = 2 kHz
Problem 2.
Calculate the voltage at the output of a phase comparator with a transfer function of KD = 0.5V/rad and a phase error
of Vϴ = 0.75 rads.
Solution:
VD = KD Vϴ = (0.5 V/rad)(0.75 rad) = 0.375 V
Problem 3.
Determine the hold in range, (i.e. the maximum change in frequency) for a phase lock loop with an open loop gain of
KV = 20kHz/rad.
Solution:
Δfmax = KV π/2 = (20 krad) π/2 rad = 31.4 kHz
Problem 4.
Find the phase error necessary to produce a VCO frequency shift of Δf = 10KHz for an open loop gain of
KV = 40KHz/rad.
Solution:
Vϴ = Δf / KV = 10 kHz / 40 kHz/rad) = 0.25 rad
Problem 5:
Given fosc = 1.2 MHz at VCOin = 4.5 V and fosc = 380 kHz at VCOin = 1.6 V. Find Ko
Solution:
Ko = 2π x (1.2 MHz – 380KHz) / (4.5V – 1.6V) rad/V = 1,777 krad/s/v
Overall PLL system
First we will consider the PLL with feedback = 1; therefore, input and output
frequencies are identical. The input and output phase should track one another,
but there may be a fixed offset depending on the phase detector
implementation.
Vi
Vosc
Frequency and phase tracking loop
We will start from the open loop gain, T(s).
T(s) = KDF(s)KO/s
F(s) is a simple LPF with a cutoff (3 dB) frequency ω1 = 1/RC.
Then, T(s) becomes second order, Type 1:
Frequency and phase tracking loop
It is sometimes useful to define a natural frequency, ωn, and a damping factor, ζ. This is standard control
system terminology for a second order system. The key is to put the denominator of the closed loop
transfer function, 1 + T(s), into a “standard” form:
either s2
+ 2 ζ ωn s + ωn
2
s2
2ζ
or
+
+1
ωn2 ωn
Taking the first formula, 1 + T(s) can be written as:
so, we can associate ωn and ζ with:
Example
A phase-locked loop has a center frequency of ω0 = 105 rad⁄s, KO = 103 rad/s per V, and KD =
1 V/rad. There is no other gain in the loop. Determine the overall transfer function H(s) for:
a) The loop filter is F(s) = 1.
b) The loop filter F(s) is shown below.
ω1 = 1/RC
= 1/(120k x3.3nF) = 2525
Example
Consider a PLL with KO = 250 krad ⁄ s per V and that uses a Type I (XOR) phase detector KD
= Vcc / π. The supply voltage is 5 V, and a simple RC filter (see below) is used. For the filter
R = 120 kΩ and C = 3.3 nF. There is no other gain in the loop.
a) Determine the transfer function H(s) = ϴo(s) ⁄ ϴi(s) of the loop.
b) Calculate natural frequency ωn and damping ratio ζ.
Synthesizer PLL
We will now add the divider 1/N to the feedback path.
This architecture is called an “integer-N” synthesizer.
We can calculate the loop gain, T(s):
• Loop gain is reduced by a factor of N.
• In most applications, N is not constant, so KV = KDKO is not a constant – varies
with frequency according to the choice of N
Synthesize PLL
Phase Lock Loop
Applications
EE174 – SJSU
Tan Nguyen
PLL Applications
FM Demodulation
Phase-Locked Loop Based Clock Generator
PLL perform:
• Clock input division
• Frequency Multiplication
In this manner, the non integer frequencies can be developed.
Integer-N Frequency Synthesizers without Prescalers
Divider /R
Frequency synthesizers are found in FM receivers, CB transceivers, TV receivers, etc.
In these applications, there is a need for generating a great number of frequencies
with a narrow spacing of 50, 25, 10, 5, or even 1 kHz. If channel spacing of 10 KHz is
desired, a reference frequency of 10 KHz is normally chosen. A quartz crystal
oscillating in kHz region is quite bulky and not practical. A more convenient to use
higher frequency crystal in the range of MHz and scale down to desired reference
frequency. This circuit is also included on most ICs.
Integer-N Frequency Synthesizers with Prescalers cont.
Divider /R
fosc = 10MHz
Four-modulus prescalers
To extend the upper frequency range of a frequency synthesizer but still allows
the synthesis of lower frequencies. The solution is the four-modulus prescaler.
The four-modulus prescaler is a logical extension of the dual-modulus prescaler. It
offers four different scaling factors, and two control signals are required to select
one of the four available scaling factors.
Integer-N Frequency Synthesizers with Prescalers cont.
As an example, the four-modulus prescaler can divide by factors of 100, 101, 110, and 111. By definition, it
scales down by 100 when both control inputs are LOW. The internal logic of the four-modulus prescaler is
designed so that the scaling factor is increased by 1 when one of the control signals is HIGH, or increased by
10 when the other control signal is HIGH. If both control signals are HIGH, the scaling factor is increased by 1 +
10 = 11.
There are three programmable /N counters in the system: /N1, /N2, and /N3 dividers. The overall division ratio
is given by:
Ntot = 100N1 + 10N2 + N3
In this equation N3 represents the units, N2 the tens, and N1 the hundreds of
the division ratio Ntot. Here N2 and N3 must be in the range 0 to 9, and N1 must be at least as large as both N2
and N3 because when the content of N1 becomes 0, all /N1, /N2 and /N3 counters are reloaded to their preset
values, and the cycle is repeated (N1,min = 9). The smallest realizable division ratio is consequently:
Ntot,min = 100 x 9 = 900
For a reference frequency f1 of 10 kHz, the lowest frequency to be synthesized is therefore: 900 x f 1 = 9 MHz.
Integer-N Frequency Synthesizers Examples
Numerical Example: We wish to generate a frequency that is 1023 times the reference frequency. The
division ratio Ntot is thus 1023; hence N1 = 10, N2 = 2, and N3 = 3 are chosen. Furthermore, we assume
that the /N1 counter has just stepped down to 0, so all three counters are now loaded to their preset
values. Both outputs of the /N2 and /N3 counters are now HIGH, a condition that causes the fourmodulus prescaler to divide initially by 111.
Solution: After N2 x 111 = 2 x 111 = 222 pulses generated by the VCO, the /N2 counter steps down to
0. Consequently, the prescaler will divide by 101. At this moment, the content of the /N3 counter is 3 –
2 = 1. After another 101 pulses
(1 x 101) have been generated by the VCO, the /N3 counter also steps down to 0. The division ratio of
the four-modulus prescaler is now 100.
The content of the /N1 counter is now 7. After another 700 pulses (7 x 100) have been generated by
the VCO, the /N1 counter also steps down to 0, and the cycle is repeated. To step through an entire
cycle, the VCO had to produce a total of
Ntot = 2 x 111 + 1 x 101 + 7 x 100 = 1023 pulses, which is exactly the number desired.
Jitters Example
Clock Data Recovery
The first CDR design required that the same clock used to serialize the
data be sent to the receiver alongside the data. This method created
some added problems for the receiver, as it had to deal with the jitter in
the data stream and with the jitter in the clock stream, alongside the data
stream. Another issue is the amount of data links is reduced by two using
this system.
Differentiation CDR
The steps taken by the algorithm to obtain the recovered data. The first plot is
the input data, the second is the differentiated input data. We can see that the
peaks occur at the zero crossings of the input data. The third plot is the fullwave
rectified differentiated data. This data is used to create a clock, which is then
used to create the fourth plot, the regenerated data
Clock Data Recovery
To counteract the effect of the system described earlier, a method
utilizing two separate clock was developed. The transmitter serializes the
data stream using the clock A. The cdr, at the receiver, uses information
from a reference clock, clock B, located at the receiver end. To
accomplish this operation a Phase-Locked Loop (PLL) is used.
Integer-N Frequency Synthesizers with Prescalers
Fixed division ratio prescalers:
To generate higher frequencies, prescalers are used; these are often built with
other IC technologies such as ECL, Schottky TTL, GaAs (gallium-arsenide), or
SiGe (silicon-germanium compound). Such prescalers extend the range of
frequencies into the microwave frequency bands. This implies that it is no longer
possible to generate every desired integer multiple of the reference frequency f1;
if V = 10, only output frequencies of 10xf1, 20xf1, 30xf1, and so on can be
generated.
Integer-N Frequency Synthesizers with Prescalers cont.
Dual-modulus prescalers
A counter whose division ratio can be switched from one value to another by an
external control signal. As an example, the prescaler above can divide by a factor of
11 when the applied control signal is HIGH, or by a factor of 10 when the control
signal is LOW. It can be demonstrated that the dual-modulus prescaler makes it
possible to generate a number of output frequencies that are spaced only by f1 and
not by a multiple of f1.
Integer-N Frequency Synthesizers with Prescalers cont.
The following conventions are used with respect to dual-modulus prescalers:
■ Both programmable /N1 and /N2 counters are DOWN counters.
■ The output signal of both of these counters is HIGH if the content of the
corresponding counters has not yet reached the value 0.
■ When the /N1 counter has counted down to 0, its output goes LOW and it
immediately loads both counters to their preset values N1 and N2, respectively.
■ N1 is always greater than or equal to N2.
■ As shown by the AND gate, underflow below 0 is inhibited in the case of the
/N2 counter. If this counter has counted down to 0, further counting pulses are
inhibited.
Integer-N Frequency Synthesizers with Prescalers cont.
The operation of the system becomes clearer if we assume that the /N1 counter
has just counted down to 0 and both counters have been loaded with their preset
values N1 and N2, respectively. We now have to find the number of cycles the VCO
must produce until the same logic state is reached again. This number is the overall
scaling factor Ntot of the arrangement shown in Fig. 6.4. As long as the /N2 counter
has not yet counted down to 0, the prescaler is dividing by V + 1. Consequently,
both the /N1 and the /N2 counters will step down by one count when the VCO has
generated V + 1 pulses. The /N2 counter will therefore step down to 0 when the
VCO has generated N2 x (V + 1) pulses. At that moment, the /N1 counter has
stepped down by N2 counts—that is, its content is N1 – N2.
The scaling factor of the dual-modulus prescaler is now switched to the value
V. The VCO will have to generate additional (N1 - N2)V pulses until the /N1
counter steps to 0. When the content of N1 becomes 0, both the /N1 and the
/N2 counters are reloaded to their preset values, and the cycle is repeated.
How many pulses Ntot did the VCO produce to run through one full cycle? Ntot
is given by:
Integer-N Frequency Synthesizers Examples
If V = 10, Ntot = 10N1 + N2
In this expression, N2 represents the units and N1 the tens of the overall division
ratio Ntot. Then N2 must be in the range of 0 – 9, and N1 can assume any value
greater than or equal to 9—that is, N1,min = 9. The smallest realizable
division ratio is therefore: Ntot,min = N1,minV = 90
The synthesizer is thus able to generate all integer multiples of the reference
frequency f1 starting from Ntot = 90.
If V = 16, Ntot = 16N1 + N2, Then N2 range of 0 – 15  N1,min = 15.
In this case, the smallest realizable division ratio Ntot,min = 16 x 15 = 240.
Using V = 100, Ntot = 100N1 + N2
where N2 range of 0 – 99  N1,min = 99.
In this case, the smallest division ratio Ntot,min = 100N1,min = 100 x 99 = 9900
If the reference frequency f1 = 10 kHz, the lowest frequency to be synthesized is
now 9900 x 10 KHz = 99 MHz.
References:
http://www.scribd.com/doc/237983665/PLL
http://www.delroy.com/PLL_dir/tutorial/PLL_tutorial_slides.pdf
Phase Locked Loops 6/e, 6th Edition by Roland Best
https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF8#q=an535
http://eprints.lancs.ac.uk/52334/1/PLLbook_chapter_final_2.pdf
http://www.ti.com/lit/ds/symlink/lm565.pdf
PLL-74HC4046_Application_Note%20(1).pdf
http://users.ece.gatech.edu/pallen/Academic/ECE_6440/Summer_2003/L170FreqSyn-I(2UP).pdf
http://iris.lib.neu.edu/cgi/viewcontent.cgi?article=1007&context=elec_comp_theses
References:
http://www.scribd.com/doc/237983665/PLL
http://www.seas.ucla.edu/brweb/teaching/215C_W2013/PLLs.pdf
http://www.ece.ucsb.edu/~long/ece594a/PLL_intro_594a_s05.pdf
http://www.ti.com/lit/an/snoa351/snoa351.pdf
http://memo.cgu.edu.tw/jtkuo/files/eelab%202014%28III%29/1230_Lab12_Expxx_PhaseLoc
kedLoop.pdf
http://siihr64.iihr.uiowa.edu/MyWeb/Teaching/ece_55141_2013/Homework/HomeworkAs
signment08Solution.pdf
http://www.freeclassnotesonline.com/VCO-and-PLL-Calculations-HW.php
http://ecee.colorado.edu/~ecen4618/lab4.pdf