Transcript Additional blocs

Etat d’avancement de la conception des Blocs FEI4
CPPM, Université de la méditerranée, CNRS/IN2P3, Marseille, France
1
Outline

Introduction

Memory block for the global configuration : CNFGREG

Temperature sensor : TEMPSENS

10 bit Global ADC : GADC

Variants :
 Pixel configuration
 Low Power discriminator

Additional blocs ?
Réunion Electronique pour SLHC
16/11/2009
2
CNFGMEM

Layout : DRC and LVS ok

Post layout simulations in order to estimate the
influence of long wires capacitances on the time
response.
Memory cell
5:32 decoder
16 rows by 32 colomns
All inputs and outputs pins are on the top side
Block dimensions : 900µm × 360µm

Buffers are ok

Output amplifier not needed

Next step :

From the review : Only one error out for the whole bloc
(instead of 1 per word)

Voltage shifters: 1.2 V to 1.5 V

Schematic ok and layout have to be done

Error In pull up for the first stage have to be done

Verilog modelling for the memory cell

Corners simulations

Estimate timing parameters for write and read cycles

1 week of work to freeze the design
Réunion Electronique pour SLHC
16/11/2009
3
TEMPSENS

The schematic is ok

Layout : DRC and LVS not yet
completed

Next step :

Finalise the layout

Post layout simulations in order to
estimate the influence of long wires
resistances on the current value

Corners simulations

3-4 weeks of work to finalize the design
Réunion Electronique pour SLHC
16/11/2009
4
GADC

Schematic

The comparator not yet figed

Global simulation : Ok

Layout

DAC and MUX ok

SAR control logic : in progress

Comparator : have to be done

Next step :

SAR design

Comparator design

Corner and mismatch simulations for the GADC

Global layout

Post layout simulations

2 weeks for the SAR

2 weeks for the comparator

2 weeks for the Global layout
Réunion Electronique pour SLHC
16/11/2009
5
Pixel Configuration

Layout in progress

2 weeks to finalize the bloc
Réunion Electronique pour SLHC
16/11/2009
6
Low power discriminator
M8
M13
M14
M3

Layout ok

To be done when the pixel array is fully
designed
 Additional Vdddiscri …
M4
M6
IM11
VTH
IM9
M11

M12
M1
1 week to implement the bloc in the pixel
M2
VIN
M15
W/L
M9
IB1
K*W/L
IM10
IB2
M5
M7
M10
Réunion Electronique pour SLHC
16/11/2009
7
Planning
16-20
CNFGMEM
Mohsine
TEMPSENS
Fabrice
SAR
23-27
14-18
Laurent
Mohsine
Global
Pixel conf
7-11
Fabrice
Comp
GDAC
30-4
Laurent
Denis
Denis
Réunion Electronique pour SLHC
16/11/2009
8
Additional blocs ?

An analog MUX and output analog buffer :
 The MUX should have 32 analog voltage inputs 5-bit address input
 single analog output with a buffer capable of driving a passive oscilloscope probe.
Réunion Electronique pour SLHC
16/11/2009
9
Additional blocs ?

Temperature dependent current source (or voltage source if easier).
 The temperature dependence should have a programmable slope (4 bits or more).
 In the case of a V source the slope should be adjustable between +5mV/C and -5mV/C
 In the case of a current source between +1%/C and -1%/C

An op-amp is already designed and available

Temperature-stable voltage and current references are also available
Réunion Electronique pour SLHC
16/11/2009
10
Additional blocs ?

Temperature dependent current source (or voltage source if easier).
 The temperature dependence should have a programmable slope (4 bits or more).
 In the case of a V source the slope should be adjustable between +5mV/C and -5mV/C
 In the case of a current source between +1%/C and -1%/C

An op-amp is already designed and available

Temperature-stable voltage and current references are also available
Réunion Electronique pour SLHC
16/11/2009
11