Transcript ee222-lect11x

EE222 Winter 2013
Lecture 11
Sung Mo (Steve) Kang
Low power design flow CAD
 Apache
 Cadence
 EPFL
Lecture No.
Date
Subject
Reference
1
Jan 8 (T)
Introduction
Rby-Ch1
2
Jan 10 (Th)
Power, Energy Basics
Rby-Ch3
3
Jan 15 (T)
Circuit level power optimization
Rby-Ch4
4
Jan 17 (Th)
Systems level power optimization
Rby-Ch5
5
Jan 22 (T)
continued
Rby-Ch5
6
Jan 24 (Th)
Interconnects and clock signaling
Rby-Ch6
7
Jan 29 (T)
Memristive computing
Invited lecture-
8
Jan 31 (Th)
Midterm exam
9
Feb 5 (T)
Low power CAS
Rby-Ch8
10
Feb 7 (Th)
Low power CAS
Rbt-Ch10
11
Feb 12 (T)
Ultra low power/voltage design
Rby-Ch11
12
Feb 14 (Th)
Ultra low power/CAD, Sub Vth circuits
Rby-Ch 11, etc.
13
Feb 19 (T)
Project proposal presentation
14
Feb 21 (Th)
High Bandwidth I/O for memory
Invited lecture-
15
Feb 26 (T)
Ultra low power ADC Circuits
Sarpeshkar
Ch15
16
Feb 28 (Th)
Low power RF Telemetry
Sarpeshkar
Ch18
17
Mar 5 (T)
Low power design flows
Rby-Ch12 &
F. Catthoor
18
Mar 7 (Th)
Project presentation
19
Mar 12 (T)
Continued
20
Mar 14 (Th)
Course review
Note
Dr. S. Shin
Prof. C. Kim!
EE222 Peer Review Form
Winter 2013 Quarter
Steve Kang
Evaluator Name______________________________
Title of
Presentation____________________________________
Date _______________________________________
Category
1
Relevance to Low Power IC Design
2
Perceived significance and clarity of
presentation
3
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highest)
EE222 Winter 2013- 5 Projects
1.
2.
3.
4.
5.
Resonant Clock for Energy Recovery
Interconnects for CMOS Topology
Asynchronous Design Techniques
Low Power Computer Architecture
Memristive Memory
F2: VLSI Power-Management Techniques: Principles and Applications
Organizer/Chair: Leland Chang, IBM, Yorktown Heights, NY
Co-Chair: Shannon Morton, NVIDIA, Bristol, United Kingdom
Committee: Ken Chang, Xilinx, San Jose, CA
Leland Chang, IBM, Yorktown Heights, NY
Jin-Man Han, Samsung, Hwasung, Korea
Piero Malcovati, University of Pavia, Pavia, Italy
Shannon Morton, NVIDIA, Bristol, United Kingdom
Vladimir Stojanovic, MIT, Cambridge, MA
Across the spectrum of microelectronics applications, power management is critical to enabling of
power-efficient products. This Forum will provide practicing circuit designers with
a summary of power-management techniques, including perspectives from a wide range of
product applications, and an outlook for the future in the context of coming challenges. The
first four speakers in this Forum will present the general principles in development today, including
power-gating and state-retention modes, PLL/DLL techniques for dynamic frequency
scaling, integrated voltage regulators for dynamic voltage scaling, and low-power signaling.
In the second half, four speakers representing different industry perspectives, including
microprocessors, consumer electronics, microcontrollers and mobile, and DRAM, will utilize
practical case studies to detail current usage of power-management techniques and speculate
on future trends.
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08:20 Introduction
Leland Chang, IBM, Yorktown Heights, NY
08:30 Advanced Power-Gating and State-Retention Approaches to Leakage-Power
Reduction
David Flynn, ARM, Cambridge, United Kingdom
09:20 Clocking Techniques for Dynamic Frequency Scaling
Jaeha Kim, Seoul National University, Seoul, Korea
10:10 Break
10:35 Dynamic Voltage Scaling Using On-Chip Voltage Regulation
Gu-Yeon Wei, Harvard University, Cambridge, MA
11:25 Power Management in High-Performance I/O
Jared Zerbe, Rambus, Sunnyvale, CA
12:15 Lunch
13:20 Fine-Grain Power Management in Microprocessors
Vivek De, Intel, Hillsboro, OR
14:10 A Key to Power Management for Digital Consumer Applications
Yukihiro Urakawa, Toshiba, Kawasaki, Japan
15:00 Break
15:20 Embedded Power-Management Solutions for Ultra-Low-Power SoCs:
Implementation Examples of Radio-Connected Microcontrollers and
Mobile-Application Microprocessors
Frédéric Hasbani, ST Microelectronics, Crolles, France
16:10 Power-Management Techniques in DRAM Design
Sangho Shin, Samsung, Hwasung, Korea
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Apache Ultra-Low-Power Methodology addresses today’s complex SOCs:
RTL Power Analysis, Debug, and Reduction with PowerArtist:
•Understand and lower power consumption early, efficiently, and effectively with a
powerful graphical environment
•Reduce clock, memory and datapath power with a range of sequential and
combinational automatic techniques
•Make reliable early power-related design decisions with power-smart, physicalaware PowerArtist Calibrator and Estimator (PACE™) models
•Track power via regressions throughout the design flow
RTL to Physical Power Integrity with PowerArtist RTL Power Model (RPM™)
•Perform early power grid and package prototyping before chip layout is available
•Increase power integrity sign-off coverage with worst case power cycles rapidly
identified from millions of RTL vectors
•Seamless model-based flow from PowerArtist to RedHawk™ with RPM, and
RedHawk to Sentinel™ with Chip Power Model (CPM™)
APACHE DESIGN SOLUTIONS- ULTRA LOW POWER FLOW
RTL POWER TRADEOFF ANALYSIS
RTL POWER DEBUG AND REDUCTION
RTL POWER
REGRESSION
RTL POWER MODEL
EARLY POWER
INTEGRITY &
PACKAGE ANALYSIS
DESIGN IMPLEMENTATION
POWER INTEGRITY SIGNOFF
█ U LT R A L O W P O W E R C I R C U I T A N D S Y S T E M D E S I G N
Impact of technology scaling on
ultra-low-power systems
Armin Tajalli
Ecole Polytechnique Fédérale de Lausanne (EPFL)
Microelectronic Systems Laboratory (LSM)
December 2009
LSM Group Meeting
44/18
Motivation
• Technology scaling
– Main issues in ULP:
• Variation / reliability
• Leakage / Energy consumption
– Goals:
• Study / analyze
• Explore limitations
• Propose design methodology
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
45/18
Main Concerns in ULP
• Primary issue: energy consumption
• Secondary issue: delay/speed
• Figure of merit: PDP, ED, etc
• Optimal point
– VDD(OPT)
– Emin
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
46/18
Subthreshold Operation
• VDD(OPT) :
– depends on activity rate
– depends on device parameters (VT, DIBL, n,
etc)
– is generally less than VT
• Subthreshold operation:
– Variability
– Leakage
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
47/18
Reliability Metric: Noise Margin
• Limited by:
– DC gain
– VDD
– Variability
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
48/18
NM
• Precise value of NM:
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
49/18
Noise Margin
• Drain current in subthreshold:
• Maximize NM ( XC = VDD/2 ):
• Calculate VTC :
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
50/18
Noise Margin
• Gain drop due to DIBL
• NM including variation
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
51/18
Noise Margin
• Comparing to transistor-level simulations
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
52/18
Noise Margin
• NM vs ION/IOFF
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
53/18
Noise Margin
• Positive NM:
• Equivalently:
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
54/18
High-VT
• Lower VDD
– Less dynamic and static dissipation [+]
– Less noise margin [-]
– Sensitive to variation [-]
• High-VT
– Less static power dissipation [+]
– No effect on noise margin [+]
– Exponential increase in delay [-]
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
55/18
Noise Margin
• Positive NM:
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
56/18
Energy Consumption
• Including:
– activity rate
– leakage
– logic depth
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
57/18
Energy Consumption
• Critical activity rate:
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
58/18
Discussion
– Scaling rules in subthreshold/ULP are different
– A combination of size/VDD scaling is required to keep
energy consumption very low
– Critical device parameters in ULP: DIBL, ION/IOFF, S
– Use high-VT instead of lower VDD if delay is not a
concern !
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
59/18
Case Study
• Example 1.
Impact of technology scaling on ultra-low-power
systems ● Armin Tajalli ● EPFL LSM ● December
2009
SUBTHRESHOLD SOURCE-COUPLED CIRCUITS