Transcript EE201C : Stochastic Modeling of FinFET LER

EE201C : Stochastic Modeling of FinFET LER
and Circuits Optimization based on Stochastic
Modeling
Shaodi Wang
004033643
Outline
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Stochastic modeling of FinFET LER
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Stochastic modeling based circuits optimization
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22nm FinFET circuits optimization
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Conclusion
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Devices Variability
Line Edge Roughness (LER)
 LER is the main variability in FinFET
Gate Dielectric Thickness (Tox)
Random Dopant Fluctuations (RDF)
Metal-gate Work Function (WFV)
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Line Edge Roughness
Stochastic
Consequence of Lithography processing
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LER vs. LWR
Line width roughness (LWR)
n

2
LWR

L  L 
i 1
2
i
N 1
2
 LWR
  L2   R2  2 X  L R
 L   R   LER
2
2
 LWR
 2 LER
1   X 
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Correlation
Resist-defined
X  0
Spacer-defined
X  1
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Correlation
2

 A  exp   y /   


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Gate LER and Fin LER
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Gate LER Affection
Fin LWR affects device performance by changing the
average Fin width in the channel region.
Gate LWR induce the FG and BG mismatch and offset.
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Stochastic modeling of Gate LWR
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Stochastic modeling of Gate LWR
 2L   12   22   32   42  2 14 1 4
2  23 2 3  2 12 1 2  2 34 3 4
2 13 1 3  2 24 2 4
Resist Forming Gate:
Spacer Forming Gate:
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Experimental grids are established
 P  2  P  2

  L  
 
 L 
  
2
 P2 , g
2
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Result
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Results
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Results
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Results
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Outline
Stochastic modeling of FinFET LER
Stochastic modeling based circuits optimization
22nm FinFET circuits optimization
Conclusion
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Stochastic Circuits Optimization
Performance vs. scaling
Power vs. scaling
 Leakage Power
 Dynamic Power
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Optimization methodology
Stochastic timing analysis
 Instead of static timing analysis
Every path can be critical path
 Every path has a probity to become a critical path
 The given yield to constrain the clock frequency
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Optimization process
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Models:
Power Model
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Models
Delay model
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Models
Devices model depends on different devices.
 MOSFET
 SOI
 FinFET
Devices simulation results
 Output from Spice, etc.
Empirical fitting model
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Tolerance modeling
Process variation
 LER
 RDF (Not important for FinFET)
 Intra-die, inter-die and across-die variation
Supply voltage variation
 Vdd and Ground noise
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Tolerance modeling
Variation affection
Example: Vt shift and follows a Gaussian distribution
 Delay distribution:
• One stage delay: N ( 0 ,  0 )
• N stage path delay: N (n 0 , n 0 )
 Average Off Current:
• Assume Ioff follows Gaussian distribution
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Tolerance modeling
Given a clock period tCK
 Each path has a delay distribution. Delay over tCK results failure.
 The total yield:
Given the yield and reverse the equation to solve tCK.
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Thermal modeling
Temperature dependence
 Subthreshold leakage
 Mobility model
 Wire resistance model
 Heat-sink model
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Results
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Results
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Defects
This works contribute the process variation into the Vt
variability. However, the device performance variability
cannot be easily appropriately modeled by Vt.
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Outline
Stochastic modeling of FinFET LER
Stochastic modeling based circuits optimization
22nm FinFET circuits optimization
Conclusion
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FinFET variability
The FinFET is 22nm technology.
 The thin channel suppresses short channel effects.
 Low doping makes RDF affection lower.
 The restriction of Tox is released.
 LER become the important process variation.
 Voltage supply noise is still a problem
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FinFET optimization based on Stochastic modeling
FinFET Device LER Simulation
Principle component analysis on
FinFET LER results
Fitting model to FinFET behavior
Transfer the principle component from
device LER
to model parameters
Circuits performance variability is
done based on model
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FinFET optimization based on Stochastic modeling
FinFET 3-D LER MC simulation is done based on sentaurus
TCAD tool.
 Non-variation current behavior is obtained. ( Works in model
fitting)
 Key parameters are obtained
•
•
•
•
Threshold voltage
Saturation voltage
Ion current
DIBL
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FinFET optimization based on Stochastic modeling
Principle component analysis performed on device LER
results
 Calculate the covariance matrix of the results of FinFET.
• Covariance matrix:
Cov(a1,a1)
Cov(a2,a1)
Cov(a3,a1)
Cov(a4,a1)
Cov(a1,a2)
Cov(a2,a2)
Cov(a3,a2)
Cov(a4,a2)
Cov(a1,a3)
Cov(a2,a3)
Cov(a3,a4)
Cov(a4,a3)
Cov(a1,a4)
Cov(a2,a4)
Cov(a3,a4)
Cov(a4,a4)
 Calculate the eigen vectors and eigen values
• Eigen vectors
Eigen value
• These eigen vectors are independent
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FinFET optimization based on Stochastic modeling
Calculate the sensitive vectors of devices key behavior
parameters to model parameters.
 My model has 9 parameters. This sensitive vectors are the 4
devices key parameters’ derivation to 9 parameters of model
D1
M 1
D2
M 1
D3
M 1
D4
M 1
D3
D1
D2
D4
Sen  M 2 M 2 M 2 M 2
    
D1
M 9
D2
M 9
D3
M 9
D4
M 9
Calculate the principle components in emperical model
PCAmod el * Sen  Eigen _ vectorsDevice
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FinFET optimization based on Stochastic modeling
Variability model in my work
 LER Variation
• Based on PCA, I used 9 parameters in the model to represent the LER
variability. ( Ion, Ioff, Vt, CLM, Vtsat, Vt,lin …)
 Voltage supply variation
• I model this into the supply voltage Vdd variability.
 Across-die, inter-die and intra-die variation
• I model this by threshold voltage variability
 All of these 3 variation are independent
Model delay variability
 Based on MC simulation.
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FinFET optimization based on Stochastic modeling
Optimization process
 Given the restriction ( Power and Yield)
 Outer loop : optimized parameters ( Vt, W and etc)
 Inner loop : optimized parameters (Vdd)
 In each one of the all loop:
• 100 samples MC performed to get the distribution of one stage Delay.
• Based on the given Yield, using iteration to find the chip clock
•
•
frequency.
Calculate the total power, the power must < Power restriction.
Choose the fast clock in given Power restriction.
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FinFET optimization based on Stochastic modeling
Optimization Results
 Optimized Block : Gate 5000, longest path 22 stages.
Clock Period (ps)
1000
Delay vs. Power
Block: 5000 Gates
100
5E-5
5E-4
0.005
Total Power(W)
0.05
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Conclusion
LER is one of the important variability in FinFET
technology.
As power restricts devices scaling, circuits optimization
becomes an important process to reduce power.
FinFET circuits optimization is done by considering LER,
supply voltage, process variation.
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Reference
Kedar Patel, et all, “L. I. Smith. “A Tutorial on Principal
Components Analysis”. Cornell University, USA, 2002. ”,
IEEE Transactions on Electronics Devices, vol. 56, no. 12,
Dec. 2009.
L. I. Smith. “A Tutorial on Principal Components Analysis”.
Cornell University, USA, 2002.
D. J. Frank, et all, “Optimizing CMOS technology for
maximum performance” , IBM J. RES & DEV. vol.50, no. 4/5,
2006
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