Best case in reading

Download Report

Transcript Best case in reading

Click to edit Master title style
STT-RAM Circuit Design
Column Circuitry Simulation
(IBM 45nm SOI)
Fengbo Ren
Summary
 Use floating body device as access transistor won’t degrade effective
TMR as long as we perform pre-charge in reading operation.
 The bipolar current (due to the floating body) will appear at the beginning
of writing operation. It should be not enough to be destructive (12uA/um,
last for 80 ps).
 Min. cell size can be achieved is 17F2 (F=0.095 um). For min. cell size,
I_W(P->AP)=645 uA, I_W(AP->P)=415 uA. More write current than 65-nm for the
same cell size.
 Use NMOS-only-MUX results in 15-20% write current degradation.
 Still working on how to do reliable short pulse reading.
2
Body contacted (BC) v.s. floating body (FB) device
 Choosing device for access transistor
– Best available BC device has 2x worse drive strength as
compared to FB device, it also has body contact making it
really big.
FET Name
Regular-Vt floating body NFET
Analog body contacted NFET
Idsat (uA/um)
1229
687
Area (for same I)
1
5
– In the interest of area, it is better to use FB device, but FB
device has variation on RMOS depending upon Vbody (can
range from 0-0.65V in our design), the following slide will
analyze how this will affect the effective TMR.
3
Effective TMR
 Some definition
TMR = (RAP-RP)/RP
Effective RP (RP_Eff) = RP+RMOS1
Effective RAP (RAP_Eff) = RAP+RMOS2
Effective TMR = (RAP_Eff-RP_Eff)/RP_Eff
_BC: body connected case
_FB: floating body case
Effective TMR (%)
–
–
–
–
–
–
100
Effective TMR when TMR=125%
90
120
80
100
70
80
60
60
50
40
40
20
30
0
50
20
40
30
 Best case in reading
20
2
Cell Size (F )
0
500
1000
1500
2000
Rp (Ohm)
– Vbody >> 0 and are same when reading RP and RAP
– RP_Eff_FB < RP_Eff_BC, RAP_Eff_FB < RAP_Eff_BC,
 Worst case in reading
– Vbody = 0 when reading RP, Vbody >> 0 when reading RAP
– RP_Eff_FB = RP_Eff_BC, RAP_Eff_FB < RAP_Eff_BC
4
Effective TMR when body is floating
 Best case improve effective TMR a little bit
 Worst case degrade effective TMR by 5-6%
 For our reading circuit, BL and SL are always pre-charged to the same
voltage level. So, Vbody should always be the same (somewhere between VDD
and VSS) regardless of MTJ resistance. Therefore, by performing pre-charge,
we are always in the best case, which means using FB device won’t degrade
TMR in our design.
5
Bipolar Current (FB device)
 When g = 0, d = 1, s = 1-> 0, since body is floating

(Vbody>>0), we have bipolar current (Ibipolar).
In our design, this current will be seen at
the beginning of writing operation.
Bipolar current at the beginning of
writing operation
Ibipolar has a peak of 12 uA/um and last for 80 ps, which should be not enough to
accidentally flip MTJs. In our design we have 128 WLs, the peak of Ibipolar_total will
be around 1.5 mA, a high but short current pulse.
6
Min. Cell Size

– W = 434 nm
– L = 40 nm
Cell size:
– 0.154 um2
– 17 F2
● Feature size: 0.095 um
 From 65 -> 45nm
– Metal pitch
● 0.2 -> 0.19 um (M4)
● 0.2 -> 0.14 um (M1)
Note: This is the min. cell size can be
achieved without violating design rule.
0.405 um
0.38 um
 Transistor size:
– Transistor pitch
(D/S shared)
● 0.5 -> 0.38
7
Cell Size v.s. Write Current
Boosted VDDW
 Rp = 700 Ohm, TMR = 125%
 Boost up VDDW, VWL
BL
– dual VWL (VWL_P , VWL_AP)
S’
VBIAS
2
17
Transistor
W (um)
IWP (uA)
IWAP (uA)
S
Cell Size (F , F=0.095 um (C1))
20
25
30
35
Boosted dual VWL
40
0.43
0.57
0.81
1.05
1.29
1.52
645
415
789
452
982
492
1100
513
1220
535
1270
547
“1”
“0”
S’
S
SL
VBIAS
 Recall 65-nm
Cell Size (F2)
35
40
27.75
30
45
50
Transistor W (um)
0.75
0.84
1.04
1.24
1.44
1.64
IWP (uA)
723
779
884
972
1040
1090
IWAP (uA)
410
422
443
458
471
480
8
Using NMOS only in MUX
 Mux size W
– NMOS: W
– PMOS: 2W
Using NMOS only in MUX will result in
15-20% write current degradation for P>AP, 10-15% degradation for AP->P.
The main reason causes the degradation
is that the VGS of the NMOS that close to
VDD will be very low during the write
operation (Shown in green in the
bottom Fig. ), in which case we need a
PMOS. So, simply increasing the size of
NMOS won’t help.
9
Read
 Normal X-INV based reading
– Monte Carlo, TMR=125%
Rp (Ω)
500
750
1000
Read time (ps)
60~160
80~160
120~270
 Still working on how to do reliable short pulse reading.
– No positive result yet.
10