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BTDS52
ISM RF/IF DUAL BAND SYNTHESIZER
May 2005 Preliminary
The BTDS52 is a high-speed Direct Digital Synthesizer
(DDS) with a frequency tuning resolution of 32 bits and
an amplitude resolution of 10 bits. Sine waves in the
1st Nyquist band can be generated up to near 1.25
GHz (at a 2.5-GHz clock rate). The initial phase can be
reset to zero degrees which is 90 degree offset from its
complementary part BTDS52Q. Co-use of the pair
BTDS52 and BTDS52Q can generate signal sources
with 90 degree offset I/Q phases. The chip has a pair
of complementary outputs with 50Ω back terminations.
The frequency of output waveforms can be controlled
by thirty-two frequency control bits, Vi0 ~ Vi31. The
BTDS52 accepts either complementary clock inputs or
a single-ended clock input and features 50Ω on-chip
back terminations with user-defined threshold. The
frequency resolution bits accept TTL or CMOS input
levels. Only a single -5.2V power supply is required.
Major Applications
•
32-bit frequency tuning word
•
On chip DAC with 10 bit linearity
•
Clock rate up to 2.5 GHz
•
Sine wave generation up to 1.25 GHz
•
Complementary analog waveform
outputs with 50Ω back terminations
•
Carry bit RF output from phase
accumulator for synchronization
triggering of testing scope or system
applications
•
Worst SFDR > 50 dBc (DC to 1.25-GHz
Bandwidth) at a 2.5 GHz clock rate
•
TTL/CMOS digital pattern control input
•
Reset (RST) pin to initiate phase 0
starting state
•
High speed strobe LVPECL or LVDS
compliant inputs (STRP/N) to change
DAC output frequency
•
High speed strobe inputs allow
BTDS52 to be controlled by microcontroller or DSP chips for real time
chirping function
•
Frequency update rate as fast as 16
clock cycles (with 8 clock cycles as
option)
•
3.7 W power consumption with a
single -5.2V power supply
•
64-pin QFN package
•VHF/UHF LO synthesis
•Tuners
•Instrumentation
•Agile clock synthesis
•Cellular base station hopping synthesizer
•Radar
•Sonet/SDH clock synthesis
BTDS52
For more information,please contact us at:
© 2005 BrillianceIC Corporation. All rights reserved.
DongHai Wang
Tel: 010-82602116 13693354034 (China Beijing)
e-mail: [email protected]
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BTDS52
ISM RF/IF DUAL BAND SYNTHESIZER
May 2005 Preliminary
Functional Block Diagram
PACKAGE DIMENSION AND PIN ARRANGEMENTS
•Unit: mm
•Package Format: 64-pin QFN
•Package Size: 9 mm x 9 mm
•Pin Pitch: 0.5 mm
BTDS52
For more information,please contact us at:
© 2005 BrillianceIC Corporation. All rights reserved.
DongHai Wang
Tel: 010-82602116 13693354034 (China Beijing)
e-mail: [email protected]
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BTDS52
ISM RF/IF DUAL BAND SYNTHESIZER
May 2005 Preliminary
Electrical Specifications:
VEE = -5.2 V and RL = 50 Ω (for DAC RF Outputs )
BTDS52
For more information,please contact us at:
© 2005 BrillianceIC Corporation. All rights reserved.
DongHai Wang
Tel: 010-82602116 13693354034 (China Beijing)
e-mail: [email protected]
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BTDS52
ISM RF/IF DUAL BAND SYNTHESIZER
May 2005 Preliminary
Theory of Operation
The BTDS52 core consists of a 32-bit accumulator, a sine wave look up table in the form of a ROM,
and a 10-bit Digital to Analog Converter (DAC). The 32-bit accumulator is a phase accumulator,
where the 32 frequency control bits are latched and added to the previous output of the
accumulator at each clock cycle. The accumulator output stores the phase of the output waveform
of the chip. Sine wave generation requires the phase from the accumulator be passed to a ROM to
look up the appropriate amplitude for the waveform. To save on size the ROM only stores the first
quadrant of sine wave data. To form the full pattern the two most significant bits of the phase are
used with the first quadrant data to generate the full sine wave. The final 10-bit digital outputs of
the ROM are passed to the DAC stage to synthesize the sine waveform. The DAC employs R-2R
ladders and segmented architecture to improve linearity and reduce output glitches. The 21 current
sw itc hes a re a ll diffe r e ntia l to prod uce a c omplementa r y pa ir of outp ut signa l s .
All 10 data bits of the digital outputs of the ROM are re-latched with the same clock edge, providing
a uniform setup time for the DAC stage. Then the 4 MSB bits are decoded into fifteen lines. The
decoding employed reduces output glitches and improves dc linearity. The remaining 6 LSB bits
(D0-D5) are passed on unchanged. The clock latches all 21 lines again. The latched data controls 6
and 15 current switches respectively to produce the analog outputs. The four MSB bits control 15
identical current switches, while the six LSB bits control 6 current switches connected through an R2R ladder. The output signals should be connected with 50Ω terminations to ground. Once
terminated each output will produce a 600 mV full-scale voltage range. The differential outputs can
be combined with a broadband balun to achieve 1.2V single ended output with the even-order
harmonics suppressed to certain degree.
For more information,please contact us at:
© 2005 BrillianceIC Corporation. All rights reserved.
DongHai Wang
Tel: 010-82602116 13693354034 (China Beijing)
e-mail: [email protected]
BTDS52
The state of the accumulator can be reset to zero when RST is set to voltage higher than 2.5V. This
has the effect of setting the initial phase of the sine wave to zero. In normal operation RST should
be set at 0V. When the accumulator overflows, a carry output bit is propagated to COUT. COUT has
a 250Ω back termination with 4 mA current sink. The COUT signal can be very useful to trigger or
synchronize the DDS outputs with other chips, functions or equipments in the system. A pair of
complementary clock inputs with 50Ω terminations to VTT are provided. VTT acts as the logic
threshold and can be set by the user. Once the 32 parallel frequency control data input bits Vi_0 ~
Vi_31 are settled at the input pins, the high speed strobe pulse (STRP/STRN) will latch ( at the
negative transition edge) the 32 data input bits into accumulator and initiate new frequency signal
at the DAC outputs. The phase of output signals will be continuous between the two output
frequency signals before and after the strobe pulse. This high speed strobe feature allows BTDS52
to be controlled by microcontroller or DSP chips for real time chirping function.
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BTDS52
ISM RF/IF DUAL BAND SYNTHESIZER
May 2005 Preliminary
ABSOLUTE MAXIMUM RATINGS . WITH NEGATIVE SUPPLY VOLTAGE:
TYPICAL OPERATION CONDITIONS . WITH .5.2 V SUPPLY VOLTAGE :
For more information,please contact us at:
© 2005 BrillianceIC Corporation. All rights reserved.
DongHai Wang
Tel: 010-82602116 13693354034 (China Beijing)
e-mail: [email protected]
BTDS52
Note 1: AVS pin can be left open as default and the corresponding output swing is 600 mVPP.
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BTDS52
ISM RF/IF DUAL BAND SYNTHESIZER
May 2005 Preliminary
TERMINAL DESCRIPTION:
TYPICAL CONNECTION:
VEE
Output
Swing Control
C2
C3
NOTES:
C4
•VCC.s and VCCA.s are
connected to ground
Accumulator
Carry Out
T1
Monitoring
Accumulator Reset
VCC
VCC
VCCA
VEEA
VCCA
VEEA
VCCA
VEED
VCCA
AVS
VCSB
VCC
N/C
EXN
VEE
VCSM
C2
VCSU
OP
COUT
VCCA
RST
ON
VEED
VCC
T7
T6
}
Complementary
Analog Outputs
VEE
N/C
Vi31
Vi30
STRP
T5
Vi28
STRN
T4
Vi27
CKN
T3
Vi26
VTT
Vi25
CKP
Vi24
Vi0
Vi23
Vi1
For more information,please contact us at:
Vi4
Vi5
Vi6
Vi7
Vi8
Vi9
Vi10
Vi12
Vi11
Vi13
Vi14
Vi15
VEE
Vi16
Vi20
Vi17
Vi3
Vi18
Vi2
Vi21
Vi19
Vi22
T2
}
Strobe Inputs
}
Complementary
Clock Inputs
•Center Pads of the
package are connected
to ground
•T1~T7: 50 Ω
transmission lines
•C1~C3: 100-nF
surface mount
capacitors
•C4: a 10-uF capacitor
on the power trace
© 2005 BrillianceIC Corporation. All rights reserved.
DongHai Wang
Tel: 010-82602116 13693354034 (China Beijing)
e-mail: [email protected]
BTDS52
Vi29
•VEE.s and VEEA.s are
connected to power
supply -5.2 V
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BTDS52
ISM RF/IF DUAL BAND SYNTHESIZER
May 2005 Preliminary
MEASUREMENT RESULTS:
RF Spectrum
The RF performance was characterized by the setup as shown in the following figure. In the setup,
frequency scanning was controlled by a PC computer with National Instruments DAQ interface card which
was connected to the BTDS52 through a 64-pin ribbon cable. The analog output was measured by a
spectrum analyzer.
PC
With NI DAQ
interface
IDC
Adaptor
BTDS52
EV Board
Clock Source
GPIB
BUS
The following figures show typical SFDR versus signal frequency at clock rates of 1.0 GHz, 1.6 GHz and
2.0 GHz respectively. The SFDR was derived based on the difference of the single-ended signal output
and the highest (or the 2nd highest) spur between DC and 0.5 * fclk (i.e the whole 1st Nyquist band)
without filtering. The highest spurs (data in red) are 2nd harmonics related spurs for each output
frequency. These 2nd harmonic related highest spurs can be reduced by converting the differential
outputs into singleended output with a broadband balun.
BTDS52
For more information,please contact us at:
© 2005 BrillianceIC Corporation. All rights reserved.
DongHai Wang
Tel: 010-82602116 13693354034 (China Beijing)
e-mail: [email protected]
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BTDS52
ISM RF/IF DUAL BAND SYNTHESIZER
May 2005 Preliminary
BTDS52
For more information,please contact us at:
© 2005 BrillianceIC Corporation. All rights reserved.
DongHai Wang
Tel: 010-82602116 13693354034 (China Beijing)
e-mail: [email protected]
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BTDS52
ISM RF/IF DUAL BAND SYNTHESIZER
May 2005 Preliminary
The following spectra were measured at a clock rates of 1.0 GHz, 1.6 GHz and 2.0 GHz. For each clock
rate, the left figure shows the spectrum of output signal frequency equal to 1/3 of clock rate. The right
figure shows the spectrum of output signal frequency equal to 3/8 of clock rate which is the typical worst
case condition and the highest and the 2nd highest spurs correspond to 2nd and 3rd harmonics aliasing
back into the Nyquist band.
BTDS52
For more information,please contact us at:
© 2005 BrillianceIC Corporation. All rights reserved.
DongHai Wang
Tel: 010-82602116 13693354034 (China Beijing)
e-mail: [email protected]
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BTDS52
ISM RF/IF DUAL BAND SYNTHESIZER
May 2005 Preliminary
BTDS52
For more information,please contact us at:
© 2005 BrillianceIC Corporation. All rights reserved.
DongHai Wang
Tel: 010-82602116 13693354034 (China Beijing)
e-mail: [email protected]
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