Transcript lowfrequency

Low frequency measurement done at the pit
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The scope was connected to an ECAL coax through a gain 10
Lecroy amplifier
The scope bandwidth was reduced to 20 MHZ
The first 4 measurements are done with the CW on
On the next 3 measurements HV is off and Agilent off but the +6 volts is on
The last measurement is with the entrance of the Lecroy
disconnected from the ECAL coax
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The CW noise with present base:slow part ±300volt
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20ms scale :the 50Hz is about ±120volt
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CW noise with only ±6volts on bases!
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Lecroy+scope noise < ± 50 volt
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Noise in lab
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The set up used is the line with 40 PMT 20 with ECALmc 20
HCALmc one of the HCALmc is a base with 10K resistance
instead of 5.6K in serie with the CW chain
The High voltage on the bases is 800 volts
To see well the CW noise the Lecroy gain 10 amplifier is used in
AC mode with frequencies < 30KHZ killed except in tek00003
and 00005 which are used to measure the 50HZ pick up noise
1 2 3 are with ECALMC base
4 5 are with HCAL mc with 5.6K
6 7 8 are HCALmc with 10K
9 and 10 are again HCALmc with 5.6K
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ECALmc bases(1)
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ECALmc bases(2)
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ECALmc bases(3)
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HCALmc (5.6K)-1
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HCALmc 50Hz measurement but may be ≠ pit
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HCALmc(10K) -1 solution to be mounted
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HCALmc(10K)-2 shows fast part about 200ns
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HCALmc(10K)-2 shows fast part about 200ns
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HCALmc (5.6K)-3 shows faster pulse vs 10K
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HCALmc (5.6K)-4 shows faster pulse vs 10K (100ns)
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Analysis-1
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ECALmc and HCAMmc are not really different. HCALmc with
10K has a slightly lower pick up voltage from CW but over a longer
time. In the fast electronic with the dynamic pedestal subtraction
this reduces the noise seen, since the pedestal subtraction is
equivalent to a differentiation with a 25 or 50 ns deltaT.
Focusing on the HCALmc 10K results:
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The measured CW noise measured with the present fast electronic is about
0.2 ADC count which corresponds to 4 femtoCoulomb (fC)
Without dynamic pedestal subtraction the 50Hz noise is about ±150 volt
max => ± 75fc => a rms of about 43fC ; At the pit perhaps smaller ±120 volt
and rms of 35fC
The peak CW noise pulse is about 240 volt with a triangular shape which
last 1 microsec over 8 microsec half period. Without dynamic pedestal
subtraction one can compute an rms of 24fC. Peak is about 120fC.
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Analysis 2: impact on upgrade electronic
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At present the calibration is 20fC = 2.5 MeV of Et . Because of the
increase of anode current at 1033 the calibration may have to
become 20fC = 12.5 Mev of Et => 5ADC count (Frederic talk)
Unsubtracted 50Hz or CW rms noise would become 9 and 6 ADC
counts!!!
If a pre-amplifier (X10?) is used on FEB it has to have a good 50
ohm termination and a noise of < 4fC which can be obtained with
1nv/√Hz (? To be checked!) . Since dynamic pedestal subtraction
has to be used AC coupling can be used and baseline shift
corrected by pedestal subtraction.
If a scheme similar to the present ECAL/HCAL Feb is used, and
the present pedestal subtraction, the CW noise would contribute
about 1 ADC count. In a switch system with 2 pedestal =>2ADC
count? (measurement to be done)
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Further test
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Measure linearity for a PMT with reduced gain. => if instead of
240 pC max charge the range is 50 pC maximum charge there
is chance of better linearity => test to be done by Bernard Jean
Marie in 3 weeks with a Lecroy amplifier.
Register a nonsubtracted noise over n samples (5? 7?) to verify
effect of different dynamic pedestal subraction on CW noise
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4 Possible solutions
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Discrete components solution : no Asic
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Preamp Op Amp gain 10 ultralow noise.
+ and - output made with another Op Amp
Delay line system
Op Amp integrator with 2.5 microsec time constant
Total: 3 Op Amp +ADC +delay line
Same delay line system but with ASIC preamp with +- output
Delay line system. Asic includes the integrator delay line output
goes out and in.
No delay line => Asic includes preamp + integrator with
switches
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Pro and cons
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The switch solution
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Con: a very large pedestal (stability?)
Larger dynamic pedestal subtraction
Pro: the most fully integrable
Perhaps we could use a 4 channel ADC with only one clock?
Delay line solution
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Con: the delay line is not integrable , even the out-in solution is not
simple from the point of view of impedance choice
More components
Pro: may be possible without ASIC => less R&D => more time
Natural small pedestal (AC coupling)
Lower CW noise if dynamic pedestal OK
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Other problems (later?)
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How to replace the delay chip?
Signal treatment on board or on TELL 40
Local DAQ for test?
Fiber driver: common mezzanine or specific?
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