HK connections - Euso
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Transcript HK connections - Euso
HK & LVPS for EUSO –TA / -Balloon
G. Medina-Tanco, L. Santiago, H. Silva Lopez,
F. Trillaud, C. Lopez, J. Rojas,
A. De la Cruz, S. Guerrero, G. Leon
HK connections
CPU
RS422
RS422-RS232
converter
SIREN
CCB
CLKB
SPI
GPS
PDMB
HOUSE KEEPING
HVPS
High Level Command
&
Monitoring Signals
Analog to Digital
Conversion
4 LVPS [4 Mon, 3 HL_Cmd]
SIREN [1 Open Drain output]
LENSES
HK connections
CPU
Of course not
needed in TA, but
still available
comm-channel if
comm with TA or
independent
remote access is
required
RS422
RS422-RS232
converter
SIREN
CCB
CLKB
SPI
GPS
PDMB
HOUSE KEEPING
HVPS
High Level Command
&
Monitoring Signals
Analog to Digital
Conversion
4 LVPS [4 Mon, 3 HL_Cmd]
SIREN [1 Open Drain output]
LENSES
Who turn HK on now?
Anyway same protocol
must be kept for HK
On/Off.
HK Interfaces
HK module
Individual boards’ functionality:
PCB 05: LENSES, LVPS-PDM, LVPS-HK: (DC25-DB25).
PCB 04: LVPS1-DP, LVPS2-DP: (DC37-DB25).
PCB 03: SIREN-HK, CPU-HK, PDM-HK (DE9-DE9-DA15).
PCB 02: CCB-HK, CLKB-HK: (DB25-DB25).
PCB 01: POWER-HK, GPS-HK, HVPS-HK: (DE9-DA15-DA15).
HK module
Back-lid
(profile from Giuseppe’s module/CAD)
produced @ CCADET-UNAM
HK
LVPS
HK production status
Two HK’s were produced
Currently 3 students from UNAM are at Naples for HK+LVPS integration with DP
Duration of mision 3 weeks
Module casing: delay of 3 days at production will arrive next week by DHL
HK module boards & Arduino
HK module boards & Arduino
HK Software
HK Software
• Software related to DP
interfaces will be
advanced during DP
integration.
• HVPS we have a channel
open & should not be a
problem.
• PDMB there is nothing
defined yet.
LVPS
LVPS System: 4 boards implemented in 4 separate modules in DP rack
Individual boards’ functionality:
LVPS-PDM:
LVPS1-DP:
LVPS2-DP:
LVPS-HK:
PDMB
CCB, CLK, GPS
CPU (& DS)
HK
[ON/OFF: HK]
[ON/OFF: HK]
[ON/OFF: HK]
[ON/OFF: SIREN]
CURRENT Boards: input 28V NOT 110V
But 110 V are AC not DC, yes?
So, No-break/batteries in between ? WHO do this?
LVP consumption
Interface
LVPS-PDM
Current TA
board does
not work
with PDM if
those values
for PDM are
final
IR Camera
High Voltage Power
Supply
LVPS DP1
LVPS DP2
Housekeeping
LVPS-PDM
LVPS-HK
CPU
CCB
Data Storage
GPS
CLK
PDMB (FPGA)
PDMB-EC-ASIC
Additional Spare
Heaters
Total
Power Consumption
in W
for Power Pack1
Power Consumption
(changes)
Power Consumption
in W
for Power Pack2
22
2
2
3.3
4.2
6
3.5
1.6
12
5
8
1
3
7.2
10
3.3
4.2
6
3.5
1.6
12
5
8
1
3
8
10
15
15
TBC
81.8
But still the margin of tolerance must be confirmed
because it is too low: < 2%
88.6
22
CONNECTORS ON LVPS_PDM FRONT PANEL
128.4
101.7
24.33
53.04
12.55
DB25
(HK_BOARD)
DE9
(PWR_PDMB)
4.65
10
(BATTERY)
30.81
10.39
Dimensiones en mm
0.36
DE9
6.9
12.55
26.2
19.3
50.5
0.36
92.4
Área efectiva enmarcada por línea azul
0.36
CONNECTORS ON LVPS2_DP FRONT PANEL
128.4
101.7
24.33
12.55
DB25
(HK_BOARD)
DA15
DE9
(PWR_CPU)
10
4.65
(BATTERY)
6.9
12.55
26.2
19.3
50.5
0.36
39.14
6.22
6.22
92.4
Dimensiones en mm
Área efectiva enmarcada por línea azul
0.36
CONNECTORS ON LVPS_HK FRONT PANEL
128.4
101.7
10.87
10.87
DA15
DE9
26.2
(HK_ON/OFF)
(BATTERY)
19.3
10
DE9
(HK_MON)
4.65
DE9
10
(PWR_HKB)
6.9
50.5
0.36
92.4
10.39
Dimensiones en mm
Área efectiva enmarcada por línea azul
0.36
CONNECTORS ON LVPS1_DP FRONT PANEL
En esta opción se le agregaron lo de 3
divisiones = 5.08x3 = 15.24
128.4
101.7
69.32
16.19
16.19
DC37
(HK_BOARD)
41.44
12.55
0.94
DE9
(CCB)
34.54
65.74
12.55
0.94
DE9
10
(BATTERY)
DE9
DE9
(CLKB)
(GPSR)
4.65
30.81
6.9
12.55
0.94
30.81
92.4
Dimensiones en mm
Área efectiva enmarcada por línea azul
0.94
CONNECTORS ON LVPS_HK FRONT PANEL
Agregar una subdivisión mas a los otros 3 submódulos sería otra opción = 50.5+5.08=
55.58
128.4
39.14
10.87
101.7
10.87
12.55
31.28
DA15
DE9
(HK_ON/OFF)
(BATTERY)
24.38
10
4.65
DE9
(HK_MON)
10
(PWR_HKB)
30.81
92.4
10.39
Dimensiones en mm
2.06
DE9
6.9
12.55
55.58
2.06
Área efectiva enmarcada por línea azul
2.06
LVPS production status
1 LVPS set was produced
LVPS-PDM
PDM – Low Voltage Power Supply Board
Battery connector
Power connector
(to load)
DC-DC of FPGA-PDM
Latching Relay of EC-ASIC
DC-DC of EC-ASIC
HK connector
Latching Relay of PDM
Monitoring circuit
(4 Operational
amplifier built-in chip)
DC-DC to power
monitoring circuit
HK – Low Voltage Power Supply Board
Battery connector
Power connector
(to load)
Latching Relay of 12V-HK
SIREN connector HK connector
for Commands
Latching Relay of 3.3-HK
Dual output DC-DC for
±12V-HK
DC-DC for 3.3V-HK
Monitoring circuit
(4 Operational
amplifier built-in chip)
DC-DC to power
monitoring circuit
DP – Low Voltage Power Supply Board #1
Battery connector
DC-DC for CCB
Latching Relay of CCB
Power connectors
(to load)
To CCB
To CLKB
To GPSR
HK connector
DC-DC for CLKB
DC-DC for GPSR
Monitoring circuit
(6 Operational
amplifier TWO chips)
Latching Relay of CLKB
DC-DC to power Latching Relay of GPSR
monitoring circuit
DP – Low Voltage Power Supply Board #2
Battery connector
DC-DC for CPU
Power connector
(to load)
HK connector
DC-DC to power
monitoring circuit
Latching Relay of DST
DC-DC for DTS
Monitoring circuit
(4 Operational
amplifier built-in chip)
Latching Relay of CPU