Transcript Regev - Guidelines for DFT

Guidelines for Chip DFT
Based on Boundary Scan
Reference to an article by Ben Bannetts
By Regev Susid
Specify 1149.1 Compliance
It is important for all the devices to be
100% compliant with the 1149.1 standard.
The optional functions should also be included:
• IDCODE – Reading the ID of the device.
• CLAMP – Scanning the cell data into the output.
• HIGHZ – Outputs a High-Z state.
And also to add the TRST.
BSDL (Boundary-Scan Design
Language)
The device’s design should be done according to the
BSDL.
It is also extremely important to check the BSDL thoroughly
In both syntactically and semantically (some commercial
Checkers are available like ASSET etc’)
The last part of checking the BSDL is to compute 1149.1
conformance tests and to apply them to a device.
Assigning IO and OZ Control Cells
Using Bidirectional (IO) and three-state (OZ) pins is
recommended in order to manage their status while in
test mode.
By doing so we can prevent unnatural test configurations
that may might place some devices on the board in a
dangerous state.
TRST
TRST option is important in order to maintain testing
consistency and in order to be sure of the correctness of
the results.
2 Choices are available:
• Adding TRST.
• Adding POR (Power On Reset).
Shorts
The first step of checking the board is for shorts.
This part is very important (though it may take some time)
because we need to be sure our test results are true.
Increasing Shorts coverage
It is important that all the devices should be BS
When a BS device is connected to a non-BS device it is
harder to discover shorts.
This problem can be solved by using BC_7 pins.
BC_7
BC_7 cell is designed for bidirectional signal pins, and
when in drive mode, it is able to sense the value of the
driven signal, thus monitoring the “transmitted” data”.
Ground Bounce
Ground Bounce is actually a state in which the DC power
supply drops the voltage for a small amount of time, this
situation might cause a disruption in the TAP Controller’s
operation.
Its important to ensure our Device is protected from such
Thing, and it could be tested by checking an “Extreme”
situation of input by using EXTEST command.
Accessing the internals DFT
By allowing access to other internal chip DFT features like:
• Memory BIST (Built-In Self-Test)
• Logic BIST
We can re-use these features once the chip is assembled
on the board which In turn supports improved board-level
diagnostics.
While using the RUNBIST (Built-In Self-Test) and INTEST
(Built-In Self-Test) the device switches into test mode
which gives the control to the boundary scan cells on the
output.
Safe States: Power-Up & EXTEST
Boundary Scan Devices should be powered up in safe
states meaning IO in input mode and OZ in output
mode, thus avoiding the risk of powering up into a
Contention state (Bus fight).
TAP Pin Layout
It is suggested to position the TDI, TDO, TMS, TRST and
TCK pins away from the Power and Ground Pins in order
to avoid the situation that shorts will behave very
deterministically as strong stuck-at-1 or stuck-at-0.
Reduced Pin-Count Test (RPCT)
Problem:
How to test a 600-pin chip on a 500 Driver/Sensor
channel tester?
Solution:
1. Buy a new machine.
2. Use 100 bits of the BS register to indirectly access the
low – frequency pins.
Design for RPCT
High data-rate pins like: Scan-In, Scan-out, Clock are
Contacted directly while the Low data-rate functional
pins are accessed by part of the BS register.
The BS register is designed to allow segments to be
addressed through the TAP using Instructions like
INTEST-RPCT.
Why Using RCPT
• Reduces cost of test: re-use older testers, no need to
buy new D/S channels.
• Reduces number of probe points during wafer probe:
- lower cost
- lower contact problems
• Enables multi-site testing at both wafer probe and
packaged die test.
• Only a few high-speed, high resolution pins needed.
THE
END