Transcript THE ST7 CORE

Sistemi Elettronici
Programmabili
ST7
Generalità e core
Sistemi Elettronici Programmabili
9-1
THE ST7 VISION
SUPPORT
FLASH MEMORY
STM
DEVELOPMENT ANALOG
TOOLS
ST7
Core
DIGITAL
3rd PARTY
DEVELOPMENT
TOOLS
EMC/LOW POWER
SERVICE
Sistemi Elettronici Programmabili
9-2
THE ST7 CORE


Well-known Industry Standard 8-bit CISC
architecture (Von Neuman)
compatible with most popular cores
200 ns minimum instruction time
with 1.375µs 8x8 multiplication
64 KBytes linear addressing memory
Indirect and Y index memory access
Direct STACK management
PERIPHERALS
HARDWARE
REGISTERS
RAM
$00
$80
STACK
$0200
RESERVED
$1000

And many powerful added features ...
ROM/EPROM
up to 60 KBytes
$FFE0
INTERRUPTS
& RESET
VECTORS
$FFFF
Sistemi Elettronici Programmabili
9-3
STM A KEY PLAYER IN
FLASH MEMORY
A VOLUME SUPPLIER
Micros with embedded non-volatile memory have been in high volume
production since 1998
Non-volatile memory products : 1 Billion units sold in 1998
MASTERING EMBEDDED FLASH SOLUTIONS Very
high reliability with 20 year retention
Two solutions for cost vs. feature optimization
eFLASH
Data EEPROM capable Flash
Sistemi Elettronici Programmabili
FLASH
9-4
ST7 FLASH : IN SITU PROGRAMMING
WITH HIGH PROTECTION
Patented high protection level on Flash, OTP and ROM versions

Piracy protection
Unexpected writing protection
In-situ programming for Flash and EEPROM

from any pins / peripheral interfaces (software configurable)
Remote mode (at production level)
Flexible production manufacturing
and test flow
Standalone mode (application running)
On-the-fly application reprogramming
Sistemi Elettronici Programmabili
9-5
ST7 ANALOG PERIPHERALS
MORE FLEXIBILITY & LESS COMPONENTS
Low Voltage Detector
Op Amp
8- & 10-bit ADC
... and more to come
Up to 16 channels
Fast conversion time 3 ms
High resolution (5 mV)

+
Simple PCB
No interrupt
Less external components
Low power consumption
Less external components
Embedded supply monitoring
Sistemi Elettronici Programmabili
9-6
LOW VOLTAGE DETECTOR
CHARACTERISTICS
VCC supply
interrupt
generation
interrupt
generation
VLVDr(
IT)
VLVDf(
IT)
VLVDr
(reset)
VLVDf(re
set)
hysteresis
fixed DV
hysteresis
VDD Min
Internal RESET
LVD (IT) : interrupt generation before
entering reset
LVD (reset) : flag activation
Selectable reset levels for

5 V applications : [4.5 V - 5.5 V]

3.3 V applications : [3 V - 3.6 V]

...

Context saving in EEPROM
Origin of reset localizable
Saves external supply monitoring circuitry
Sistemi Elettronici Programmabili
9-7
LOW VOLTAGE DETECTOR
ST7
VDD
External components saved

2 Clamping diodes

4 Resistors

1 Transistor

1 Zener diode

1 Filter capacitor
Reset
circuit
Integrated 3-level range on
Low Voltage Detector
Reset automatically activates
when 0.8V < VDD < Safe Level
 External reset generation (30 µs)
Internal interrupt & reset generation

Reset of other devices of the application
Cost savings of 10 to 15 cents
Enhanced reliability
Safe micro behavior
Sistemi Elettronici Programmabili
9-8
INTEGRATED OPERATIONAL
AMPLIFIER
ST7
ADC
OUTPUT
Op-Amp
+
ANALOG / DIGITAL
OUTPUT
PROGRAMMABLE
VREF

Rail-to-rail programmable op-amp
Band gap
Fixed voltage reference
Programmable voltage reference
6.5 MHz bandwidth
Auto-zero mode
On/off capability
Internal connection to ADC

PROGRAMMABLE GAIN
OP-AMP
Can be used for

ADC zooming

Comparator / voltage threshold detector

Peak voltage detector
ADC error suppression
Low power consumption
Cost saving
Sistemi Elettronici Programmabili
9-9
ST7 LOW POWER SOLUTIONS
EMC by design
Oscillator
Low power modes
2 mA
RUN
3 KV
2 KV
ST7
PRODUCT
RANGE
1 KV
SLOW
Industry
Acceptance
WAIT
INTERNAL SAFE
OSCILLATOR
SLOW-WAIT
ACTIVE-HALT
98
99
Low emission
High robustness
00
< 700 mA / 16 MHz
Low power and safe
Sistemi Elettronici Programmabili
0.2 mA
HALT
Low power consumption
9-10
ST7 MULTI-OSCILLATOR SYSTEM
osc1


osc2
Quartz / ceramic
Up to 16 MHz
osc1


osc2
External source
Up to 16 MHz
osc1



osc2
Internal RC
1 MHz +/- 1%
4 MHz +/- 20%
osc1


osc2
External RC
1 to 14 MHz
Low frequency backup safety oscillator
 Automatic switch from main clock to safe clock
 Dedicated flag & Interrupt generation
 Watchdog always operational

osc1


osc2
Internal safe oscillator
250 KHz +/- 15%
Power optimization
Safe microcontroller behavior
Sistemi Elettronici Programmabili
9-11
ST7 LOW POWER MODES
Consumption
5V4MHz
typical
ST7 LOW POWER MODE FIT ALL YOUR
APPLICATION REQUIREMENTS
1.8mA
Core and peripherals run at max. frequency
Selected peripheral can be switched off
600µA
Core and peripherals run at Fosc2n
RUN
SLOW
1mA
WAIT
350µA
SLOW-WAIT
ACTIVE-HALT
HALT
Core frozen
Peripherals run at max. frequency
Core frozen
Peripherals run at Fosc2n
300µA
0.2µA
Sistemi Elettronici Programmabili
9-12
EMC APPROACH : SECURE & ROBUST




Low power design
Protected and robust macrocells
Factual measurements through comprehensive testing
Operation in noise sensitive environments can be evaluated
from the information available in datasheet
High protection
Cost savings
 Fewer components on the board
Sistemi Elettronici Programmabili
9-13
ST7 PROGRAMMABLE I/Os
PIN-BY-PIN FLEXIBLE CONFIGURATION
REGISTER
W
DATA BUS
R
R/W
REGISTER
DATA BUS
ALTERNATE INPUT
EXTERNAL
INTERRUPT
INTERRUPT
ALTERNATE OUTPUT
ANALOG INPUT
Input I/O port configuration example
Output I/O port configuration example
High flexibility in I/Os and software configuration
 Fewer external components and less expensive PCB

One microcontroller for different design versions
Lower development and inventory cost
Lower pin count and better pricing through economy of scale
Sistemi Elettronici Programmabili
9-14
ST7 : A SET OF AVAILABLE
PERIPHERALS
SPI
I/Os
I2C
TIMERS
CAN
EEPROM
LCD
DRIVER
MOTOR
CONTROL
ST7
Core
SCI
(UART)
USB
ROM
Op
Amp
FLASH
ADC
Sistemi Elettronici Programmabili
SRAM
SMART
CARD
INT.
9-15
Sistemi Elettronici Programmabili
9-16
ST7 TECHNICAL TRAINING
1 - INTRODUCTION
2 - CORE
3 - ADRESSING MODES
4 - PERIPHERALS
5 - ST7 SOFTWARE TOOLS
6 - ST7 HARDWARE TOOLS
7 - STVD7
Sistemi Elettronici Programmabili
9-17
ST7 CORE
Sistemi Elettronici Programmabili
9-18
ST7 CORE
General Description
• THE ST7 CORE (Von Neuman Architecture) IS BUILT AROUND :
– an 8-bit Arithmetic and Logic Unit (ALU)
– 6 internal registers : Accumulator (A), X and Y index registers,
Program Counter (PC), the Stack Pointer (SP) and the Code Condition
register (CC)
– a controller block
• IT INTERFACES WITH :
– an on-chip oscillator
– a reset block
– address and data buses to access memories and peripherals
– an interrupt controller
Sistemi Elettronici Programmabili
9-19
ST7 CORE
Block Diagram
OSCin
Mutli oscillator
Clock controller Internal
CLOCK
OSCout
ISPSEL/ Vpp
CONTROL
RESET
8 -BIT
ALU
ADDRESS BUS
Accu
Index X
Index Y
CC
SP
PCL
PCH
DATA BUS
Watchdog
LVD
Enhanced
Reset
Program
memory
RAM
Sistemi Elettronici Programmabili
9-20
ST7 CORE
Internal Registers (1)
• The ACCUMULATOR is an 8-bit general purpose register
used to hold:
– Operands
– Results of arithmetic and logic operation
• The X and Y REGISTERS are two 8-bit registers used to :
– Create effective addresses
– Store temporary data
 Y is not automatically stacked. If needed, it must be done

using the PUSH and POP instructions
Instructions using X are faster than the ones using Y
Sistemi Elettronici Programmabili
9-21
ST7 CORE
Internal Registers (2)
• The PROGRAM COUNTER PC is a 16-bit register used to store
the address of the next instruction to be executed by the CPU. As
a result, the ST7 can address up to 64k of program memory
• The STACK POINTER SP is a 16-bit register. The msb is fixed
by hardware
• The CODE CONDITION CC is a 5-bit register
BIT
H
I
N
Z
C
NAME
DESCRIPTION
H=1 when a carry occurs during ADD and ADC
Half Carry Bit
instructions
Interrupt mask I=1 disabled the interrupt
Negative bit N=1 if the result of the last operation is negative
Z=1 if the result of the last operation is zero
Zero bit
Carry/Borrow Affected when carry or borrow out occur and some
bit
inst. are executed
Sistemi Elettronici Programmabili
9-22
ST7 CORE
Internal Registers (3)
7
ACCUMULATOR :
X
RESET VALUES :
0
X
X
X
X
X
X
7
0
X INDEX REGISTER :
RESET VALUES :
X
RESET VALUES :
PROGRAM COUNTER :
RESET VALUES :
STACK POINTER :
X
X
X
X
X
X
7
Y INDEX REGISTER :
X
15
X
X
0
X
X
X
X
X
X
7
X
0
RESET VECTOR @ FFFEh-FFFFh
15
x
7
x
x
x
x
x
x
0
x
Fixed By HW
CONDITION CODE REGISTER :
RESET VALUES :
Sistemi Elettronici Programmabili
7
1
6
1
5
1
4 3
H I
2
N
1
Z
0
C
1
1
1
X
1
0
1
0
9-23
ST7 CORE
Stack manipulation (1)
• PURPOSE :
– Save the CPU context during subroutine calls or interrupts
– Save temporary user's data (PUSH and POP instructions)
• IN CASE OF OVERFLOW (LOWER LIMIT EXCEEDED) :
– SP rolls over to the higher address
– Previous value is overwritten so lost
– Stack overflow is not indicated
Pop
Y
Return from
subroutines or
interrupt
Lower
Address
Higher
Address
Sistemi Elettronici Programmabili
Push
Y
Call subroutines or
interrupt
9-24
ST7 CORE
Stack manipulation (2)
CALL
subroutine
PUSH Y
Interrupt
event
POP Y
RET
RSP
IRET
$0100
SP
SP
SP
$017F
PCH
PCL
CC
A
X
PCH
PCL
PCH
PCL
Y
CC
A
X
PCH
PCL
PCH
PCL
SP
CC
A
X
PCH
PCL
PCH
PCL
SP
PCH
PCL
SP
Stack size and position is device dependent :
ST72254 : 128 bytes ($0100 to $017F)
ST72334 : 256 bytes ($0100 to $01FF)
Sistemi Elettronici Programmabili
9-25
ST7 CORE
The memory space
• THE MEMORY CAN BE MADE OF
6 DIFFERENT BLOCKS :
Short
• Peripherals hardware register
Addressing
Mode I/O Ports, TIM, ADC, WDG,SPI,
Location I2C, EEPROM etc
• Ram 0 : ram in first page
• Stack : from 128 to 256 bytes
(device dependent)
• EEPROM Data (up to 256 bytes)
• Program memory
• Interrupt and Reset vectors
Sistemi Elettronici Programmabili
PERIPHERALS
HARDWARE
REGISTERS
RAM 0
128 Bytes
$00
$80
$0100
STACK
128 Bytes
$0180
RESERVED
$E000
ROM/EPROM
8KBytes
$FFE0
INTERRUPTS
& RESET
VECTORS
$FFFF
9-26
ST7 IN-SITU PROGRAMING
Remote ISP
• What is it for ?
– To PROGRAM or REPROGRAM (flash devices) the
Program Memory when the micro is soldered on the
application board.
• Main features:
– Only 6 wires are used (including VDD & VSS).
– Do not need double voltage on the application board.
– Supported by the ST window eepromer tools.
• Performances:
– ~ 5 s to program 8Kbytes.
Sistemi Elettronici Programmabili
9-27
ST7 IN-SITU PROGRAMING (ISP)
Remote mode
ISPCLK
I/Os
Boot-ROM
ISPCLK
ISPDATA
ISPDATA
RESET/ISPSEL 4
VCC/VSS
RESET/ISPSEL 4
VCC/VSS
RAM
1
Periphs
PROG
MEMORY
RAM
2
Software executed in RAM
programs the prog memory
PROG
MEMORY
Boot-ROM allows an executable
software to be dowloaded in RAM
through ISPCLK & ISPDATA
Software executed in RAM runs any applicative software with I/Os
and peripherals access
In-Situ Programming uses 6 wires only
Sistemi Elettronici Programmabili
9-28
Memory & CPU register
Summary
• How Many CPU registers belong to the ST7 Core?
• Is it possible to place and read data in ROM (program memory)?
• Is it possible to execute code located in RAM ?
• Is the Stack handle automatically by the ST7 core ?
Sistemi Elettronici Programmabili
9-29
ST7 INTERRUPTS
Overview
• EXCEPT FOR THE SOFTWARE INTERRUPT (TRAP Instruction), ALL
INTERRUPTS CAN BE MASKED BY SETTING THE I BIT IN CC
• WHEN AN INTERRUPT OCCURS :
– The context is saved on the stack (CC, A, X, PC)
– All other interrupts are masked (the I bit is set By H/W
– The interrupt vector is loaded in the Program Counter
• WHEN RETURN FROM INTERRUPT IS EXECUTED :
– The original context is automatically restored (CC, A, X, PC)
– Interrupts are enabled (I bit reset)
• PRIORITY BETWEEN INTERRUPTS IS GIVEN BY THE INTERRUPT
ADDRESS VECTOR
Sistemi Elettronici Programmabili
9-30
ST7 INTERRUPTS
ST72254 Interrupt mapping
CPU INTERRUPT
INTERRUPTS
Reset
Reset
Trap (instruction)
REGISTER
FLAG
NAME
INTERRUP
T SOURCE
VECTOR
ADDRESS
N/A
N/A
-
FFFEh-FFFFh
Software
N/A
N/A
I0
FFFCh-FFFDh
External Interrupt 0
Port A
N/A
N/A
I1
FFFAh-FFFBh
External Interrupt 1
Port B and Port C
N/A
N/A
I2
FFF8h-FFF9h
CSS
Clock Filter Interrupt
CRSR
CCSD
I3
FFF6h-FFF7h
SPI
Transfer Complete
Mode Fault
SPI Status
SPIF
MODF
I4
FFF4h-FFF5h
Timer A
Input Capture 1
Output Compare 1
Input Capture 2
Output Compare 2
Timer Overflow
Timer A Status
ICF1
OCF1
ICF2
OCF2
TOF
I5
FFF2h-FFF3h
Timer B
Input Capture 1
Output Compare 1
Input Capture 2
Output Compare 2
Timer Overflow
Timer B
Status
ICF1
OCF1
ICF2
OCF2
TOF
I7
FFEEh-FFEFh
I2C
Byte Transfer finished
Bus Error
STOP Detection
I2C Status
BTF
BERR
SSTOP
I12
FFE4h-FFE5h
Sistemi Elettronici Programmabili
9-31
ST7 INTERRUPTS
Peripheral Int management
Periph Status
Register
X
X
X
1
X
X
X
X
Interrupt flag
set by H/W
Periph Control
Register
X
X
X
1
X
X
X
X
Interrupt Enable bit
set by S/W
Condition Code
Register
1
1
1
H
0
N
Z
C
Interrupt Mask bit
set by S/W

Interrupt
generation
Sistemi Elettronici Programmabili
Context switch
takes 10 CPU
clock cycles
9-32
ST7 INTERRUPT
Peripheral Int management
 SOFTWARE EXAMPLE
.Main
...
BSET Control_reg, #IT_enable ; Enable Periph
interrupt
RIM
; Clear I bit in CC regis
...
; ie interrupt enabled
.Int_routine
...
BRES Status_reg, #IT_flag
IRET
...
; Avoid to process the
; same interrupt forever
; Return from interrupt
Sistemi Elettronici Programmabili
9-33
ST7 Interrupt Summary
•
•
•
•
Interrupt Vectors:
Number:
S/W Priority * :
Interrupt Reaction
Time:
• Automatic register
pushed:
• up 16 Vectors
• 16 levels hardwired
• 4 levels user
configurable
• 1.250µs to 2.750 µs
(end of the current
instruction +10 cpu
cycles)
• Program Counter,
Accumulator, CC, X
Software levels allows the ST7 nested interrupt process
(only in the ST72511R & subsets)
At least one Interrupt Vector per Peripheral
Sistemi Elettronici Programmabili
9-34
Concurrent Interrupt Management
IT0
IT3
NMI
IT1
IT4
IT2
• An interrupt can not be interrupted by another one
• Except by the NMI (Non Maskable Interrupt)
Software Priority
3
NMI
3
Hardware Priority
IT0
IT1
3
IT1
IT2
3
3
IT3
RIM
3
IT4
main
main
Sistemi Elettronici Programmabili
3/0
9-35
Nested Interrupt
• The 4 interrupt S/W levels are set thanks to the pair of bits
I0, I1.
Interrupt Software Priority
Level
I1
I0
Low
1
0
Level 1
0
1
Level 2
0
0
1
1
Level 0 (main)
Level 3 (=interrupt disable)
High
• 1 pair of bits by interrupt vector stored in the ISPR
registers
• The pair of bits is copied in the CC register when the
corresponding IT is activated (software level greater than
the current one).
Sistemi Elettronici Programmabili
9-36
Nested Interrupt Management
IT0
IT4
IT3
NMI
IT1
IT2
• An interrupt can be interrupted by:
– The NMI (Non Maskable Interrupt)
– An interrupt request having an highest software Priority
Software Priority
3
NMI
3
Hardware Priority
IT0
IT1
2
IT1
IT2
1
IT2
3
IT3
RIM
IT4
main
3
IT4
Sistemi Elettronici Programmabili
main
3/0
9-37
Interrupt Roadmap
GP 42,44,56,64 pins
GP 28,32 pins
ST72104G1
ST72215G2
ST72216G1
ST72254G1/2
Concurent Interrupts
ST72314J2/4
ST72314N2/4
ST72334J2/4
ST72334N2/4
Auto 42,44,56,64 pins
ST72532R4
ST72311R6/7/9
ST72512R4
ST72511R6/7/9
Nested Interrupts
Concurent Interrupts
Dedicated Solutions
ST72171K2
ST72411R1
ST72141K2
Sistemi Elettronici Programmabili
Concurent Interrupts
9-38
Interrupts Summary
• How many interrupt vectors can be used in the ST7 ?
• Are the software interrupt levels able to be modified
during the application?
• What are the instructions that enable & disable the
Interrupts?
Sistemi Elettronici Programmabili
9-39
Multi oscillator (1)
• ADVANCED ST7 CLOCK SYSTEM
OSC1
OSC2
 QUARTZ/CERAMIC
OSC1
OSC2
 EXTERNAL SOURCE
OSC1
OSC2
 INTERNAL # 4Mhz
OSC1
OSC2
 EXTERNAL RC
• Low frequency backup safety oscillator
• Implemented on Reprogrammable devices only
Sistemi Elettronici Programmabili
9-40
Multi Oscillator (2)
• 4 Crystal / Ceramic
Oscillators
– Designed to reduce EMI
& consumption
• Low speed
• Mid low speed
• Mid high speed
• High speed
• 1 External RC Oscillator
• 1 Internal RC Oscillator
• 1 Internal Safe Oscillator
• Frequency range
•
•
•
•
1 to 4 MHz
2 to 4 MHz
4 to 8 MHZ
8 to 16 MHz
• 1 to 14 MHz
• # 4 MHz
• # 250KHz
Oscillator selected by option byte
Sistemi Elettronici Programmabili
9-41
Main Clock Controller
Clock Security System (CSS)
OSC1
Multi Oscillator
(MO)
OSC2
Clock
Filter
Safe
Oscillator
fOSC
Main Clock Controller (MCC)
CLKOUT
Alternate
Function
MCCSR
Register
Clock Divider
fCPU
Clock divider Values:
2,4,8,16,32
Sistemi Elettronici Programmabili
CORE &
PERIPHERALS
9-42
Clock Security System
• Clock Filter Function
Main Oscillator
Clock
Internal ST7
Clock
• Safe Oscillator (# 250KHz)
Main Oscillator
Clock
Safe Oscillator
Clock
Internal ST7
Clock
CSSD bit is set by H/W if one of the safety function is activated and
can generate a maskable interrupt request
Sistemi Elettronici Programmabili
9-43
ST7 CLOCK IN LOW POWER
MODES
• RUN MODES: Fcpu=Fosc/2
– Core & periph. running except if WAIT (Core stopped) selected
• SLOW MODES: Division ratio from 4 to 32 by software
– Core & periph. running except if WAIT (Core stopped) selected
• ACTIVE HALT: Division ratio from 32000 to 400000 by software
– Core & periph. stopped but periodic wake-up through interrupts
• HALT MODE: Oscillator stopped
– Core & periph. stopped
Sistemi Elettronici Programmabili
9-44
ST7 Clock System Roadmap
GP 28,32 pins
ST72104G1
ST72215G2
ST72216G1
ST72254G1/2
Multi oscillator
RC ext.
4Mhz int. 20%
Safety oscillator
SLOW: 4/8/16/32
ST72314J2/4
ST72314N2/4
ST72334J2/4
ST72334N2/4
Auto 42,44,56,64 pins
Dedicated Solutions
ST72171K2
ST72532R4
ST72311R6/7/9
ST72512R4
ST72511R6/7/9
Quartz/Ceramic/Ext.clock
4Mhz min
SLOW:4/8/16/32
ACTIVE HALT
GP 42,44,56,64 pins
Multi oscillator
RC ext.
4Mhz int. 20%
Safety oscillator
SLOW: 4/8/16/32
ACTIVE HALT
ST72411R1
ST72141K2
Sistemi Elettronici Programmabili
Idem as GP 28,32 pins
7.16Mhz int / Ext.Clock
SLOW:/32
Quartz/Ceramic/Ext.clock
SLOW:4/8/16/32
9-45
ST7 CORE
Reset diagram (1)
• EXTERNAL RESET USING RESET PIN
– Purpose : allow to generate an external reset
– Condition : reset pin pull low
• POWER SUPPLY DEPENDEND RESET USING LVD
– Purpose : ensure the MCU is in a known state whatever Vcc
– Condition : internal reset when Vcc reaches Vcc min
• WATCHDOG RESET USING THE WATCHDOG TIMER
– Purpose : guarantee the safety in case of software trouble
– Condition : internal reset when the WD register is not
refreshed
Sistemi Elettronici Programmabili
9-46
ST7 ENHANCED RESET
SYSTEM
• 3 RESET SOURCES
– Watchdog
– Low Voltage Detection
(LVD)
– External RESET pin
• COMPLETE RESET
MANAGEMENT
– Flags on Reset sources
– Internal Reset externally
issued to reset the whole
application
COMPLETE RESET SEQUENCE
Phase with
RESET pin
grounded
Internal Reset
4096 clock cycles
Fetch Reset
Vector
From internal Watchdog Reset: Phase # 30µs
From internal LVD Reset: 30µs<Phase<Low voltage duration
From external RESET pin: 30µs<Phase<Ext RESET pulse width
Sistemi Elettronici Programmabili
9-47
ST7 CORE
Reset diagram (3)
VCC
CK
OSCILLATOR
Internal
Reset
SIGNAL
COUNTER
TO ST7
NRESET
(ACTIVE LOW)
RESET
30µs Delay
LVD RESET
WATCHDOG RESET
Sistemi Elettronici Programmabili
9-48
NEW ST7 LVD GENERATION
Safe behaviour despite
starting current sunk
VCC supply
VLVDr
250mV hysteresis
VLVDf
Min working VDD
RESET
 3 Selectable levels
 Low consumption
 Activation Flag
 RESET pin tied to GND
Sistemi Elettronici Programmabili
9-49
3 LVD LEVELS TO OPTIMIZE
THE SAFE AREA
Freq.
LVD low
LVD med. LVD high
Absolute working
window
16Mhz
Safe 16MHz
area.
3.5V Reset
issued
8Mhz
Safe 8Mhz
area
3.0V
3.5V
Safe 16Mhz
area
3.8V Reset
issued
Vsupply
4.0V
Sistemi Elettronici Programmabili
9-50
LVD PART OF COMPLETE
RESET MANAGEMENT
Software
clearance
LVDRF
If LVDRF is
not cleared
upon another
Reset, the
flag remains
SET to keep
trace of
original
failure.
WDGRF
Vdd supply
LVD Reset
ensures a
stable cleared
state of the
WDGRF
when CPU
starts
LVD
External
LVD
WDG
Original RESET
source
LVD
WDG
LVDRF
WDGRF
External RESET pin
0
0
Watchdog Reset Flag
0
1
Sistemi Elettronici Programmabili
Low Voltage Reset
Flag
1
X
9-51
ST7 WATCHDOG
Overview (1)
• ITS PURPOSE IS TO DETECT THE OCCURENCE OF A
SOFTWARE FAULT. IT MUST BE REGULARLY
REFRESHED BY THE PROGRAM :
– ld
WDCR, #$FF ; Reload WD
• 2 DIFFERENT WATCHDOG CAN BE SELECTED BY
OPTION MASK :
– Hardware Watchdog : WD automatically activated
upon reset
– Software watchdog : it is activated by software (bit 7 =
1). Once activated, it cannot be disabled
Sistemi Elettronici Programmabili
9-52
ST7 WATCHDOG
Overview (2)
• RESET AND WATCHDOG :
– HALT instruction can generate a reset if watchdog
activated and if the option byte allows it
– The Watchdog can be used to generate a software reset
(bit 7 = 1, bit 6 = 0)
ld
WDCR, #$80
; Reset !
 Min : WDCR = C0h
D

= 2^0 × 12288 = 12288 clock cycles
= 1.54 ms for Fcpu = 8MHz
Max : WDCR = FFh
D = 2^6 × 12288 = 786432 clock cycles
= 98.30 ms for Fcpu = 8MHz
Sistemi Elettronici Programmabili
9-53
ST7 WATCHDOG
Block diagram
Reset
Activation bit
(WD active if set)
WDGA
-
-
-
-
MSB
-
LSB
-
-
WDGF
Watchdog Status
Register
Watchdog Control
Register
7-bit Down Counter
Fcpu
Clock Divider
÷12288
Sistemi Elettronici Programmabili
9-54
LVD ROADMAP
GP 42,44,56,64 pins
GP 28,32 pins
ST72104G1
ST72215G2
ST72216G1
ST72254G1/2
3 LVD levels:
4.00V/4.25V
3.60V/3.85V
3.10V/3.35V
Reset Flags
ST72314J2/4
ST72314N2/4
ST72334J2/4
ST72334N2/4
Auto 42,44,56,64 pins
ST72532R4
ST72311R6/7/9 LVD by device reference
ST72512R4
ST72511R6/7/9 4.25V/4.50V
3 LVD levels:
4.00V/4.25V
3.60V/3.85V
3.10V/3.35V
Reset Flags
Dedicated Solutions
ST72171K2
Idem as GP 28,32 pins
ST72411R1
1 level LVD
ST72141K2
Sistemi Elettronici Programmabili
9-55
Clock & Reset system
Summary
• What are the maximun oscillator frequency and the
maximun CPU frequency ?
• How many internal RC oscillator are implemented
on the ST7 ?
• What are the internal reset sources?
• Are these internal resets can detected externally?
Sistemi Elettronici Programmabili
9-56
ST7 LOW CONSUMPTION
MODES
Overview
• MAXIMUM CONSUMPTION : 20 mA WITH FOSC = 16
MHZ AND VDD = 5V
• TO REACH LOWEST POWER CONSUMPTION
– Switch off unused peripherals
– Configure I/Os as output low level and connect them to
GND
– Use the lowest oscillator frequency possible
– Use the Slow mode, Wait mode or better the Halt mode
• DATA RETENTION VOLTAGE IN HALT MODE : 2V
Sistemi Elettronici Programmabili
9-57
ST7 LOW CONSUMPTION
MODES
Slow mode
• GOAL : reduce the comsumption by reducing the
clock speed keeping the same Oscillator frequency
• ENTER BY : configuring the miscellaneous register
• CAUSES : the CPU clock slows down
– the Fosc can be divided by 4, 8 ,16 or 32 rather than 2
• EXIT BY : configuring the miscellaneous register
Sistemi Elettronici Programmabili
9-58
ST7 LOW CONSUMPTION
MODES
Wait mode
• GOAL : Reduce the consumption while monitoring external
events
• ENTER BY : execution of the WFI instruction
• CAUSES : the micro is software frozen
– Program execution stopped
– Memory and registers remain unchanged
– The oscillator still provides a clock to the peripherals
• EXIT BY
– Reset (Watchdog, reset pin)
– Internal interrupts (timer A, timer B, A/D, SPI etc)
– External interrupts (I/OSistemi
ports)
Elettronici Programmabili
9-59
•
ST7 LOW CONSUMPTION
MODES
Active
Halt
mode
GOAL : Reduce the consumption to the lowest value while
monitoring a real time clock.
• ENTER BY : execution of the HALT instruction while the OIE
(Oscillator Interrupt Enable) bit is set.
• CAUSES : the micro is SW frozen, all the peripherals are stopped,
only the Oscillator & the Main Oscillator Counter are running.
• EXIT BY
– External Reset
– Interrupts with exit from halt capability (External IT,..)
– Time Base Interrupt (32000,64000,160000,400000 *Tcpu
– From 2ms to 25ms with fOSC=16MHZ
Sistemi Elettronici Programmabili
9-60
ST7 LOW CONSUMPTION
MODES
Halt mode
• GOAL : Reduce the consumption to the lowest value
• ENTER BY : execution of the HALT instruction
• CAUSES : the micro is SW and HW frozen
– Program execution stopped
– Memory and registers remain unchanged
– The oscillator stopped
• EXIT BY
– External Reset
– External interrupts (I/O ports)
Sistemi Elettronici Programmabili
9-61
PROGRAMMING TIPS
Low Consumption Modes (1)
• DURING WAIT MODE or HALT MODE, BIT I
(INTERRUPT BIT) OF CC REGISTER IS
AUTOMATICALLY RESET TO ENABLE INTERRUPT
• TYPICAL CONSUMPTION
ST72254
ST72334
Run mode (Vdd=5V, Fcpu=8MHz)
5.5 mA
7.1 mA
Slow mode (Vdd=5V, Fcpu=500KHz)
0.7 mA
1 mA
Wait mode (Vdd=5V, Fcpu=8MHz)
Wait minimun mode (Vdd=5V,Fcpu=500KHz)
Active Halt mode (Vdd=5V,Fosc=16MHz)
Halt mode (Vdd=5V)
Sistemi Elettronici Programmabili
2 mA
0.4 mA
0.5 mA
-
20µA
0.5 µA
0.5 µA
9-62
PROGRAMMING TIPS
Low Consumption Modes (2)
• AFTER EXITING FROM HALT MODE
OR WAIT MODE AFTER RESET, THE
MICRO WAITS 4096 CPU CLOCK
CYCLE (STABILIZATION TIME)
BEFORE BEING OPERATIONAL
• SOURCE THAT ALLOWS TO EXIT
FROM WFI OR HALT MODE
– Internal Interrupts => Wait and Halt modes
– External Interrupts => Halt mode
Sistemi Elettronici Programmabili
9-63