Transcript Presenter

Test and Fault-Tolerance for Timing
Error
Presenter: Feng Yuan
CUHK
D
FF
FF
Q
Probability
Timing is Almost “Everything” in IC Design
CLK
CLK
Delay
CLK
Setup Time
D
D
Timing
Guardband
 Speed binning --accurate delay testing
 Better than worst case design--online timing error masking mechanism
PSEUDO-FUNCTIONAL TESTING FOR SMALL DELAY DEFECTS
CONSIDERING POWER SUPPLY NOISE EFFECTS
CUHK
The Challenge with Delay Testing
o Causes for timing uncertainty
o Static process variation
o Dynamic supply voltage and temperature variation
o Aging effect
o Difficulties to apply delay
o Small delay defects (SDD)
o power supply noise (PSN)
• 1% supply voltage change cause 4% gate delay change in 90nm 0.9-V
technology
• More severe with technology scaling
• Essential to be considered
PSN-Aware Delay Testing Method
o To guarantee the worst-case scenario
o Method to maximize PSN
o To reduce test escape
At-speed scan patterns 20% slower
than any functional patterns in a
recent study!!!
o Introduce test yield loss
o To avoid undesired test yield loss
o Low power testing techniques to reduce PSN
o Lead to test escape
Observation: ICs in structural test mode behaves more
differently from functional mode
An Example of Functional Un-testable Scan
Testable Delay Fault
1|X
FF0
0|1
1|X
FF3
B
0|1
FF1
1|1
FF2
E
A
0|1
1|0
1|0
X|1
D
1|0
F
G
FF4
C
0|0
Functional Constraint
 Transition on targeted path can be activated by structural test
pattern <1,0,1;X,1,1>
 This transition can be only activated by non-functional pattern
New Weapon: Pseudo-Functional Testing
o To resolve the discrepancy
o Generate functional-like test patterns
o Functional constraint identification methods
o SAT-based method
o Mining+SAT strategy
o Implication-based technique
o Structural analysis in [Yuan, DAC’09]
• Identify near-complete constraints
How to exercise worst-case timing in
They do not consider
PSN
effects
in delay
testing
 under testing
functional
mode
during
delay
testing?
Layout-Aware Pseudo-Functional Delay Test
Pattern Generation Flow
Fault List
Static Timing
Analysis
Pseudo-Functional SDD Test Cube
Generation
PSN Effect Maximization
Physical
Layout
Relevant Transition Identification and PSN
Impact Evaluation
Illegal State
Identification
Pseudo-Functional Transition Activation
for PSN Effect Maximization
Netlist
Fault Drop
Pseudo-functional SDD
cube generation
1.Sensitize long paths
2.Avoid to involve illegal states
PSN effect maximization
1.Identify relevant transitions
2.Activate them as many as
possible
3.Avoid to involve illegal states
TW Comparison for 6 Paths of des
Yield loss
Better
performance
Test escape
INTIMEFIX: A LOW-COST AND SCALABLE TECHNIQUE FOR IN-SITU
TIMING ERROR MASKING IN LOGIC CIRCUITS
CUHK
Equivalent Circuit Construction with
Approximate Logic
o Definition of Approximate logic
(i.e., G=1 implies F=1)
G is 1-approximation of F, if G => F
Example: G=a+b is the 1-approximation of F=a+b+acb
G is 0-approximation of F, if G => F
0-Approximation
Logic (G0)
Original Circuit (F)
1-Approximation
Logic (G1)
This circuit has following properties
A
B
1. It is logically-equivalent with the
original circuit F
2. Worst case delay is dominated by G0
and G1, when they are working
Basic Idea
All circuit’s
inputs
Approximated
inputs
Timing critical
inputs
Masking Timing Error with Approximate
Logic
Launched
value
Input0
Essential side-input
value
B
Input1
Input2
1
0
E
A
1
1
X
D
X
1 H 0
F
0
0
G
I
0
0
J
0
X
C
Masking Logic
0-approximation logic
H'
A'
B
F'
I'
C
1-approximation logic
H''
D''
G''
J''
C
B
Input2
Overall Flow
Timing information &
netlist
Identifying Critical Flip-Flop
Extracting Primary Critical Segment
Merging Primary Critical Segment
Inserting Approximate Logic
Multiple critical paths can be
processed concurrently
FF
To reduce the hardware cost
Experimental Result
Original standard deviation: 0.39
Our standard deviation: 0.19
QUESTION TIME
Presenter: Feng Yuan
CUHK