Transcript Analog CMOS Circuit Design Prof.Hansraj Guhilot, Professor&Head

VTU - VLSI on Analog Design
Lecture slides for the class of -2005
Prof. Hansraj Guhilot
Professor and Head, E&CE Department
KLE Society’s College of Engineering and Technology, Belgaum-590008
Email: [email protected]
Hansraj Guhilot
Topics Covered
Current Mirror
Band gap voltage reference
Design of 2 stage OPAMP
OPAMP Performance metrics
OPAMP and OTA circuits
Statistical design and simulation
Current Mirror
Basic configuration
Cascode Current Mirror
Wilson Current Mirror
Regulated Cascode
Basic Definitions
Current Sink
VO
Current Source
VDD
IO
IO
VO
Current Mirror
Iref
IO
VO
IO= Iref
VO
Iref
Current Lens
VO
IO= KIref
Often times, the term current mirror is used to include current lens
Simplest current source/sink
NMOS/PMOS transistor in saturation
Vo
Io
2
VGS
Io 
 oxW VGS  Vt 
Tox L
2
1  Vo 
• Sensitive to variation in Vo (I.e.Ro is not infinity)
• Sensitive to variation in VGS
• Sensitive to temperature variation (Vt, n, p)
• Sensitive to process variation (Vt, W, L, Tox)
Strategy: Create one very well defined current reference using
complex temperature compensation and VDD insensitivity.
Then use current mirrors (copy) to generate others
Basic Current Mirror
M1 is diode connected and
is always in saturation
IR
IO
M1
VR+
_
+
M2 VO
-
IR sets a unique bias voltage VR
IR 
 oxW1 VR  Vt 2
Tox L1
2
1  VR 
M2 will mirror this current provided VO >VR - Vt
Since VR = Vt + DV where DV is gate over drive ; VO > DV
IO
DV
VO
Current ratio
Neglecting channel length modulation effect,

W L 2
IO 
IR
W L1
However it is advisable to choose constant L for
Both M1 and M2 and ratio based on Ws only
L  Lg  2 LD
LD is constant for all Lg  Ratio in Lg does not translate to ratio in L
W2
IO 
IR
W1
Channel width effect
Strictly speaking
W  Wg  2DW
where DW is due to field oxide encroachment
Ratio in Wg does not translate to ratio in W
Parallel transistor layout can be used to overcome this problem
Ex: Io=2IR , then W2=2W1
M1
M2
M2
S
Io 
2Wg1  2DW
Wg1  2DW
IR
D
S
Io 
2Wg1  4DW
W g 1  2 DW
I R  2I R
Issues with basic current mirror
Vds effect results in incorrect mirroring
I O W 2 1  Vo

I R W1 1  VR
For L1=L2, 1= 2 =
For VR << 1, and neglecting 2 term:
IO W 2
1   (Vo  VR )

I R W1
The output resistance is finite
Ro=ro2
Cascode current mirror
IR
VGB
VO
M3 is in common gate configuration
IO
Hence M2 and M3 form cascode pair
M3
X
M3 shields node Y from variations in Vo
Y
M1
VR+-
M2
Dvo g m 3  g mb3

Dv y
g o3
Dvo
Dv y 
Av (0)
In order for Io=IR, VGB should be chosen such that Vx=Vy
VGB = Vx + VGS3
This is achieved by introducing another diode connected transistor in series with M1
Cascode current mirror with matching
VGB  Vx  Vgs 0
IR
For Vgs0=Vgs3, we need
VO
IR
M0
X
M1
VGB
IO
M3
Y
VR+-
M2
(W / L)3 (W / L) 2

(W / L) 0 (W / L)1
Then Vx=Vy and IO=IRW2/W1
The minimum allowed Vo:
VGB= Vgs0+Vgs1 = 2DV+2Vt
assuming similar overdrive and Vt
 VOmin =2DV+Vt
Beyond VOmin, M3 comes out of saturation
Output resistance of cascode mirror
io
vo
Applying KCL at output node
-gm3vy
Y
go2
+
vy
-
gmb3vy
go3
io  ( g m3  g mb3 )v y  g o3 (vo  v y )
io  v y g o 2
Ro=vo/io
Ro  ro3  g m3ro 2 (1   )  ro3  g m3ro 2
The output resistance of M3 (ro3) is enhanced by a factor gm3ro2
Cascode mirror with improved o/p swing
The voltage at Go is VG0=2DV+2Vt
IR
VO
M0
X
M1
VGB
Vt
IO
M3
Y
VR+-
M2
Hence the voltage at G3 is
VG3=2DV+Vt
 VOmin =2DV
Although output swing is increased,
it should be noted that VxVy
Hence the improvement has come
at the expense of current matching
Cascode mirror with improved o/p swing
Vt can be implemented using following configuration
IR
W/4L
M0
X
M1
W/L
VDDVO
VGB
VR+-
VO
For the currents to be identical
the gate overdrive of M0 be
twice that of M1 (2DV and DV)
IO
M3
M5
IO
Y
M3
Vgs0=3DV+2Vt
M2
Vgs3=2DV+Vt
M2
M4
W/L
The size of M0 is 4 times
smaller than that of M1
W/L
VOmin=2DV
Wilson Current source
IR
VO
Negative feedback arrangement
through M1, M2 and M3.
IO
X
• If Vo increase, then Io tends to increase
Id2 and hence Vy increase
• Since IR is constant, Vx decreases
thus decreasing the gate drive for M1
• This will restore Io to its initial value
M1
Y
M3
M2
i.e. any change in Vo is absorbed as an appropriate change in Vx
IO W 2

1  2V y  3Vx )
I R W3

Vomin=2DV+Vt

Output resistance
+
-
vx-vy
gm1(vx-vy)
gmb1vy
Y
go2
gm3vy
gm2
Ro=vo/io
 g m1 g m3 
Ro  ro1 1 

 g m 2 g o3 
Ro  ro1 ( g m1ro3 )
+
-
vy
go2
io
go1
vo
Modified Wilson
IR
M4
X
M3
VO
IO
M1
Y
M2
The current matching is improved
Vx=Vy can be ensured if
(W / L)1 W2

(W / L) 4 W3
Under this condition,
IO=IRW2/W3
The output resistance is similar to Wilson
Ro=ro1(gm1ro3)
Regulated Cascode
IR
VO
The gate of M3 is connected to drain of M2
IO
The gate of M2 is connected to fixed VG2
M1
X
Y
M3
VG2
M2
The negative feedback is provided
through M1 and M3
Change in Vo is absorbed at Vx
No explicit conventional mirror connection of transistors
The mirroring is entirely due to the negative feedback
The output resistance is enhanced significantly
The minimum allowed output voltage is lowered Vomin=2DV
*The circuit works reasonably well even if Vomin drops to DV
Output resistance
+
-
vx-vy
gm1(vx-vy)
gmb1vy
Y
go2
gm3vy
+
-
vy
go2
 g m1 g m 3 
Ro  ro1 1 

 g o 2 g o3 
Ro  ro1 ( g m ro ) 2
Very high output impedance
io
go1
vo
Regulated cascode with bias generation
VDD
M6
M7
X
IO
M1
M3
Y
IR
X
Y
M5
VR+-
VO
M4
M2
IR generates fixed bias for VG2
IR is mirrored on to M3 through the NMOS (M4-M5)
and the PMOS (M6-M7) current mirrors
Layout Issues
Orientation
Symmetry
Adding dummy layers
Unit cell repetition
Common centroid
Avoiding interconnect resistance
Orientation
Matched transistors should be oriented in same direction
M1
M2
M1
M2
Photolythography process has different biases in
different axes, hence the requirement
Symmetry
An unrelated metal line going in the vicinity of one of the transistor
M1
M2
Metal 1
Symmetry should be preserved by adding another similar line
M1
Metal 1
M2
Metal 1
Unit cell repetition
Wide transistor should be laid out as parallel transistors
of unit width to decrease gate resistance, s/d area capacitance
as well as to counter DW effect
Disproportionate aspect ratio can be managed as below:
Interdigitation and dummy layer
D1
M1
D2
G
M2
Dummy poly
S
D1
G
S
D2
Interdigitation distributes the transistors uniformly
Dummy poly line eliminates loading effect in photo and etch
Common centroid
1/2M1
1/2M2
1/2M2
1/2M1
Common centroid configuration eliminates the first order
gradient effects of parameters along both the axes
Interconnect routing
IR
M1
V+
_R
Circuit 1
Circuit 2
Circuit 3
Circuit 4
M2
M3
M4
Mn
…
To distribute IR in a large circuit, the resistance of ground bus makes
VgsnVgs1, thus affecting the current mirroring significantly
Interconnect routing
Decrease the ground bus resistance
Provide multiple ground node connections if possible
And use short span ground bus
Keep several reference distributed in a large circuit
and mirror the reference locally
Bandgap Voltage Reference
Bandgap Voltage reference
Design Task to set the DC bias of any circuits
1. Power Supply Independent Biasing
2. Temperature Independent Biasing
Bandgap Voltage Reference
Resistance biasing
VDD
IREF
R1
M1
IO
VR+
_
+
M2 VO
-
VDD
Io 
R1  1
g m1
W2
W1
DVDD W2
DI o 
W1
R1  1
g m1
Io is very sensitive to variation in VDD
In order to have low sensitivity, the circuit must bias itself
i.e. self biasing
Self Biasing circuit
VDD
(W/L)p
M4
K(W/L)p IO = K IREF
M3
But how do we fix IO
IO
IREF
M1
(W/L)n
IO is bootstrapped to IREF
VR+
_
Because as long as all transistors are
saturated, any current is a valid
M2
K(W/L)n solution for the circuit!
In order to uniquely define the current another
constraint should be added to the circuit
Self Biasing
Vgs1  Vgs 2  I O RS
2IO
 Vt 
COX (W L) n
IO 
VDD
(W/L)p
M4
IREF
M1
(W/L)n
+
_
2IO
 I O RS
COX (W L) n
2
1 
1 
1



2
COX (W L) n RS 
K
2
(W/L)p
M3
The current is uniquely defined and
it is independent of supply voltage
IO
The current is still a function of
Process parameters and temperature
M2
K(W/L)n
RS
The Start-up problem
The previous circuit can support zero current as well!
At the start up it should be ensured that the circuit does
not enter this degenerate situation
(W/L)p
At the start up the 3 diode connected
transistors M1, M5 and M3 provide
a path to the ground give non zero Io
IO
Vt1  Vt 5  | Vt 3 | VDD
VDD
(W/L)p
M4
IREF
M1
(W/L)n
M3
M5
M2
3Vt  VDD
K(W/L)n After start up, M2, M4 should turn on
and M5 should be turned off
RS
Vgs1  Vt 5  | Vgs3 | VDD
Temperature Independent Reference
The concept:
Generate the reference by combining two voltages of which
one has negative temperature coefficient and the other one
has a positive temperature coefficient
VREF  1V1   2V2
V1
 ve
T
V2
 ve
T
V
V
1 1   2 2  0
T
T
VBE of a BJT (diode) is a good candidate for negative TC
Difference between 2 different VBEs is a good candidate for +ve TC
Other candidates such as resistor etc. also exist
Negative TC
The BJT collector current is given by
 VBE 
IC
  VBE  VT ln
I C  I S exp 
IS
 VT 
IS=CkTni2
where VT=kT/q , is thermal voltage
C is proportionality constant
  OT m where m-3/2
ni2  T 3exp(-Eg/kT) where Eg is bandgap of Si, Eg  1.12eV
At constant collector current, using above equations,
VBE VBE  (4  m)VT  E g / q

VT
T
Note that the TC is a function of VBE and T itself
For VBE=0.75V and
T=300oK,
VBE
 1.5mV / oK
VT
Positive TC
nIO
IO
+
DVBE
Q1
Suppose that the two collector
currents are nIO and IO
(typically done by adjusting
the device dimensions/layout)
DVBE  VBE1  VBE 2
Q2
DVBE  VT ln
nI O
I
 VT ln O
IS
IS
DVBE  VT ln n
DVBE k
 ln n
T
q
Note that the TC is independent of Ic and Temperature
Bandgap Reference
VREF  1V1   2V2
Choose V1= VBE and V2 = DVBE
Set 1=1 and choose 2 such that the TC is zero at 300oK
Since dV1/dT = -1.5mV/oK and dDVBE/dT = +0.087mV/oK,
Choose 2 so that (2lnn)(0.087mV/oK)=+1.5mV/oK
VREF  VBE  17.2VT
VREF  1.19V
Note: VREF can also be expressed as
Eg
VREF 
 (4  m)VT
q
In the limit as T0 , VREF  Eg/q
Hence the name bandgap voltage reference
The circuit to add VBE and 17.2VT
IO
IO
VO1
VO2
VBE1=RIO+VBE2
R
Q1
A
Suppose that VO1 and VO2 are made
equal by some external means
Then,
RIO = VBE1 - VBE2 = VTlnn
VO2=VBE2 + VTlnn
Q2
nA
Q1 is unit transistor with area A
Q2 has n unit transistors in parallel
The current in one unit of Q2 is IO/n
which is the required reference
Need a mechanism for VO1 = VO2
lnn =17.2 results in impractical n and
hence should some how scaled properly
Circuit Implementation
The OPAMP forces VX=VY
R1
R2
Y
A1
+
X
R3
Q1
A
VBE1 - VBE2 = VTlnn
Q2
nA
VO
This results in a current
through the right branch
IR3= VTlnn/R3
Vo  VBE 2 
VT ln n
( R2  R3 )
R3
 R2 
Vo  VBE 2  VT ln n1  
 R3 
If R2/R3 = 10, then n=5
The output Vo gives the required reference voltage
Compatibility with CMOS Technology
In an n-well technology the vertical PNP BJT can be realised
C
E
p+
p+
B
n+
n well
p-substrate
The p-substrate, connected to most negative potential (Gnd) acts
as a collector whereas n-well and p+ region act as base & emitter
Modified circuit for CMOS Technology
R1
R2
Y
A1
+
X
R3
A
Q1
Q2
nA
The output voltage Vo is the
bandgap voltage reference
VO
Vo
T
Design of 2 stage OPAMP
Ideal OPAMP
Infinite differential gain
viv i+
-
Av
+
vo
Infinite input impedance
Zero output impedance
Zero input current
Zero common mode gain
Unfortunately Ideal OPAMP does not exist in reality!
Further attempts to reach ideality with these parameters will
have trade off with respect to speed, power, voltage swings etc
We will treat OPAMP as a “high gain differential amplifier”
designed with an adequate performance metrics for a given
application at hand
Parameters of interest-Open loop gain
OPAMPs are invariably used with closed loop negative feedback
R2
For an ideal OPAMP (Av=),
R1
vi
Av
+
the closed loop gain can be set
vo by only resistance ratio
vo
R2
 1
vi
R1
Suppose R2/R1=9 and Av and it is required to have less than
0.1% error in the gain. Then what is the minimum Av required?
vo
R2  R1  R2 1 

 1  1 
vi
R1 
R1 Av 
For gain error < 0.1%, the open loop gain Av > 10,000
Parameters of interest-small signal bandwidth
AV
The open loop gain drops at
higher frequency resulting in
an increased error for the
closed loop feedback system
20log|AV(0)|
f3dB
fU
f
Also the large signal settling time for the closed loop system
depends on the open loop unity gain frequency
ACL
ACL


Av (0)3dB U
Parameters of interest-slew rate
Determines the large signal behaviour
It gives the highest rate of change of input beyond
which the output does not respond instantaneously
Need very large slew rate for linearity
dVO/dt
SR
dVi/dt
Parameters of interest
Output swing: Trade off between O/P swing, bias current and gain
Linearity:
Differential implementation to suppress even harmonics
Allow significant open loop gain so that closed loop feedback
system achieves required linearity
Noise : Thermal noise and 1/f noise
Offset : Systematic and Random offset
Output load : Typical on-chip OPAMP applications mostly have
very low capacitive load < 1pF
Stand alone OPAMPs may have to drive
high capacitive and low resistance loads
Basic 2 stage OPAMP
Most of the OPAMP designs have two gain stages
Unless absolutely desired, more gain stages should be avoided
Since the frequency compensation becomes complex due to
Multiple dominant poles
Ccomp Compensation Capacitor
vi1
vi2
A1
+
First gain stage
A2
Second gain stage
1X
Output Buffer
vo
Impact of Pole
Vi
R
1
Vo
sC

Vi R  1
sC
Vo
1

Vi 1  s
 1 RC 
Vo
C
The pole is on the left half of s plane (i.e. s=-1/RC  stable system)
The pole frequency p=1/RC
|Av|
1
0.707
p

Gain and Phase response due to pole
G  20 log
Vo
2
 20 log  1  w wp  


Vi

20log|Av|
-20dB/decade
-6dB/octave
0dB
-3 dB
p


   tan 1  w w 
p

0o
-45o
-90o
p

At p the gain is 3dB lower
At p the the phase shift is –45o
Beyond p, the gain decreases at a
rate of –20dB/decade
At 0.1p the the phase shift saturates to 0o
At 10p the the phase shift saturates to -90o
20log|Av|
2 pole system response
-20dB/dec
Go dB
-40dB/dec
0dB
p1
p2
p1
p2

0o
-45o
-90o
-135o
-180o

x
1
H (s) 
1  s 1  s 



p
p
1 
2

If Av(0) is very large and
if p2 is close to p1,
Then it is likely that at
at some frequency x, the
phase shift will be –180o
but the gain will still be
greater than unity
Implication in closed loop negative
feedback system
v iv i+
-
Av(w)
+
vo
At DC and low frequency there is
a phase shift –180o between the
Input vi and the output vo
(This is due to the inversion between
Gate and Drain voltage of Transistor)
If Av() is a two pole transfer function, the poles introduce
and additional phase shift of –180o at x
The negative feedback system gets converted to a positive
feedback system!!
The system becomes unstable and oscillatory
Pole splitting
20log|Av|
-20dB/dec
Go dB
Split the nearby poles far apart by
some technique
fT
0dB
p1
p2

By the time the second pole is
reached the gain has already
dropped below unity
The closed loop feedback system
becomes a stable system
0o
-45o
-90o
-135o
-180o
The phase margin is defined as
PM   ( t )  180o
p1
p2
 PM should be positive for stability
R1
Impact of zero
Vo
Vi
C1
R2
Vo
R2
1  sR1C1

Vi R1  R2 1  sR1 R2C1
R1  R2
1 s
Vo
R2

Vi R1  R2 1  s
z=-1/R1C1 and p=-(R1+R2)/R1R2C1
The zero frequency z=1/R1C1
|Av|
1.47
R2
R1  R2
z
R2
R1  R2

( 1 R1C1 )
 ( R1  R2 ) R1 R2C1
Gain and Phase response due to zero
G  20 log
Vo
2
 Go  20 log  1  w w p  


Vi
  tan 1  w w 

 R2 
Go  20 log 

 R1  R2 
G
Go+3dB
GodB
+20dB/decade
+6dB/octave
z

z

90o
45o
0o
z

At z the gain is 3dB higher
At z the the phase shift is 45o
Beyond z, the gain increases at a
rate of 20dB/decade
At 0.1z the the phase shift saturates to 0o
At 10z the the phase shift saturates to 90o
Negative zero is good

s  z1 
H ( s) 
s  p1 
20log|Av|
-20dB/dec
Go dB


  tan 1  w w   tan 1  w w 

0dB
p1
z1
p1
z1
0o

z1


p1
Negative zero can increase PM
-45o
-90o
-135o
-180o


Positive Zero can be more dangerous

s  z1 
H ( s) 
s  p1 
20log|Av|

1  w


w
   tan
 tan 

w
 wz1 
p
1


1
-20dB/dec
Go dB
Positive zero can make
the system unstable
0dB
p1
z1
0o
-45o
-90o
-135o
-180o

Unstable!
p1
z1

If the positive zero exists
nearby dominant pole,
then cancel the zero
First stage for the 2 stage OPAMP
The first stage should do two tasks
Produce reasonably large gain
Perform differential to single ended conversion
This is done using differential amplifier with
active current mirror load to enhance the gain
VDD
Active current mirror adds
M3
M4
currents in two branches
g m Dv
and doubles the gain while
g m Dv
2
vo performing differential to
g m Dv
2
2
single ended conversion
M1
M2
vi1
vi2
IS
Second stage for the 2 stage OPAMP
VDD
vix
M6
vo
To 1X buffer
Ccomp
PMOS common source amplifier
with the current source load
Ccomp performs frequency compensation
Two stage OPAMP circuit
VDD
M3
g m Dv
2
vi1 -
M1
M4
g m Dv
2
g m Dv
2
M6
M2
vo
Ccomp
vi2+
Vbias
M5
M7
The input vi2 goes through two inversions and hence is +ve i/p
The input vi1 goes through one inversions and hence is -ve i/p
Note that the AC voltages at drain of M1 and M2 will be quite different
First stage Low Frequency Differential Gain
VDD
io  g m Dv
M3
M4
g m Dv
2
M1
g m Dv
2
g m Dv
2
M2
vi1=+Dv/2
gm1=gm2=gm
i o vo
vi2=-Dv/2
1
Ro 
Go
1
Ro 
go2  go4
g m Dv
vo  io Ro 
go2  go4
A1 
vo
gm

Dv g o 2  g o 4
Second stage Low Frequency Differential Gain
VDD
Common source PMOS amplifier
with current source load
vi
M6
Ccomp
Vbias
M7
vo
vo
g m6
A2   
vi
go6  go7
Combined two stage differential response
gm
g m6
Av (0)  
go 2  go 4 go6  go7
W6
W
1
1
Av (0)    nCox I d 1
 p Cox
Id 6
L
I d 1 ( 2  4 )
L6
I d 6 (6  7 )
1
W
Av (0)   Cox
Id
L
1
n n
(2  4 )(6  7 )
For Id1=Id6
2
2
Av (0)  
(2  4 )(Vgsn  Vtn ) (6  7 )(Vgsp  Vtp )
For high gain either use small Id or large device dimension
Small Id impacts slew rate, large W/L impacts area and input capacitance
First stage Common mode Gain
VDD
M3
vc
M4
X
Y
M1
M2
Rs
gm1=gm2=gm
For matched devices
Vx=Vy, and hence
we can short these M3
vo
vc
VDD
M4
X
Y
M1
M2
Rs
gm1=gm2=gm
This brings M1 in parallel M2 and M3 in parallel M4
vo
Equivalent circuit for CM response
VDD
1
1

2 g m3 / 4  2 g o 2 g m3 / 4
vc
2gm1/2
This configuration now looks like
common source amplifier with
source degeneration Rs and drain
Resistance RD=1/2gm3/4
RD
1
Ac1  

Rs
2 g m 3 / 4 RS
RS
The second stage simply amplifies this further
The two stage common mode gain is
g m6
Ac  Ac1 Ac2  
2 g m 3 / 4 RS g o 6  g o 6
1
Common Mode Rejection Ratio
Ad
CMRR 

Ac
g m1
1
( g o1  g o 2 )
2 g m3 / 4 Rs
2 g m1 g m3 Rs
CMRR 
g o1  g o 2
CMRR is essentially determined by the first stage
High frequency equivalent circuit
v1
Cc
+
+
vi
-
gm1vi
GT1 =1/RT1 = go2+go
GT2 =1/RT2 =go6+go7
CT1=Cdb2+Cdb4+Cgs6
CT2=Cdb6+Cdb7+CL
CC=Cgd6+Ccomp
GT1 CT1
gm6v1
GT2 C
T2
vo
-
High frequency Response
Writing the nodal equations for equivalent circuit
and solving for the gain, we obtain poles and one zero
1
p1  
g m 6 RT 1 RT 2Cc
p1  
g m 6 Cc
g m6

CT 1Cc  CT 2Cc  CT 1CT 2 CT 1  CT 2
g m6
z1 
Cc
p1 needs to be made a dominant pole by appropriately
choosing the compensation capacitance
z1 is a positive zero that can impact stability
Pole splitting and choice of Cc
g m1
g m1
1
p1  

g m1 g m 6 RT 1 RT 2Cc
| Av(0) | Cc
Cc should be chosen such that the unity gain frequency
u << p2 to get adequate Phase Margin
Also for the single pole response (with p1), the unity
gain frequency is given by
g
u  m1
Cc
Cc 
g m1
u
Feed forward zero
The positive zero location is very close to u and
this will degrade the phase margin
g m6
z1 
Cc
If gm6  gm1 then z1  u
This zero should be cancelled, otherwise the system
becomes unstable
Zero cancellation with nulling resistance
Rz
Vi
Cc
i1 i2 V
o
Vo
R2 1  sCc ( R1  Rz )

Vi R1  R2  sCc ( R1 R2  R1 Rz  R2 Rz )
z1 
R1=-1/gm6
R2
z1 
1
Cc ( R1  Rz )
1
Cc (1 g m 6  Rz )
Qualitatively, adding Rz makes i2 weaker at any given frequency
compared to the value of i1 , i.e. the effect of feed forward zero
is suppressed
When Rz = 1/gm6 , the zero is at infinity
For Rz > 1/gm6 , the zero moves to the left half plane improving PM
(lead compensation)
Zero cancellation with PMOS
VDD
MB2
M6
vo
Mz
Cc
Vbias
The linear region Rz is
Vz
M7
The PMOS transistor Mz
is biased such that it is
in linear region
Vgs-Vt > Vds
MB1
RZ 
1
 nCox Wz L (Vgsz  Vtz )
z
For M6,
1
1

g m 6  Cox W6 (V  V )
n
L6 gs6 t 6
The RZ is able track 1/gm6 very well in spite of through process variations
OPAMP Performance Metrics
Slew rate
When a step input is applied,
in order for the output to follow
vo the input the capacitance Cc
should be charged to the new value
vi
Av
+
The maximum current that is
available to charge this capacitor
is the bias current Is
vi
vo
Hence the slew rate, i.e. the
dvo/dt(max)=Is/Cc maximum rate of change of
output is = Is/Cc
t
Random Input offset
Random offset arises due to transistor mismatch in the
supposedly matched differential pair (first stage)
The effect of offset is modeled as an input referred offset
voltage in series with the input terminal of ideal OPAMP
Vos  DVt1, 2  DVt 3, 4
g m3
g m1
W
 DW

D
(Vgs  Vt )1, 2 
L1, 2
L3, 4 


 W

W
2

L1, 2
L3, 4 

DVt1, 2  Vt1  Vt 2
Vt1  Vt 2
Vt 
2
D(W / L)  (W / L)1  (W / L) 2
W
L

W
L1
W
2
L2
Offset voltage in series
with the gate of M1
Systematic Offset
For matched M1-M2 and M3-M4
VDD/2
M3
g m Dv
2
M1
vi1
vi2+
Vbias
vi1=vi2=0 should give vo=0
What about relative sizing of
M3-M4-M6 and M5-M7 ???
M4
g m Dv
2
g m Dv
2
M2
M5
-VDD/2
M6
Ccomp
M7
vo
We need to ensure that:
Vgs6=Vds4=Vgs3=Vgs4
i.e. Current per unit W/L in these
Transistors should be identical
W L  W L  W L
W L W L 2W L
3
4
6
6
5
7
If this is not true then a systematic offset voltage results at the input
1/f noise
1/f noise
Noise
Power
Thermal noise
fc
f
Thermal noise is due to random fluctuation of carriers in a resistor
Higher bias current helps decrease thermal noise
The 1/f noise or flicker noise is due to interface states in MOSFET
fc is 1/f corner frequency in the range of 500KHz
Flicker (1/f) noise due to interface states
Flicker noise is due to trapping and detrapping of carriers
from the interface states
dangling bonds
Ids
Interface
covalent bonds
The random trapping and detrapping of carriers from the
channel creates fluctuations in drain current
K 1
vn 
CoxWL f
2
Noise varies as 1/A due to averaging effect
Noise varies as 1/Cox since the fraction of charge is less
Noise varies as 1/f since traps have certain time constant
MOSFET versus BJT
The BJT circuits are not affected by flicker noise!
metal
oxide
p
n+
p
p
n+
p
n+
np
The current flow path does not
encounter any kinds of defects
since the current flow is entirely
in the bulk of Silicon
Silicon
The current flow path is abutting
The interface defects region
Dual gate vs Single gate technology
• Historically CMOS technology had a single gate type
• Both NMOS and PMOS had n + poly-Si gate
• This was because the poly thickness was fairly large
(more than 0.5m) and it was difficult to activate
such poly using implant and annealing
• Hence in-situ doping (i.e. doping during deposition process
itself) was invariably used
• As a result both NMOSFET and PMOSFET had n+ gate
• Almost all the recent technologies use dual poly gate
i.e. n+ gate for NMOS and p+ PMOS
• The poly is fairly thin (0.2m or less) and hence the activation
is done during s/d implant and anneal step itself
The problem of PMOS Vt setting
Vt  V fb  2b 
Tox 4 s qN ab
 ox
The Vfb term depends on gate material
For NMOS with n+ gate, Vfb ~ -0.9V, 2b=0.7V, the third
term is positive for p- well And hence Vt can be set to low value
For PMOS with p+ gate, Vfb ~ +0.9V, 2b= -0.7V, the third
term is negative for n- well And hence Vt can be set to low value
For PMOS with n + gate, Vfb ~ -0.1V, 2b= -0.7V
hence Vt setting on n-well becomes very difficult
Hence in a single gate technologies the PMOS well was typically
counter doped to bring Vt to manageable levels. This process in turn
pushes the inversion layer away from interface
Buried vs Surface Channel PMOSFET
Buried channel PMOSFET
Surface channel PMOSFET
n+
oxide
p+
p+
oxide
p+
p+
n
p+
n
Silicon
Silicon
Current flows away from interface
Current flows at the interface
The flicker noise performance of buried channel PMOS
is similar to BJT with almost zero flicker noise
However the surface channel PMOS is no better than
the surface channel NMOSFET
Output Stage
Output stage requirement
Capable of providing high output current to drive large loads
However, the DC bias current should be low to avoid
Static power dissipation
The output impedance should be very low
Source follower can serve the purpose
Class AB NMOS and PMOS source follower
(push-pull) stage is a preferred configuration
Output stage class AB
VDD
vi
VGG1 and VGG2 are set such that
M1B and M2B are biased just
above Vt to avoid cross over
distortion
M2B
VGG2
vo
VGG1
vi
M1B
vo
M2B
M1B
Biasing the output stage
VDD
vi
M3B and M4B are diode connected
NMOS and PMOS respectivel
M6
M3B
X
Vxy = Vgs3b + Vgs4b
M2B
Vxy = Vtn3b + Vtp4b+2DV
vo
Y
M4B
Vbias
M7
M1B
Choose the sizes of M3B and M4B
such that Vxy is just above the
the two Vts of M1B and M2B to
avoid cross over distortion
Folded Cascode
+
M1
VB1
M2
MB
VDD
M10
M9
VB3
M3
M4
VB2
vo
M8
M6
M7
M5
The differential current due to inputs are folded through
M1-M3 and M2-M4 pairs
The gain will be comparable to 2 stage OPAMP due to
cascoding of the load transistor
The load capacitance itself acts as compensation capacitance
Folded cascode gain
Av (0) 
gm
g o 2  g o9
g o5

g m 4 ro 4
g m 7 ro 7

g m ro 
A ( 0) 
2
v
Assuming all gm and ro are identical
3
The dominant pole is associated with the output
CL provides frequency compensation
Increasing CL improves phase margin
OTA and OPAMP Circuits
Operational Transconductance Amplifier
OTA is essentially an OPAMP without an output buffer
An OTA without output buffer can drive only capacitive loads
OTA is an amplifier where all nodes except I/O are low
impedance nodes. Hence the two stage OPAMP configuration
minus buffer is NOT an OTA since the drain of M4 is high
impedance node
As the name suggests, the quantity of interest in OTA is
not the voltage gain, but it is
iout
iout
Gm 

vi 2  vi1 vi
The basic OTA circuit configuration
VDD
M8
M3
vi1 -
M4
M1
M2
1:K
+vi2
M9
M6
io
M7
1:K
Vbias
M5
Gm expression
Assumptions
gm1=gm2 and (W/L)3= (W/L) 4 = (W/L) 8
(W/L)6= K(W/L) 4 and (W/L)7= K(W/L) 9
Then
io  id 6  id 7  K (id 4  id 9 )  K (id 2  id 1 )
vi 
 vi
io  K  g m  g m   Kg m vi
2
2

i
Gm  o  Kg m
vi
Transconductance Gm
Gm can be set by appropriate K
For a given K (i.e. after design) Gm can still be varied
by setting an appropriate bias current, IS
i.e. Filters made using OTA can be tuned by changing IS
Output pole is the only dominant pole!
i.e. capacitive loads improve the phase margin
The symbol for OTA
IS
vi2
+
vi1
-
io
Simple Low pass filter
vo  io
vi
+
io
vo
1
j C
vo  Gm (vi  vo )
1
j C
Gm
-
vo
j C

vi 1  Gm
j C
vo
1

vi
 C 

1  j 
 Gm 
C
Single pole low pass filter with a cut off frequency of
p=Gm/C
Simple High pass filter
 Gm vo
vo  vi 

j C
j C
vo
1

vi 1  Gm
jC
io
+
vi
io
vo
C
j  C 
Gm 
vo


vi 1  j  C 
 G 
m

High pass filter with cut off frequency of
p=Gm/C
General biquadratic (biquad) configuration
v2
C1
v1
+
-
+
-
vo
C2
v3
Filter
Low-pass
High-pass
Band-pass
Input Condition
Transfer function
2
v1= vi , v2 = 0 ,v3 = 0
gm
v1= 0, v2 = 0 ,v3 = vi
s 2C1C2
v1= 0, v2 = vi ,v3 = 0
sC1 g m
Band-reject v1= vi , v2 = 0 ,v3 = vi
s 2C1C2  sC1 g m  g m
2
s 2C1C2  sC1 g m  g m
s 2C1C2  sC1 g m  g m
s 2C1C2  g m
2
2
2
s 2C1C2  sC1 g m  g m
2
Inverting and Noninverting amplifier
Inverting
R2
vi
R1
-
Av
+
Non inverting
vo
vo
R2
 1
vi
R1
R2
R1
vi
vo
vo
R2

vi
R1
Av
+
Integrator and Differentiator
Integrator
vi
C2
R1
-
Av
+
Differentiator
vi
vo
1
vo  
vi dt

R1C2
R2
C1
-
Av
+
vo
dvi
vo   R2C1
dt
Log and Antilog Amplifier
Log
+ vd -
R1
vi
-
Av
+
Antilog
vi
vo
vi
vo  VT ln
R1 I o
R1
+ vd -
-
Av
+
vo
vo   I o R1e
vi
vT
Wide Common Range OPAMP
Common mode range for differential amplifier
RD1
RD2
vo1
vi1
Id1,Id2
Vo1,Vo2
VDD
vo2
M1
M2
vi2
IS/2
VDD-ISRD/2
0
Vt
Vt+DV1/2+DV3
Vci
IS
Only the lower limit of Vci is the
hard limit and is above negative rail (0V)
|Av|
We presumed the upper limit also to be
much below positive rail (VDD) due
to IsRd/2 drop
Vt
Vcmin
Vcmax VDD
Vci What if you replace the load RD
with current source load?
The common mode range with current source load
VDD
VB
M3
|Av|
M4
vo1
vi1
vo2
M1
IS
M2
vi2
Vt
Vcmin
VDDVcmax
The Vcimax will be even greater VDD!
However the Vcimin is the hard limit
Vci
Common Mode Range for NMOS and PMOS
VDD
VB
M3
vo
vi11
M1
M4
VDD
VDS
IS
CMR
vi1
vo2
M2 vi2
M5
M6
vo1
IS
VDS
VGS
vo2
VGS
VB M7
vi2
M8
CMR
Vc
Combine NMOS and PMOS input differential pair to
obtain rail to rail common mode range, Vci !
(In fact the CMR Could be even beyond rail to rail)
The rail to rail input stage
VDD
IS1
vi1
M3 M4
M1
vi2
M2

To summing circuit
using current mirror
IS2
Low common mode input : Only P-type diff pair operates
Intermediate common mode input: Both N and P-type operate
High common mode input : Only N-type diff pair operates
The variation of the first stage gain
N and P-pair
2gm
gm
N-pair
P-pair
0
Vt
VDD-Vt
VDD
Vci
For the simple circuit, the first stage gain is not constant
over the common mode input range
Additional circuit is required to maintain the constant gain
The concept of gain control
Suppose that N and P pair bias current is constant and
N and P transistors are sized to match the transconductance
k n I S  k p I S  kIS
When both pairs are active the transconductance gets added
Gm  2 kIS
If we like to maintain the same transconductance when either
N or P differential pair is switched off, then we need to change
the active pair bias current using some circuitry
Gm  kn 4 I S  2 kIS
Gm  k p 4 I S  2 kIS
Increase N bias current by a
factor of 4 when only N is active
Increase P bias current by a
factor of 4 when only P is active
The first stage with gain control
M6
1:3
M7
VDD
+
V
- R1
IS1
M8
vi1
M3 M4
M1
vi2
M2
M5
+
VR2
-
IS2
M9
1:3
M10
VR1 and VR2 are chosen slightly above Vt of M5 and M8
The current switching
For low Vci i.e Vci < Vt
M8 is OFF and M5 is ON  IS2 flows through M5
The current mirror M6-M7 multiplies IS2 by a factor
of 3 onto the drain of M7. This is added to IS1, thereby
increasing The P bias current by a factor of 4
For high Vci i.e Vci > VDD – Vt
M5 is OFF and M8 is ON  IS1 flows through M8
The current mirror M9-M10 multiplies IS1 by a factor
of 3 onto the drain of M10. This is added to IS1, thereby
increasing the N bias current by a factor of 4
For intermediate Vci i.e Vt < Vci < VDD – Vt
M5 is OFF and M8 is OFF  Current mirrors are disabled
N bias current = P bias current = Is
The corrected gain
P-pair
N and P-pair
N-pair
2gm
gm
0
Vt
VDD-Vt
VDD
Adding current switching makes the differential gain
almost flat over the common mode range
Vci
Bulk Driven OPAMP
The dead zone problem in
complementary input stage
Suppose that supply voltage is very small VDD < VGSn+VGSp+2DV
CMR
VDS
VGS
N-Pair
Active
DEAD
ZONE
VGS
VDS
CMR
P-Pair
Active
Then there is a dead zone in Vc range!
Both the pairs are deactivated and no useful operation
Overcoming the Vt problem in single stage
N and P stages are inherently limited by the fact that the
gate voltage should be more than Vt to turn on the transistor
Possible remedy:
Fix the gate voltage above Vt and apply the inputs
to the body of the transistor (bulk driven)
Modulating the body voltage results in change in Vt
and hence gives rise to body effect transconductance
Which is used to operate on the input signals
Note: At the higher range of input common mode voltage
significant junction leakage may result
VBS
The bulk driven NMOS
Vg = VDD
p+
n+
VDD
VDD
n+
n+
electron channel
p-well
n-substrate
Id
Bulk driven MOSFET can
be viewed like a JFET
Bulk-source
Driven MOS
Vgs=1.5V
-2 -1 0
Gate-source
Driven MOS
Vbs=0V
1
Vgs or Vbs
Parasitic BJTs are not
turned on
The transistor is ON even
when the input VBS=0
Bulk driven NMOS first stage
VDD
VB
M3
Rail to rail Vci is possible
M4
vo1
vi1
M1
M2
Gm is not constant over the Vci range
vo2
vi2
If the supply voltage is less than 1V
then the maximum forward bias of
junction would be about 0.5V
IS
Note that body effect is active even
when body to source voltage is
forward biasing the junction
Need for Statistical Design and Simulation
The Order of Variability
Intrachip
Intrawafer
Interchip
Interwafer
Interwafer and interchip variation results in distribution of chip speed
Intrachip variation impacts functionality of the chip
Short Range and Long Range Order
Inter chip, Inter wafer and Inter lot variations have long range order
Intra chip variations can be medium and short range
The variation along a clock tree has medium range order
The variation in matched differential pair is short range order
SPICE corner models are derived from long range order and
they will be very pessimistic for short range order
Typically the intra die variation of a parameter P between
two transistors M1 and M2 is given by
 ( P1  P2 ) 
2
ap
2W1 L1

ap
2W2 L2
 s p D12
2
2
2 is variance, D12 is distance between M1-M2, ap and sp are
Process technology dependent
Short Range Order is Crucial for
Matched Transistors in Analog Design
Variation in Vt
(long range)
Frequency (#)
Vt)
Vt
Vt)
Frequency (#)
Variation in DVt
(short range)
Frequency (#)
DVt
0
DVt
0
DVt
Mismatch Coefficient
qTox 2 NWd
AVT
DVt 

WL
 ox WL
W is width of transistor , L is length of transistor
DVt
0.2/4
2/0.18
5mV
0.18m technology
0
1
WL
The equation is obeyed very well except at the edge of the
Process technology
Technology Scaling Trend
VDD
V
Signal amplitude
6DVt
1m
Technology
0.1m
• The parameter matching is becoming difficult with scaling
• 6DVt has become appreciable fraction of power supply
Yield versus Mismatch
ADC
SRAM
100
100
Yield
Yield
10 9 8
bit bit bit
7
bit
600MHz
800MHz
0
0
0
6mV
DVt
DVt
• High precision and high speed require very low mismatch
•The mismatch problem should be tackled in both
Process Technology and Circuit Design domains
Pessimistic design with Worst Case
Process corners SPICE models
If the corner parameters are used to simulate the
worst case mismatch effect, the design will be
pessimistic
As a designer, in order to do a reliable as well
as high performance design, obtain the
matching data as well from the fab
It does take quite a bit of effort for the fab to generate
mismatch data, but it would be worth the effort
from designer’s viewpoint
Statistical circuit simulation
Ideally the statistical design/simulation should be
part of the design flow for analog circuits
Process
Statistical
Parameter
Extraction
Normal Ckt
Parameter
Extraction
Design/simulation
With normal parameters
PVT, except short range
Statistical
Simulation
Measured
Yield
Yield Prediction
Monte Carlo Technique
Statistical technique used to predict the output
distribution when there is no closed form
expression relating output distribution to input
Random number generation is used to randomly
assign a value to input variables and walk through
the input to output transformation
By transforming a large set of inputs to the output
the output distribution is obtained
Response surface methodology using DOE
For a complex circuit the SPICE simulations
in the Monte Carlo loop become computationally
inefficient
By performing very few input to output transformation,
a mathematical model could be fit to relate the output
quantity to the input (linear, quadratic or some other
function)
This model replaces SPICE simulations from MC loop
Computational efficiency is enhanced significantly
Acknowledgements
For
The Material and PPTs Used in this course
(1)Prof. A.N. Chandorkar
IIT, Bombay
(2)Dr. Navakant Bhat
IISc Bangalore
(3) Prof.Behzad Razavi
UCLA,Los Angeles
Analog CMOS VLSI Design,McGraw-Hill
(4) Prof. J.Vasi
IIT Bombay
(5) Prof. Dinesh Sharma
IIT Bombay
(6) Profs.R.J. Baker, H.W.Li and D.E. Boyce
Dr. Navakanta Bhat