Transcript here

Introduction to FPGA and
DSPs
Joe College, Chris Doyle,
Ann Marie Rynning
Field Programmable Gate Arrays
Architecture
Logic Block
Interconnection
Input/Output
Switch Box
Connect Block
3
Architecture
• Logic Block Options
– Transistor pairs
– Basic small gates (such
as two-input NAND’s or
exclusive-OR’ s)
– Multiplexers
– Look-up tables (LUT’s)
– Wide-fanin AND-OR
structures
Logic Block
Interconnection
Input/Output
Switch Box
Connect Block
• Granularity
4
Architecture
Logic Block
Interconnection
Altera’s Stratix II ALM
Input/Output
Switch Box
Connect Block
5
Architecture
Logic Block
Interconnection
Xilink’s Virtex 4
Input/Output
Switch Box
Connect Block
6
Architecture
• Routing Options
– From nearest neighbor
mesh to much more
complex, like that in
multiplexers
– Wire segments of
varying lengths
Logic Block
Interconnection
Input/Output
Switch Box
Connect Block
• Delay Considerations
• Density Considerations
7
Architecture
Logic Block
• Provide programmable
multiplexers signals
• Connect shorter local
wires to longer-distance
routing resources
Interconnection
Input/Output
Switch Box
Connect Block
8
Architecture
Logic Block
• Used to change the
direction of a signal
Interconnection
Input/Output
Switch Box
Connect Block
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Programmable Switch Technology
• SRAM
• Antifuse
• EPROM
Control Pass Gate
SRAM
Cell
SRAM
Cell
0
1
Multiplexer
0 or 1
MUX
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Programmable Switch Technology
• SRAM
• Antifuse
• EPROM
Disadvantages
Volatile
External Permanent Memory Required
Large Area Required
Advantages
Reprogrammable, easily and quickly
Requires only standard integrated circuit
process technology (as opposed to
Antifuse)
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Programmable Switch Technology
• SRAM
• Antifuse
• EPROM
0
1
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Programmable Switch Technology
• SRAM
• Antifuse
• EPROM
Disadvantages
Not reprogrammable; links made are
permanent
Requires extra circuitry to deliver
the high programming voltage
Advantages
Small size
Relatively low series resistance
Low parasitic capacitance
13
Programmable Switch Technology
Bit Line
Word Line
Control Gate
Oxide Layer
Floating Gate
--
Drain
1
Source
Word Line
Bit Line
• SRAM
• Antifuse
• EPROM
-------
Drain
Control Gate
Oxide Layer
Floating Gate
0
Source
14
Programmable Switch Technology
• SRAM
• Antifuse
• EPROM
Disadvantages
High resistance of EPROM transistors
High static power consumption
UV light exposure needed to reprogram
Advantages
No external memory required; retains
memory even without power
Reprogrammable
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FPGA Producers
Major Producers
Smaller Producers (specialty)
21
Digital Signal Processors
Brief History of DSPs
1978
1979
1980
Today
23
Analog Blackfin
•
•
•
•
DSP
RISC MCU
Dual core
Clock control
25
Analog Blackfin
•
•
•
•
Fast MAC
Parallelism
Pipelines
Close/fast
storage
• Multiple
memories
• High-bandwidth
buses
• External
interface
26
Analog Blackfin
•
•
•
•
Fast MAC
Parallelism
Pipelines
Close/fast
storage
• Multiple
memories
• High-bandwidth
buses
• External
interface
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Analog Blackfin
•
•
•
•
Fast MAC
Parallelism
Pipelines
Close/fast
storage
• Multiple
memories
• High-bandwidth
buses
• External
interface
28
Analog Blackfin
•
•
•
•
Fast MAC
Parallelism
Pipelines
Close/fast
storage
• Multiple
memories
• High-bandwidth
buses
• External
interface
29
Analog Blackfin
•
•
•
•
Fast MAC
Parallelism
Pipelines
Close/fast
storage
• Multiple
memories
• High-bandwidth
buses
• External
interface
30
Analog Blackfin
•
•
•
•
Fast MAC
Parallelism
Pipelines
Close/fast
storage
• Multiple
memories
• High-bandwidth
buses
• External
interface
31
Analog Blackfin
•
•
•
•
Fast MAC
Parallelism
Pipelines
Close/fast
storage
• Multiple
memories
• High-bandwidth
buses
• External
interface
32
Analog Blackfin
•
•
•
•
Fast MAC
Parallelism
Pipelines
Close/fast
storage
• Multiple
memories
• High-bandwidth
buses
• External
interface
33
Analog Blackfin
•
•
•
•
DSP
RISC MCU
Dual core
Clock control
34
Analog Blackfin
•
•
•
•
DSP
RISC MCU
Dual core
Clock control
35
Analog Blackfin
36
Analog Blackfin
•
•
•
•
DSP
RISC MCU
Dual core
Clock control
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Analog Blackfin
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ASIC vs. µP vs. Reconfigurable
• Application Specific Integrated Circuit
– Designed to perform a specific computation
– Circuit cannot be altered after fabrication
• Software Programmed Microprocessors
– Modification with software
– Slower than ASICs
• Reconfigurable Computing
– FPGAs and DSPs
– Easily modifiable
– Larger Area
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Comparison
•
•
•
•
•
•
Virtex-4 FPGA
Xilinx
500 MHz Processor
18-Bit MACS
48-Bit Accumulator
Up to 1392K Bytes of
On-Chip Memory
• Brand-New
•
•
•
•
•
•
Blackfin DSP
Analog Devices
600 MHz Processor
Two 16-Bit MACS
40-Bit Accumulator
308K Bytes of OnChip Memory
• Somewhat Older
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Comparison Criteria
•
•
•
•
•
•
•
Performance – MIPS, MMACS, MHz
Price
Development Tools
Supply Voltage
Implementation Time
Flexibility
Most Importantly: Comfort Level
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FPGA: Virtex-4 DSP Slice
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FPGA: Virtex-4 DSP Slice
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DSP: Blackfin Processor Core
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DSP: Blackfin Processor Core
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DSP: Blackfin Processor Core
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How to Use and Program an FPGA
•
•
•
•
•
•
Write HDL code
Generate Netlist
Place and Route
Generate Binary File
Power On FPGA
Configure FPGA
• Verilog
• VHDL (Very High Speed
Integrated Circuit
Hardware Description
Language)
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How to Use and Program an FPGA
•
•
•
•
•
•
Write HDL code
Generate Netlist
Place and Route
Generate Binary File
Power On FPGA
Configure FPGA
• Lists components that are
connected to each other
• Lists connections between
components, power, and
ground
51
How to Use and Program an FPGA
•
•
•
•
•
•
Write HDL code
Generate Netlist
Place and Route
Generate Binary File
Power On FPGA
Configure FPGA
• Often performed by the
FPGA company's
proprietary software
• Determines which logic
blocks to use for each part
of the program, to optimize
• User validates
52
How to Use and Program an FPGA
•
•
•
•
•
•
Write HDL code
Generate Netlist
Place and Route
Generate Binary File
Power On FPGA
Configure FPGA
• Often performed by the
FPGA company's
proprietary software
53
How to Use and Program an FPGA
•
•
•
•
•
•
Write HDL code
Generate Netlist
Place and Route
Generate Binary File
Power On FPGA
Configure FPGA
• FPGA is initially in
configuration mode
54
How to Use and Program an FPGA
•
•
•
•
•
•
Write HDL code
Generate Netlist
Place and Route
Generate Binary File
Power On FPGA
Configure FPGA
• Cable from your PC to the
FPGA
• Use a microcontroller on
your board
• Use a "boot-PROM" on
your board, connected to
the FPGA
55
Using DSPs
• C/C++/Assembly
• Lots of development environments
• Documentation
– Interfacing
– Common operations
– Porting
56
Using DSPs
• C++/Assembly
• Lots of development environments
• Documentation
– Interfacing
– Common operations
– Porting
57
Using DSPs
• C++/Assembly
• Lots of development environments
• Documentation
– Interfacing
– Common operations
– Porting
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Comparison Chart
Performance
Price
Development
Voltage
Implement Time
Flexibility
Virtex-4
Blackfin
500 MHz
350 MHz
$495
HDL
1-1.6V
Higher
Higher
$350
C++/ASM
1-1.2V
Lower
Lower
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