Transcript PPT - Dept. of Electrical and Computer Engineering

Major Blocks and Peak Detector Sections of Channel Equalization Techniques for Ethernet
Communication Systems
Lizhuo Wang
Dr. Jose Silva-Martinez
Undergraduate Student
Texas A&M University
Undergraduate Summer Research Grant Program
Department of Electrical Engineering
Texas A&M University
Assistant Professor
Texas A&M University
ABSTRACT
Peak Detector
Buffer and Error Amplifier
Fast communication signals sent from one computer to another
across the lines of transmission are degraded because of the
reflection at the receiver. It is shown that equalizing the
impedance at both ends will further improve the data
transmission.
The peak detector circuit is show below.
The acquired peak values from the pervious stage will be
compared by subtracting each other in a differential amplifier
circuit.
 It will connect to the peak detector stage where a DC
voltage is held. So a buffer is needed.
The signal input is provided at the left side, while output includes the peak value of the
AC amplitude and the DC component brought by the transistor.
a symmetrical structure with low pass filters is implemented to eliminate the DC effect.
A control loop using an active impedance matching device
based on a chip solution is a feasible solution, which could save
hundreds of thousands of dollars over the lifetime of a single
product line and millions of dollars in all.
 PMOS transistor for bringing the gate impedance
 The values in filters are not
required to be reasonable for
on-chip design because the
reference part on the right will
not be put onto chips
the main idea is to compare the voltage difference between the
two ends of the transmission line and minimize the value by
adjusting the impedance at both ends based on the value of the
difference as a feedback.
 the minus end of the ideal amplifier is connected to a
DC supply voltage around the input level.
The project targets on designing fundamental building blocks,
and mainly focuses on the peak detector part.
The early design of the peak detector
with reference counterpart.
DESIGN
The differentiation building block
The figure on the right shows that the output
difference from the peak detector has the ability
to track the input amplitude.
Applications
Both amplifier output and detector outputs are graphed below.
Matched perfectly = this stage works properly!
Comparison of the peak detector
transfer characteristic as determined
by Cadence simulations,
measurements at 80M Hz
The latest version of the peak detector building
block is shown on the left.
*Pictures from Mr. Richard
Kamprath’s Master Thesis
No need for the DC reference part in the end.
Large Capacitor for small ripples.
Transmission Line Model
Peak detector building block
The transmission line circuit
block used in Cadence
The schematic
of the whole
circuit
It is clearly shown in the right side graph that the
difference of the peak values between the two
wave signals is presented, which means it is
functional as peak detectors.
CADENCE SIMULATION RESULTS: The signal degradation is
minimized when both the emitter and receiver capacitances are
around 1/3 of the capacitance of the transmission line capacitance in
the T-model.
Outputs of the peak detector stages
 To prove that the difference between
detected values and the difference
between real peak values have a direct
relationship.
 Plotted with several sets of simulation
results
Magnitude: capacitance
as parametric sweep
Group delay with the
parametric simulation
Plot of real peak difference vs. detected
difference with the input signal
amplitude from 40mV to 300mV
 A direct relationship, which means the
detection will surely make sense and can
be used for later stages.
CONCLUSION AND FUTURE WORK
The transmission line model, peak detector and error amplifier
building blocks for on-chip matching component of the
Ethernet communication system are scratched out. It will
connect to a A/D converter and a control part to adjust the
ends capacitances in the transmission line stage.