Transcript ppt
The Lab DAQ system + Brief reminder of the requirements • To be used as an alternative to the IC Tester • Easily reproduceable • Manual or Computer operation • Of all Voltage settings • Interface between the Pixel Readout Chip and DAQ • Use in test beam therefore use with long cables Mike BURNS CERN-ALICE CERN, 20 September 2000 1 Specifications + + + + + Voltages variable up to 2.56 V • @ approx.. 4 A for supplies • @ 100’s of mA for biases • with 8 bit resolution • test voltage level 12 (11) bit resolution LVDS (differential transmission) connection to Pilot Module for all DAQ signals GTL interface to Pixel Readout Chip Multiplicity ‘encoding’ • LVDS output to be read by a separate system • can also be read via control JTAG Fast OR • read out via control JTAG Mike BURNS CERN-ALICE CERN, 20 September 2000 2 Specifications & Status + + + + 2 independent JTAG ports • control JTAG • Pixel JTAG BS testable to all Pixel devices Design almost finished • PCB art work finished but awaiting final checks • Design of electronics almost finished We should have a board in 4 weeks Mike BURNS CERN-ALICE CERN, 20 September 2000 3 Block Diagram of DAQ adapter board Data bus [15:0] 16 Bit Data Register DAC Outputs Control bus [n:0] Tms Function Decoder DACs 8 Bit Instruction Register ADCs Tck Tdi Tdo CONTROL Mult[9:0] ADC Ready Fast OR I to V Tdo Data[31:0] RO Clk Register CS[9:0] Delay Tck Tdi Tdo Pixel JTAG Tdi Trst Tms PIXEL JTAG Data[31:0] CS[9:0] RO Control Test Pulse Pixel Databus Tck Test Pulse MISC. TTL/GTL Level Adaptors Tms RO[n:0] Fast OR BS cells Pixel JTAG Trst Pilot Module Multiplicity TTL/GTL Level Adaptors Multiplicity Control JTAG Trst RO Clock Feed Back PILOT INTERFACE Mike BURNS CERN-ALICE CERN, 20 September 2000 4