Transcript Development of Readout ASIC for Pair

Development of Readout ASIC
for Pair-monitor
2009/06/29
Yutaro Sato
Tohoku Univ.
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Pair-monitor
Pair-monitor is a silicon pixel detector
e+
to measure the beam profile at IP.
e+ beam
IP
• The distribution of the pair B.G. is used. e- beam
e– The same charges with respect to the
oncoming beam are scattered with large angle.
– The scattered particles have information on beam shape.
• The location will be in front of the BeamCal.
Y [cm]
Distribution of pair B.G.
1σx (nominal)
2 σx
Y [cm]
LumiCal
BeamCal
BeamCal
Pair-monitor
X [cm]
X [cm]
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Content
Tohoku group has developed
– development of the readout ASIC for the pair-monitor .
– performance study of pair-monitor .
• The readout ASIC for the pair-monitor was developed.
– The operation test of the prototype ASIC was performed.
• The bare chip of the new prototype which uses the SOI technology
was delivered.
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Development of the readout ASIC
The readout ASIC for the pair-monitor was developed.
Design concept of readout ASIC
• Pair-monitor measures the hit distribution of the pair B.G..
• Measurement is done for 16 parts in one train
for the time-dependent measurement.
− 16 hit counts are stored at each part.
− Count rate : < 2.5 MHz / (400μm x 400μm)
− Information of the energy deposit is not necessary.
• Data is read out during inter-train gaps. ( ~ 200 msec )
Beam structure
1 train = 2625 bunches
2
16
1 msec
~
~
1
……
[
[
[
…………………
200 msec
→ The prototype readout ASIC was designed to satisfy these concepts.
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Design of readout ASIC
Layout of prototype ASIC
Design of readout ASIC
• 36 (6 x 6) readout pixels
– Amplifier
– comparator
– 8-bit counter
 to hit a number of hits
– 16 count-registers
 to store hit counts
• Shift register
 to select a pixel from 36 pixels
Readout pixel
Input
Amplifier
8-bit counter
comparator
Count register
x 16
Output
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Prototype of Readout ASIC
The prototype of the readout ASIC was developed.
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•
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•
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0.25 μm TSMC process
Chip size : 4 x 4mm2
# of pixel : 36 ( = 6x6 )
Pixel size : 400 x 400 μm2
Sensor will be bump-bonded to the ASIC.
The chip was packaged in a PGA144.
→ The production of the readout ASIC
was done in Oct. 2008.
4mm
4mm
Prototype ASIC
Readout cells
Packaged ASIC
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Test system
The operation test was performed.
Test system
• GNV-250 module was used for the operation and readout .
– KEK-VME 6U module
• The test-sequence by GPIO is controlled by a PC.
FPGA
Test-board
GPIO
FIFO
Readout ASIC
Hit count
Hit count
Operation signals
Register switching
PC
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Response of amplifier block (Ⅰ)
The response of the amplifier block was checked.
Readout pixel
Input
Amplifier
Pre-amp.
Comparator
Threshold
block
8-bit counter
Count registers
x16
Output
Differentialamp.
Output from differential-amp.
Output from pre-amp.
TP timing
TP timing
→ The output signals were observed.
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Response of amplifier block (Ⅱ)
TOT [ns]
TOT (Time Over Threshold) characterization was checked.
Injected charge dependence
• TOT increases according to injected charge.
High charge
Low charge
TOT
Feedback current dependence
• TOT decrease according to feedback current.
High feedback
Low feedback
Injected charge [e-]
TOT [ns]
threshold
threshold
→ The amplifier block works correctly.
Feedback current [μA]
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Response of counter block
The response of the counter block was checked.
Readout pixel
Input
Amplifier
Comparator
8-bit counter
TP timing
Q1
Gray code is used.
Q2
Q3
→ The counter block works correctly.
Count registers
x16
Output
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Readout of hit counts
Readout pixel
Input
Amplifier
Comparator
switch
Count registers 1
Count registers 2
…
8-bit counter
Count registers 16
Readout
# of readout hit counts
Readout of hit counts was checked.
• The hit count was stored at 4 MHz hit rate/ (400μm x 400μm)
and read out from the count registers.
No bit-lost!
@ 4MHz
# of input TP
The correct hit counts were read out from count registers.
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Noise characteristics
Efficiency
Threshold scan was performed to evaluate the noise level of the chip.
• A lot of test pulses at a given charge were injected
and count the number of hits versus threshold voltage.
• Equivalent Noise Charge was evaluated.
→ 600 electrons or less
( gain is 1.6x10-3 [mV/e]. )
Error
function
Noise
Threshold
Threshold voltage [mV]
Noise level is much smaller than typical signal level ( ~20,000 e ).
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Response to signals from pin photodiode
The response of the chip to signals from pin photodiode was checked.
• The pin photodiode was connected with the chip as a sensor.
and was lit up by the LED.
Output from diff.-amp.
Output from diff.-amp.
Input voltage to LED
Input voltage to LED
Output from diff.-amp.
Input voltage to LED
The amplified signals were observed successfully.
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Pair-monitor with SOI technology
SOI (Silicon On Insulator) technology is used
for development of the pair-monitor.
SOI pixel detector
• The sensor and readout electronics are integrated
in the SOI substrate. (monolithic)
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–
–
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High speed
Lower power
Thin device
Low material
Development of the Pair-monitor with SOI technology was started,
participating in MPW (Multi Project Wafer) Run at KEK.
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Prototype of SOI chip
For the next prototype, only the readout ASIC will be developed.
Prototype ASIC
2.5 mm
• FD - SOI CMOS 0.2 μm process
• Chip size : 2.5 x 2.5 mm2
• # of pixel : 9 ( = 3 x 3 )
• Design of the ASIC is modified a little.
– Pole-zero cancellation
– One comparator → Two comparators
– TOT circuit → RC circuit
The bare chip of the readout ASIC was delivered.
The operation test will be started in Aug.
Layout of readout ASIC
2.5 mm
Bare chip (50pcs)
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Summary
• Pair-monitor is a silicon pixel detector
to measure the beam profile at IP.
• The prototype of the readout ASIC was developed.
– All the ASIC components were confirmed to work correctly.
– The noise level was estimated as 600 electrons or less.
– The chip responded to the signals from the pin photodiode
successfully.
• The next readout ASIC will be developed with SOI technology.
− The bare chip was delivered.
− The operation test will be started in Aug.