Transcript The Effect of Voltage Fluctuations on the Single Event Transient

The Effect of Voltage Fluctuations on the
Single Event Transient Response of Deep
Submicron Digital Circuits
Matthew J. Gadlage 1,2, Ronald D. Schrimpf 1, Balaji Narasimham1,
Bharat L. Bhuva1, Paul H. Eaton3, and Joseph M. Benedetto4
1
Vanderbilt University, Nashville, TN
2 NAVSEA Crane, Crane, IN
3 Microelectronics Research and Development
Corporation, Albuquerque, NM
4 Microelectronics Research and Development
Corporation, Colorado Springs, CO
2007 MURI Review
Outline
• How will voltage
fluctuations affect
single event
transients pulse
widths?
• Data from two
unique test chips
will be presented
• Simulations along
with a simple model
will be used to
explain the
experimental results
2007 MURI Review
[1] Harris, D.; Naffziger, S., "Statistical clock skew modeling with data
delay variations," IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, vol.9, no.6, pp. 888-898, Dec 2001.
June 15, 2007
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Motivation
• Voltage drops in
advanced CMOS devices
are a major concern
among circuit designers
• Mostly due to simple IR
drops
• Expected to become a
more significant issue as
technologies scale [2]
2007 MURI Review
[2] Ajami, et. al., "Analysis of IR-drop scaling with
implications for deep submicron P/G network designs,"
Fourth International Symposium on Quality Electronic
Design, 2003, pp. 35-40.
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Background
• The probability of a digital
single event transient
(DSET) causing an upset
depends on its width
• Delay based circuit
techniques have been
developed to eliminate
DSETs
• Heavy ion induced SET
pulse widths in advanced
technologies can be as wide
as 1 ns
Illustration Detailing the Significance of SET Pulse Widths [3]
[3] Mavis, D.G., Eaton, P.H., ”Soft error rate mitigation techniques for modern
microcircuits,” Reliability Physics Symposium Proceedings, 2002. Pages: 216-225.
2007 MURI Review
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Two DSET Test Chips
DICE (Dual Interlocked
Cell) Test Chip
SET Measurement
Test Chip
• Consists of a chain of DICE
latches with inverters
between each latch
• SETs are induced in a large
target circuit of inverters
• Immune to static upsets
• All upsets with this device
are due to SETs
• To be described in more detail…
• This device measures the SET
pulse width
• Both devices were fabricated on a 130 nm IBM technology through MOSIS
• Heavy ion testing was performed at Lawrence Berkeley National Labs
2007 MURI Review
June 15, 2007
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Two DSET Test Chips
DICE (Dual Interlocked
Cell) Test Chip
SET Measurement
Test Chip
• Consists of a chain of DICE
latches with inverters
between each latch
• SETs are induced in a large
target circuit of inverters
• Immune to static upsets
• All upsets with this device
are due to SETs
• To be described in more detail…
• This device measures the SET
pulse width
• Both devices were fabricated on a 130 nm IBM technology through MOSIS
• Heavy ion testing was performed at Lawrence Berkeley National Labs
2007 MURI Review
June 15, 2007
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DICE Chip Data
1.2 V
1.5 V
1.0 V
2.0 V
130 nm DICE Chip Schematic
• Significant increase in cross
section from 2V to 1V
• Average SET width
increases with decreasing
voltage
2007 MURI Review
DICE Chip Data at an LET of 68 MeV-cm2/mg
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SET Pulse Width Measurement Chip
nth stage
Target Circuit –
array of
inverters/
NAND/NOR
Latch
Latch
Latch
Autonomous or
self-triggered
SET pulse
measurement
Latch
Latch
CONTROL SIGNAL
• SET width measured in units of inverter delays
• Target circuit separate from measurement circuit
• Trigger signal is actually taken from first stage (shown here as nth stage for clarity) and
delayed in time to allow SET pulse to propagate down the measurement circuit stages
• Target circuit – array of inverters – as they produce long transients with little
attenuation
2007 MURI Review
June 15, 2007
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Ave. SET Pulse Width (ps)
SET Pulse Width Measurement Data
• Slight variations in voltage
result in a wide variation in
SET pulse widths
900
800
• An ~8% decrease in VDD
created a ~33% increase in
the SET pulse width
700
600
500
• An increase in SET width
will result in a proportional
increase in the error cross
section in the combinational
logic of a circuit
LET = 31 MeV-cm2/mg
LET = 58 MeV-cm2/mg
400
1.05
1.10
1.15
1.20
1.25
Supply Voltage (V)
SET Pulse Width Measurements vs. Supply Voltage
2007 MURI Review
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SPICE Simulations
• ~3X increase in SET width from
2V to 1V
Strike Here
Measure
SET Width
Here
• Input was a constant double
exponential current pulse
• Varied the supply voltage
Pulse Width (ns)
• A few tenths of volt can change
the SET width significantly
2
1
Below
Operating
Spec.
0
1
• Measured the SET width after
10 inverters
2007 MURI Review
0.13 um IBM
2
Voltage (V)
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Near the SET Threshold…
Pulse Width (ps)
400
0.13 um IBM
300
• SET threshold is the
smallest LET at which a
transient will be created
• An IR drop of only a few
mVs can change the
threshold value
200
• The SET threshold in a
modern device may be
near that of an alpha
particle
100
0
1.10
1.12
1.14
1.16
1.18
1.20
Voltage (V)
SPICE Simulation Near the SET Threshold
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R
1
  (VDD  VT )
Time Constant
  RC
2
2
1.5
1.5
1
1
0.5
0.5
0
RC Time Constant
(Arb. Units)
MOSFET Resistance
Pulse Width (ns)
MOSFET RC Model
0
0.5
1
1.5
2
2.5
Voltage (V)
Lower VDD => Larger Time Constant => Slower Circuit => Longer Transients
2007 MURI Review
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Implications
• Took an extreme case of IR drop
from a microprocessor [1]
600 ps
800 ps
800 ps
> 1 ns?
600 ps
600 ps
• Plotted the supply voltage variation
as a function of die location at a
given time
• The approximate pulse width from
the SET measurement chip is
shown in each contour region
• Different locations on a die can
have different SET pulse widths
(or different error cross sections)
[1] Harris, D.; Naffziger, S., "Statistical clock skew modeling with data
delay variations," IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, vol.9, no.6, pp. 888-898, Dec 2001.
2007 MURI Review
June 15, 2007
13
Conclusions
• Data from two unique test chips were
presented to illustrate the effect of
voltage fluctuations
• Small variations in voltage can
significantly increase single event
transient pulse widths
• Has the potential to become a more
significant issue as devices continue to
scale
2007 MURI Review
June 15, 2007
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