Transcript Modeling of On-chip Variation - Computer Science and Engineering

“Location Based On-Chip Variation”
Rasit Onur Topaloglu
University of California San Diego
Computer Science and Engineering Department
Ph.D. candidate
www.cse.ucsd.edu/~rtopalog
Outline
•Motivation
•Process model
•On-chip variation model
•Validation methodology
•Experimental Results
•Conclusions
Motivation
•Currently static timing analysis tools neglect cell locations
Cell locations contain a valuable systematic information
•Process variations, if not considered properly, may cause chip
to fail or prone designs to be impossible to attain a spec.
Increases design time and reduces yield
Oxide Distribution on Wafer
30cm wafer, 0.13m, SEM
Oxide distribution seems to be circular & continuous
Ref: Intel Technology Journal, Vol. 06, Issue 2, May 2002
Process and OCV Models
Modeling of Process Variations : “Volcano Model”
Equ-speed circles on wafer
Cell speed
Cell speed
1.05
1.15
Distance from center
Distance from center
•Variation curves are circular
•Linearly increasing or decreasing cell speeds along radius
•Effects such as oxide variation, threshold voltage variation,
lumped as cell speed variation
Modeling of On-chip Variation : “Angular Model”
•Chip may fall anywhere on wafer
Process curves on chip
chip1
1
2
-model
-real
C
1
chip2
•On-chip variation available as std. dev. only
Assumption :  max. on-chip speed
variation
•Since chips are small, circle arcs approximated to be straight lines
•Cell speeds will be effected depending on angle wrt wafer center
Location of Chip Matters

C
•Equ-lines are taken to be parallel to each other and normal to the line
that connects wafer center and closest corner of chip
Calculation of Speed Variation
p
A

B

A // B  A  B * B / B 2
|A//B| / |B| ratio is used to find process variation effect at location p
•Multiply this ratio by maximum on-chip variation to find cell speed
Hypothesis I : Chips at Same Angle
if equ-speed circles not evenly distributed on wafer:
A
B
1.1
1.2
•If process variation not linearly effecting cell speeds, maximum
on-chip variations for chipA and chipB will differ
•Chip2 has more variation, simulating for it is satisfactory
Hypothesis II : “Dominant Locations” on Wafer
•Check a number of angles on wafer
•We want other dies to pass too
•Make sure simulating effects of process variations for dies on
dominant locations is satisfactory
Test and Validation of Proposed Methods
Comparison Methodology
Extract cell locations from Astro
For each dominant location angle
{
Run script that changes cell speeds of a chip at a given angle
and given max. on-chip variation
Compare minimum setup times and hold times with a
nominal run
}
Used to show that location based variations can be deteriorating
as compared to worst-case runs
Comparison with Probabilistic Cell Speeds
For each dominant location angle
{
Run script that changes cell speeds of a chip using a uniform
distribution given max. on-chip variation
Run script that changes cell speeds of a chip using a Gaussian
distribution given max. on-chip variation
Compare minimum setup times and hold times with a location
based deterministic run
}
Used to show that location based variations can be deteriorating
as compared to probabilistic models due to systematic variation
Proof I : Checking Validity of Method for Chips on
Same Angle
For a number of variations up to max on-chip variation
{
Run script that changes cell speeds of a chip at angle 
}
Compare minimum setup times and hold times  runs
Used to show that for chips at same angle, simulating worst
variation is satisfactory
Proof II : Checking Validity of Dominant Locations
For a number of (angles \ dominant angles)
{
Run script that changes cell speeds of a chip given that angle
Check that minimum setup or hold times are higher than
found using dominant locations
}
Used to show that simulating for chips at dominant locations
satisfactory for any location
Experimental Results
Setup (max delay)
0.1243
Nominal
Location based
0.1001
0.1242 when less variation used
Uniform random
0.1206
Gaussian random
0.1234
•Up to 20% variation in minimum slack observed on ARM7
•Or, try setting clock to 1GHz whereas your chip can run @ 800MHz
on most locations on wafer
•Hypothesis I supported
Where Location Based Method fits in PrimeTime?
WC
Setup (max delay)
Hold (min delay)
1.74
1.71
TYP
3.92
1.40
BC
BC/WC
OCV
5.15
0.53
1.74
0.53
-1.70
-3.29
max delays  paths
max delays  paths for setup
max data min clock delays for setup
underestimate
overest.
Location based falls here, more realistic than both directions
Conclusions
•Dominant locations provide a means to reduce simulation
time, yet integrate more accurate process variation effects
•Probabilistic models fail to be satisfactory as they neglect
deterministic systematic relationship between cells
•Location based variation fits on a more realistic scale as
compared to current PrimeTime models
Future Directions
•Proper selection of dominant locations
•Incorporation of interconnect delay variations
A layout based mathematical approach