Transcript ped-rel-panel-narayanan

PED Roadmapping Issues
Vijaykrishnan Narayanan
Dept. of CSE
Penn State University
GSRC Workshop, March 20-21, 2003
Why PED-Robustness Roadmap?
speed/area speed
speed/power/reliability
area
speed/power
power
1970’s
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1980’s
low power reliable ultra-low power
1990’s
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Increasing variability
Static
 Changes in characteristics of devices and wire
 Caused by the IC manufacturing process & wear-out.
Runtime
 Changes in VDD, temperature, Vt, local coupling, external
noise sources
 Caused by runtime variation due to environment/operation.
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Impact on Optimizations
Lack of modeling resources or information flow can
transform variability to uncertainty.
Designing for worst case will not be power-efficient
Need for adaptation and dynamic monitoring

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Enablers: Modeling of noise sources, Interaction of parameters
that can be controlled at runtime, overheads
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Power-Reliability Interaction
 Supply voltage fluctuations can increase in power-aware design

Need models that can be adapted by architects/software designers that
abstract detailed circuit issues

Cost of hardware solutions - supply grids, decoupling capacitances

Cost of software solutions – balancing work load
 Substrate coupling between digital and analog
 Interconnect reliability and power
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
Noise sources – single errors, multiple errors, amplitude of the error sources,
modes of failure

Challenge – detecting the unobserved
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Detectable & Residual Word Error Rate
Word Error Rate
1.E+02
PAR-D
DED-D
TED-D
PAR-U
DED-U
TED-U
1.E-04
1.E-10
1.E-16
1.E-22
1.E-28
1.E-34
1.E-40
0.14
0.18
0.22
0.26
0.3
Noise Variance ( σ )
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Residual Word Error Rate
Dynamic Switching Error Detection Codes
1.E+02
PAR-U
1.E-04
DED-U
TED-U
1.E-10
DYN-U
1.E-16
1.E-22
1.E-28
1.E-34
1.E-40
0.14
0.18
0.22
0.26
0.3
Noise Variance ( σ )
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Power-Reliability Interaction
 Supply voltage fluctuations can increase in power-aware design

Need models that can be adapted by architects/software designers that
abstract detailed circuit issues

Cost of hardware solutions - supply grids, decoupling capacitances

Cost of software solutions – balancing work load
 Substrate coupling between digital and analog
 Interconnect reliability and power

Noise sources – single errors, multiple errors, amplitude of the error sources,
modes of failure

Challenge – detecting the unobserved

How to offset encoding/decoding costs – Just Enough Power
 Soft errors
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Soft Errors in Leakage Controlled SRAMs
Qcritical in fC for 1 -> 0 flips
350
14
300
12
250
10
200
8
150
6
4
100
2
50
0
0
D
GN
...
sy
ow
Dr
d
te
Ga
Leakage controlled circuits are more susceptible to Soft errors
Support for error correction and detection (SECDED)
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6T
D
GN
Qcritical depends on capacitance and voltage and is the key
parameter


...
sy
ow
Dr
d
te
Ga
6T
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Qcritical in fC for 0 -> 1 flips
16
Specially important for dirty data not written back
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Leakage Vs Soft Error Susceptibility
35
0.3
30
0.25
25
20
0.15
15
pJoules
fCoulumbs
0.2
0.1
10
5
0.05
0
0
0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00
Qcritical in Vdd
fC
Leakage in pJ/cycle
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Conclusion
 Need system approach that spans circuit, micro-
architecture, software to addressing problems
#1 Create models of physical/circuit effects reusable at higher
levels of abstraction – what is important to optimize?
#2 How to map applications onto the underlying heterogeneous
fabrics to meet energy and reliability requirements?
#3 What are new technologies that change slopes of technology
trends?
#4 Roadmap applications – what does the world need or rather what
can we give the world?
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