Transcript Fast Addressing of Plasma Display Panels

Fast Addressing of Plasma
Display Panels
Vladimir Nagorny
Plasma Dynamics Corp.
Addressing Speed

Frame (16.7ms) ≥10
Subfields




Reset ~ 300ms ·10  3ms
Address ~ 1-1.5ms/line (best)
5-7.5ms (500 lines)
10-15ms (1000 lines)
Sustain (Variable time)
Unless addressing speed
better (<1ms/line)

Single Scan
 Low Resolution, or dim
image

High Resolution
 Dual Scan
Plasma Dynamics Corp.
How to make addressing faster?
To answer this question one should first
answer other questions:

Q1: How does address discharge work?

Q2: Which factors control/limit its speed?

Q3: Are there any alternative ways to make
addressing faster?
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Q1: Starting point for addressing
Reset
Period

Vb
X

Y
VA
V AY
AY
XY
(sustain gap
discharge)
AX
V XY

Assume that at the end of the reset period
both SG and PG discharges are active, and
ramp is stable. This can be verified by
measuring the Vt-curve (K. Sakita, et al.,
SID2001; H. Kim, et. al., SID2001; S.T. de
Zwart and B. Salters, IDW2001).
Vt-curve is analog of the breakdown voltage
in 1D case and 2 electrodes. It positions
applied voltages with respect to discharge
conditions inside the cell, since it shows
where the balance between production of
charged particles and their losses is.
It doesn’t tell, though, anything about the
discharge, when one applies a vector V
which takes the cell off the balance.
XA
Plasma Dynamics Corp.
Q1:Vt-curve – what it is and what it is not
What it is:


Vt-curve depends on the wall charge surface distribution, which is not uniform and depends on real
parameters of a cell, discharge “history”, trajectory (VXY(t), VAY(t)) rather than final VXY, VAY  Vt-curve
transforms (Figs. below)  it has to be measured in every “critical” operation-wise point (after sustain
period, before and after ramps UP and Down, AFTER address discharge) otherwise actions one takes may
have undesirable results.
What it isn’t:


As in 1D case and 2 electrodes the knowledge of the breakdown voltage gives only the reference point for
comparison with voltage across the gap, the Vt-curve serves only as a reference line for 3 electrode system,
but it doesn’t give any information about the dynamics and the speed of the discharge.
When Va is applied, the field lines reconnect and conditions in the gap change completely. For example
V=(DVXY, DVA)=(10, 70) from SIP doesn’t mean VXY becomes 10V above the breakdown (next slide).
V
2
AY
2
1
1
0
F

3
VXY
0
3
4
0
0
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Q1: Field reconfiguration
End of the ramp case 1
End of the ramp case 2
End of the ramp+Va(80V) case 1
End of the ramp+Va(90V) case 2
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Q1: Experiments with priming
Va=80V case 1 (3D PIC/MC)
After the ramp cell is emptied of all
charges, address voltage applied and a
weak source (~1e/ms) imitating
exoemission is placed either near the
inner edge or in the central part of the
cathode.
Emission from the edge does not
produce self-sustaining discharge - it
decays.
Electron emitted in the center
produced ~4.5 times stronger
avalanche than from the edge, and
then number of particles increases with
characteristic time ~ 43ns by itself.
Plasma Dynamics Corp.
Q1: Summary of how discharge works

Details depend on geometry, but in any case address discharge
comprises a few phases:
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Priming – most likely by exoelectrons (unless external UV is present), and
following amplification due to avalanches.
Fast growing PG discharge – source of electrons for ALL other regions (due
to electron diffusion), leading to growth of the ion/current density
everywhere, as the source (PG discharge) grows.
Spread of the PG discharge and creating the SG “field channel”. Depending
on geometric parameters of the cell (SG vs. PG), SG channel may be created
sooner or later than PG discharge peaks. In the latter case a strong PG
discharge precedes SG discharge.
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Strong SG discharge.
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Decay of a plasma due to mostly recombination after SG discharge.
It is SG discharge, which creates a large memory charge. Removing the
scan voltage prior to plasma density decays will result in lowering
memory charge and may be even secondary discharge, erasing it.
Plasma Dynamics Corp.
Q2: Controls/limitations of the discharge
speed?
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Priming (statistical phase)
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PG discharge
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Mostly geometrical factors and capacitance of the dielectric near address and
sustain electrodes, Va. Channel can be created even at low Va, it will just take
longer time, which makes the whole process analogous rather than digital.
SG discharge
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Voltage across the gap, gap size ( t ~L-2 )
Creating the SG channel
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Both exoemission rate, structure and strength of PG field (Va). Stronger field,
higher exoemission rate  shorter delay.
Speed-no problem.
Decay (waste of time)

Mostly due to recombination. It requires ~0.5ms, otherwise the memory charge
will be reduced. Memory charge depends on actual applied voltage. No control of
the decay time.
Plasma Dynamics Corp.
Alternatives

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How about addressing more
than one line at a time,
achieving fast speed for
addressing a whole panel
rather than a single line?
Can we make addressing
“digital”?
What else can we do to
accelerate addressing of a
single line, using what we
have learned about the
discharge.
Movies - courtesy of Kenn Melvin:
ourworld.compuserve.com/homepages/kennmelvin
Plasma Dynamics Corp.
Addressing the ON cells

After SG discharge starts one can change the address voltage without
any effect. The SG discharge IS a release button for the ON cells.
Memory charge differs by only 2% (actually better with the switch)
If the cell is addressed ON, then one can apply the scan voltage and
address the next line right after start of the SG discharge without locking the
line back, having large memory charge and not wasting time for the decay.
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k
n
n'
ON
OFF
ON
ON
(n', k)


t
(n, k)
(n, k') (  50 )
Addressing the OFF cells
k'
Tscan,min
t
t

One need to have PG discharge in OFF cells to
prevent them from being addressed later on.
One can use different modes of the PG
discharge for OFF (weak) and ON (strong)
discharges.
OFF discharge being only PG discharge can be
made fast if PG is short and voltage Va high.
The higher voltage Va (while discharge is weak,
and no SG channel formation) the better.

(n', k')
t
V AY
(n, k)
t
(n, k') (  50 )
t
(n', k)
Natural geometry – short PG (T~L2), long SG 
TOFF<TON (=Tscan,min)
VOFF
AY
AX
t
V
(n', k')
t
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XA
XY
Dual Addressing, TOFF <TON
“Unlock the line” “address ON and OFF”  “go to the next line” (Taddr=TOFF )
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Addressing: Short PG
1. End of the Ramp Setup
3. After OFF discharge (VOFF=50V)
2. Address voltage (60V) is applied
4. Beginning of the ON discharge
VON=60V, t=335ns
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Parameters of the
OFF discharge
Parameter /Va
30V
40V
50V
60V
DVgap, V
62
70
102
Break (ON)
t1/2 , ns
270
155
118
xx
T(5000), ns
895
810
747
xx
Ni,max(105)
6.55
15
27.9
xx
Ttot, ns
770
680
472
xx
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Short PG – ON discharge
Vaddr=10V (VON=60V), First 335ns
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TOFF>TON : Advantages of Dual Addressing
k
n
n'
Taddr=TON (=Tscan,min)
k'
ON
OFF

ON
ON
Larger VOFF 

(n, k)
(n, k') (  50 )
t

Tscan,min
t
(n', k)
t
(n', k')
t
Lower Vaddr (Vaddr=VON-VOFF), or
higher possible VON
(combination of VOFF and
common V’addr):
VON=V’addr+VOFF
V AY
AY
T scan,min
(n, k)
V OFF
XY
(sustain gap
discharge)
t
AX
(n, k') (  50 )
t
(n', k)
t
(n', k')
t
V
XA
Plasma Dynamics Corp.
XY
Dual Addressing, TOFF >TON
TOFF>TON=Tscan,min  PG is large,
Taddr=TON, Vaddr=VON - VOFF
In addition to VOFF bias, one may
decrease the voltage between
sustain electrodes (VXlock) in order to
obstruct the spread of the discharge
across SG (better separate SG and
PG discharges) and maximize VOFF.
To maximize memory charge we
choose Vb,ramp higher than Vb by
“Unlock address ON and OFF  lock
go to the next line” (Taddr=TON )
VXlock. This is not necessary, though.
Plasma Dynamics Corp.
Summary
Dual addressing with discharges in both ON and OFF cells has

advantages, that come in one of three ways:

If parameters of a PDP cell allow one to achieve a fast OFF discharge
(TOFF<TON=Tscan,min) then one can address the panel with TOFF per line, using
“Unlock the line” “address ON and OFF”  “go to the next line” scheme.

If TOFF>TON, then Taddr=TON, but one can either use a lower voltage for address
drivers (Vaddr=VON - VOFF), or

Achieve a higher speed for the ON discharge and shorter Taddr by combining
conventional address drivers with large VOFF bias.
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In any case Taddr is smaller of TON and TOFF.
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In a cell with short PG we obtained addressing time of ~650ns with
Vaddr=10V, VOFF=50V.

In a cell with large PG (105-130um), TOFF > TON  Taddr=TON, and with
VXlock~30-40V we obtained VOFF>50V.
Plasma Dynamics Corp.