Transcript Research & Product Introduction

Research & Product Introduction
A Small Business Perspective
Presentation to SAITAMA Industry Executives
By Raj Nair, AnaSIM Corp.
February 15, 2007
Small Business is Key
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“Small Businesses are the heart of the American
economy because they drive innovation” *
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Employment & job creation
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Small technology businesses tend to take much greater RISK
Survival depends upon innovation
Go above and beyond ‘1% inspiration, 99% perspiration’
“Small and young companies create two-thirds (66%) of the
net new jobs in the American economy” * - US Data
Focused and Driven
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Led by Scientists, Engineers and Entrepreneurs, technology
ventures are determined to make a difference
Reference: * http://www.whitehouse.gov/infocus/smallbusiness/agenda.html
February 15, 2007
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Boldly Go Where No One Has
Existing Product,
Existing Customer
Existing Product, New
Customer
New Product, Existing
Customer
New Product, New
Customer
Small Business Target
February 15, 2007
AnaSIM – Nano Tech 2008
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See a Need, Fill a Need
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Technology GAP or Convergence
Usually infeasible for a small business to come up
with a revolution in technology (Cold Fusion…)
 Identify a GAP – area of technology unaddressed
 Or Convergence – a future need that will occur
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Conduct Studies
Is it a “Solution hunting for a problem?”
 Is it ‘Disruptive’ ?
 Is it a ‘Niche’ solution, or broadly applicable?
 Time to Market, Time to Money (TTM)
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February 15, 2007
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Partnering for Innovation
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Business strategy is to INNOVATE
Creativity, sometimes defined as “Seeing what
everyone sees and thinking what no one has”
leads to inventions, concepts with practical benefit
 But more important is the eventual useful product!
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Resources and Constraints
Innovation: further development of creative ideas
and inventions into NEW, useful product
 “A person invents, a team innovates”
 Tech. startups must ‘PARTNER’ to innovate / sell
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February 15, 2007
AnaSIM – Nano Tech 2008
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IP Strategy
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Four stages
IP Creation, Protection, Development & Defense
 Creation: figuring out an ingenious solution,
protection: filing national and international patents
 Development & Defense need varying resources
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Example: Proprietary Silicon IP
Architecture & Design may need minimal resources
 Filing patents may also be easy
 Fabrication, Testing, Characterization, detecting
and prosecuting infringement are very expensive!
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February 15, 2007
AnaSIM – Nano Tech 2008
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Anasim IP Protection Strategy
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Information Classification
Secret, Confidential and Public, with access control
 Confidential information provided only under nondisclosure agreement. Secret information shared
only under a partnership agreement.
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Patent filings
Proprietary IP deemed licensable, with no clear
advantage in secrecy, is patented
 Example is ‘Effective Current Density’ modeling
that is the core technology within -fp
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February 15, 2007
AnaSIM – Nano Tech 2008
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Market Strategy
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Understand End-User
Chip design community; diverse – Analog, Dig., RF
 In the past, depended on self-developed tools, but
increasingly dependent upon EDA Company Suites
 Preference for automation / masking of complexity
 Dependence/Reliance upon BIG EDA providers
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Understand Current Products
Strengths, Weaknesses, Opportunities…
 What does the end-user perceive as lacking?
 What inadequacies are current products hiding?
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February 15, 2007
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Anasim Marketing Strategy
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Vision
“Value-Add, NOT Compete”
 Anasim’s offering COMPLEMENTS existing products
 Anasim’s product ADDS quality to end-user’s work
product without disrupting existing methodology
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Differentiation to potential Partner
Partner’s EDA products enhanced by Anasim’s
 Holy Grail of WWW (Win-Win-Win) for Anasim,
Partner and End-User
 Leverage partner’s marketing infrastructure
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February 15, 2007
AnaSIM – Nano Tech 2008
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Practical Challenges
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Size, Credibility
Bootstrapped startup too small on radar screens
 Insufficient resources for effective marketing push
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Customer-Wins Difficult
Customers reluctant to devote resources to a NEW
‘unproven’ tool & methodology
 Inertia and risk-averseness widespread
 Ingrained “Copy Exactly” philosophy
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Conflicting Industry Messages
February 15, 2007
AnaSIM – Nano Tech 2008
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Motivation, Technology & Product
at Anasim Corp.
Presentation to SAITAMA Industry Executives
By Raj Nair, AnaSIM Corp.
February 15, 2007
SoC Voltage Minimization is Key
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Total power strongly V-dependent
Active power proportional to V2
 Leakage (tunneling) also related as Vx (DIBL, Efield, tunneling distance reduction with V)
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Energy / task minimized similarly
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ΔIDS ~linearly related to ΔV in nanoscale processes
Power Delivery
Must include voltage gating
 Must provide fine grain supply voltage control
 Needs accurate noise, power integrity estimation
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Reference: Nair, AZ Nanotechnology Symposium 2006
February 15, 2007
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Performance w/ Voltage Scaling
IDS  (VGSVT)
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15nm
Delay & Frequency
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Linear dependence in
deep nanoscale CMOS
CVdd/Ids ~constant
Nanoscale CMOS delay
and performance are
roughly constant within
a ΔVdd range of Vdd
Opportunity
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500
Vg = 0.8V
Intel’s 15nm NMOS
m A/ m m)
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25 nm
Drain Current (
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400
0.7V
300
0.6V
200
0.5V
0.4V
100
0.3V
Use lowest possible Vdd!
And maintain frequency
0
0
0.2
0.4
0.6
0.8
Drain Voltage (V)
Chau et al., IEDM 2000
February 15, 2007
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}
}
}
Low Power ≠ No Power
Integrity
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For Energy, not Frequency, it is Voltage
Reduced Voltage, reduced Frequency increases
task duration and wasted Leakage energy loss
 V  & F ~same  Active AND Leakage energy  
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L•di/dt remains significant at low V
 IDS
~linearly related to V in nanoscale processes
 Frequency ~ same, L•di/dt to V ratio is same
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Device variations require controlled V
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Nano process variation , low V makes it worse
Accurate, total supply noise estimation
a must
February 15, 2007
AnaSIM – Nano Tech 2008
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On-Die CAP for Noise Reduction
With Die Caps
Without Die Caps
Simple, lumped SPICE analyses indicate On-Die CAP helps in ΔVCC reduction
Area cost, Gate Oxide leakage are concerns
Reference: Narendra, ICCAD ‘03
February 15, 2007
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SoC Power Integrity Simulation
R+L+C Dynamic Noise Simulation in
-fp
9 x 7mm
chip
Differential
noise
5nF /sq. cm
distributed
CAP
Explicit CAP
LENS
100mA peak
noise pulse
of 100ps
width
Pulse noise
source
Power grid
simulation
Do CAPACITORS really absorb noise energy?
Source: D. Bennett, ANASIM Corp.,
February 15, 2007
-fp power integrity aware floor planner,
AnaSIM – Nano Tech 2008
www.anasim.com
Animation slide
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CAP Connectivity & Noise
Analysis on a CLOCK chip
Corner CAPs connected to IO Ring
Corner CAPs connected to Core Grid
CAPACITOR blocks from IO ring corners connected into Core
power grid increased noise in the core grid
Source: ANASIM Corp.,
February 15, 2007
-fp power integrity aware floor planner,
www.anasim.com
AnaSIM – Nano Tech 2008
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SoC Power Grid a Noise Conduit
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Low impedance grids
conduct and sum up
supply noise
Low energy loss in
global power grids 
more, sustained noise
Scaling and high perf.
 high local di/dt &
loop inductance leads
to greater local noise
Reference: Bennett, EEDesign 2003 article, www.anasim.com
February 15, 2007
AnaSIM – Nano Tech 2008
Animation slide
18
Power Gating & Noise Flow
Power Gating transforms preferred pathways for noise flow in addition to transient
noise generation due to large switched capacitances…
Source: ANASIM Corp.,
February 15, 2007
-fp power integrity aware floor planner,
www.anasim.com
AnaSIM – Nano Tech 2008
Animation slide
19
Effective Current Density (ECD)
Source: ANASIM Corp.,
February 15, 2007
-fp power integrity aware floor planner, http://www.anasim.com/content/Technology
AnaSIM – Nano Tech 2008
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Floor Planning & Power Integrity
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Advanced SoC’s
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February 15, 2007
AnaSIM – Nano Tech 2008
Must include power
integrity awareness in
pre- and post synthesis
floor planning
Must determine optimal
usage of power metal
Determine lowest
possible ‘noise band’
and best arrangement
of noise-sensitive blocks
Determine minimum
operating supply
voltage
All these including all of
power delivery stack
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System-level Noise Analysis
Noise excited by super-position of all chip loads upon power delivery stack
Source: ANASIM Corp.,
February 15, 2007
-fp power integrity aware floor planner,
www.anasim.com
AnaSIM – Nano Tech 2008
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Advanced SiP Solutions
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Near load systems
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Active Noise Regulator*
Distributed Local
Voltage Regulators
Chip power grid noise
Integrated Solutions
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On-Chip Dynamic
Voltage Scaling (DVS)
Energy Management in
Package (EMP)
Stacked power
conversion silicon layer
Intel® CMOS Regulator chip
Reference:
ANR attached to top left corner
* Nair & Bennett, ComLSI
Power Management Designline article http://www.powermanagementdesignline.com/howto/175800373
February 15, 2007
AnaSIM – Nano Tech 2008
Animation slide
of grid
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Summary
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Supply voltage optimization, minimization
is key to SoC energy management
Comprehensive, dynamic noise estimation
essential for low power/energy SoC design
Advanced noise estimation methodology
and tools needed for optimal floorplanning
Anasim’s pi-fp fulfils this need!
February 15, 2007
AnaSIM – Nano Tech 2008
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Backup
February 15, 2007
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