Transcript QE8 Low Power

Taking the Lead in Low Power
QE Family—The Low-end, ultra-low power S08QE8
Feb. 2008
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All other product or service names are the property of their respective owners. ©
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TM
Day’s Agenda
8:00 – 8:30 Registration
8:30 – 9:00
•
The Controller Continuum
9:00 to 10:00
•
Low Power applications
• Inside look at the QE8
• QE8 Board Overview
10:00 to 10:15 Break
10:15 to 12:00
•
Hands-on Labs

Initialization Utility
 Low Power Lab
 Touch Sensing lab
12:00 to 12:15
•
Closing remarks
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
The Industry is Changing
•
Embedded developers are increasingly tasked to design for a
portfolio of products ranging in performance
•
The challenge is that they have to use very different MCUs that
are typically not pin-compatible.
•
8-bit users are driven to reach performance ceilings with
increased demands for performance and functionality
•
The challenge is learning and using completely different tool
sets. This leads to more complicated processes that increase time
to market.
•
Economies of scale and process technology improvements push
costs down on 32-bit MCUs making them more affordable
•
Migrating across continuum of performance and price options
isn’t easy or quick when different bit architectures require recoding and different tools
Freescale is breaking bit boundaries to provide a simple and seamless path
to performance between 8-bit and 32-bit MCUs
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Industry’s Only Controller Continuum
The Freescale Controller
Continuum is our roadmap for
8-bit and 32-bit compatibility
ColdFire
V4
ColdFire
V3
ColdFire
V2
ColdFire
V1
HCS08 core
(QG, QD family)
32-bit
FlexisTM
The Controller
Continuum
“Connection Point”
RS08 core
(KA family)
8-bit
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
The “connection point” of the Continuum features
QE products – the industry’s first 8-bit and 32-bit
compatible MCUs
TM
QE8 Key Messages
The MC9S08QE8 microcontroller extends the ultra-low-power QE family offering high
integration with an ideal pin and memory combination to help our customers design
energy-efficient and high-performing applications.
Low Power
The QE8 offers industry-leading lowpower benefits through new and robust
low-power features.
The MC9S08QE8/4 extends the ultra-low-power
QE family and offers the lowest power benefits
of that MCU family and of our S08 portfolio.
The QE8 offers low-power features such as two
ultra-low power stop modes, new low-power run
and wait modes, 6 usec wake-up time from
stop3 mode, ultra-low power external oscillator
and clock gating registers to disable clocks to
unused peripherals.
The QE8 strongly positions Freescale against
TI’s MSP430 series offering “winning” features
at 1.8V such as 20MHz CPU, flash
reprogramming, ADC accuracy.
A full ecosystem of resources is available to
help you design in for low power for the
application you need. Application notes,
reference designs, and a low-power battery
calculator are located at
freescale.com/energyefficiency.
High Integration
Small Footprint
Offering a rich peripheral set, the QE8
offers high performance and makes
the development process flexible by
allowing you to choose what you need
from a wide range of features.
Small 8-bit footprint is ideal for
portable applications.
Creativity is not limited due to the amount of
peripheral options you can choose to enhance
the end customer experience.
Pin compatibility with other small footprint MCUs
such as QG, QD and other QE family parts.
QE is ideal for QG customers seeking additional
peripherals and lower power.
Plenty of IO for a low end product.
The QE8 includes a 1.8V to 3.6V supply voltage
range, a 20 MHz CPU core, two timers, UART,
SPI and IIC.
QE8 is ideal for small, portable applications
such as toys, pregnancy tests and low end
medical monitoring devices.
QE8 offers two analog comparators, a 10channel 12-bit ADC, temperature sensor and
highly accurate internal oscillator –perfect for
health care monitoring instrumentation and
electronics such as digital and web cameras.
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
5
Freescale 3V VLP MCU Continuum
51QE128
51QE128
Production - Available NOW
Execution - Specification Frozen, High Confidence Schedule
Planning - Specification Subject to Change, Tentative Schedule
Proposal - Project Subject to Change, Open to Market Feedback
S08QE128
S08QE128
S08QE128
S08QE128
CIO Only! - For Internal CIO Discussion ONLY, Not for Customers
S08QE 96
S08QE 96
S08QE 96
S08QE 96
9S08QE 60
S08QE 60
S08QE 60
S08QE 60
S08QE32
S08QE32
S08QE32
S08QE32
S08QE16
S08QE16
S08QE16
S08QE16
S08
CFV1
RS08
S08QE8
S08QE8
S08QE8
S08QE8
S08QE4
S08QE4
S08QE4
S08QE4
S08QG8
S08QG8
S08QB8
S08QG4
S08QG4
S08QB4
S08QA4
9S08QB4
S08QA2
9S08QB2
RS08KA2
RS08KA2
RS08KA8
RS08KA8
RS08KA1
RS08KA2
RS08KA4
RS08KA4
8 pin
16 pin
20 pin
6 pin
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product or service names are the property of their respective owners. © Freescale
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28 pin
32 pin
44 pin
48 pin
64 pin
80 pin
TM
MC9S08QE8/4
►
►
►
Special Features / Benefits
• Internal 32KHz clock source (Factory Trimmed to 0.5% typ.)
• Fast start-up time from STOP3 mode (~6uS)
• Ultra- Low power 1KHz oscillator (standby current <500 nA)
• Optimized clock tree and clock gating techniques
Supply Voltage / Performance
• 1.8 – 3.3 V operation
• -40 to 85°C operation
Core and I/O
• 20 MHz HCS08 core
• 10 MHz bus frequency max
• Up to 26 GPIO (8 KBI/slew rate control/pull ups)
►
Memory
• 8K/4K Flash, (16 pages of 512 bytes, 100K cycles)
• 512B/256B RAM
►
Communications
• SCI (with LIN support)
• SPI (full duplex/single wire/master/slave)
• IIC (with broadcast mode)
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
SCI
ICE
+
BDM
SPI
IIC
KBI
LVI
COP
2xACMP
ULP Regulator
10-ch
12-bit
ADC
ICS w/ ULP OSC
8/4K
Flash
2-ch
16-bit
Timer
2-ch
16-bit
Timer
512/256B
RAM
S08 Core
TM
MC9S08QE8/4
►
►
►
ADC
• 10 channel, 12 bit resolution
• 2.5uS conversion time
• Automatic compare function
• Temperature sensor
• Internal bandgap reference
• Operation in STOP3
Analog Comparator
• Dual comparator
• Selectable interrupt on either edge
• Compare option to internal bandgap reference
• Can feed a timer input
Timers
• Dual 16 bit Timer Counter Module
• Selectable input capture/ out compare/ buffered PWM
►
Packages
• 16 TSSOP, 16 PDIP, 20 SOIC, 28 SOIC, 32 LQFP
►
QE8 Pricing
• $1.15* MSRP at 10K units
2xSCI
ICE
+
BDM
SPI
IIC
KBI
LVI
COP
2xACMP
ULP Regulator
10-ch
12-bit
ADC
ICS w/ ULP OSC
8/4K
Flash
2-ch
16-bit
Timer
2-ch
16-bit
Timer
512/256B
RAM
S08 Core
*Varies by package
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Enabling Low-Power Products
Personal Medical Devices
Home Appliances
Low Power Wireless
Security Systems
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
Cell Phone Accessories
TM
Ultra-low-power Features
Low power run and wait modes
•
•
CPU and peripherals run with voltage regulator
in low power mode
Allows full functionality at reduced frequency
for lower power operation
Clock gating
•
•
Turns clocks off to unused peripherals
Reduces overall run and wait mode current
Internal regulator and oscillator
•
•
Fast start up from stop modes, typically 6-7 µs
New low power crystal oscillator consumes less than
1µA
Internal clock source and oscillator
•
•
Eliminates need for external clock source
Supports low frequency operations which lowers power
in system
Ultra-low-power real-time counter
•
•
Use in run, wait and stop modes
Use with low power oscillator, internal or external clock
sources
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Changes for Ultra-low Power
Reduce Run IDD
•
•
•
•
•
•
Implement new cell library and improved clock tree and gating
techniques
Achieved through new design tools
Re-architecture for module enabling/disabling during Run mode (explicit
clock gating)
Every peripheral has clock enable bit
Reset to clock enabled for compatibility with existing MCUs
Disabling clocks to unused modules reduces run and wait currents
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Changes for Ultra-low Power
Voltage Regulator (VREG)

VREG is always on when MCU is in Run or Wait modes
•
Also on when in stop3 with LVI or ADC enabled
• Runs internal logic at lower voltage, therefore lower power

Modify stand-by VREG to allow execution in
low power modes
•
New LPRun and LPWait modes allow
peripherals to run while VREG is in stand-by
• When in FLL Bypass Low Power Modes
(reduced operating frequency) place VREG in
un-regulated mode.
VDD
2.42V

Create new VREG with faster start-up
•
IDD
Allows more applications to use Stop modes
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Changes for Ultra-low Power
Reduce Stop3 IDD with oscillator enabled

RTC’s internal clock is not accurate over processing, voltage and
temperature variations
•
+/-35% frequency variation
•
Customers often require more accuracy

Current 32 kHz consumes ~5 uA in Stop3 mode

New 32 kHz loop-controlled crystal oscillator
•
Reduces typical Stop3 current from 5 uA to <1 uA
•
Allows for time-keeping accuracy at very low power
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Multiple Power-saving Modes
Highest
Functionality
New modes
for S08 and
ColdFire
► Run
► Wait
► Low-power
run (LPRun)
► Low-power
wait (LPWait)
► Stop3
► Stop2
Lowest Power
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Low-power Modes—Run
►Run Mode
• Standard user mode – default out of any reset
 Default frequency is ~8 MHz
 Clocks are enabled to CPU and all peripherals
• Typical IDD as low as 4.6 mA at 10 MHz CPU speed and 3V
with all modules on
• The voltage regulator is in active mode
►Advantages
• All peripherals can be used without limitations
• Interrupts can be serviced without changing modes
• Flash can be reprogrammed across all VDDs and
temperature
►Limitations
• Consumes more current than other modes
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
POWER
LIMIT
4.6
mA
TM
Low-power Modes—Wait
► Wait Mode
• The bus clock source remains active
• Clocks are disabled to CPU but peripherals can be clocked
• Typical IDD as low as 1.5 mA at 10 MHz CPU and 3V
► Advantages
• Reduces power consumption versus run mode
• No stop recovery time; the interrupt is serviced immediately
• Reduces noise while taking A-to-D readings
► Limitations
• The voltage regulator remains active, consuming more
current than stop or LP modes
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
WAIT
POWER
LIMIT
1.5
mA
TM
Low-power Modes—LPRun
► Low-power Run (LPRun) Mode
• The bus clock source is limited to FBELP
• Typical IDD as low as 20 uA at 16 kHz CPU and 3V when executing
from Flash (Lower if running from RAM)
• The voltage regulator is in low-power mode
► Advantages
• All peripherals can be used
• Reduces power consumption versus Run mode when high
performance is not required
• Interrupts can be serviced without changing modes
► Limitations
•
Flash cannot be programmed or erased
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
POWER
LIMIT
20
μA
TM
Low-power Modes—LPWait
► Low-power Wait (LPWait) Mode
• The bus clock source is limited to FBELP
• Clocks are disabled to CPU but peripherals can be clocked
• Typical IDD as low as 3.3 µA at 16 kHz CPU and 3V
• The voltage regulator is in low-power mode
► Advantages
• Reduces power consumption versus LPRun mode
• No stop recovery time; the interrupt stacking begins immediately
• Reduces noise while taking A-to-D readings
► Limitations
• Consumes more current than stop modes
• Maximum frequency is limited (see reference manual)
• Due to slower frequencies, may take longer to react to wake-up
trigger than stop2 or stop3 modes
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
LPWAIT
POWER
LIMIT
3.3
μA
TM
Low-power Modes—Stop3
► Stop3 Mode
• The equivalent to HC08’s Stop mode with typical IDD as low
as 300-400 nA at 3V
• Exit with any active interrupt: ADC, ACMP, IRQ, KBI, LVD,
RTC, SCI or reset
►Advantages
• Still has very low-current consumption
• RAM and register retain their values

•
Does not require reinitializing peripherals
Latency from interrupt event to code execution is only 5 us +
38 ICSOUT cycles (~6 us at 10 MHz)
STOP3
POWER
LIMIT
400
nA
► Limitations
• Not quite as low current as stop2
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Low-power Modes—Stop2
► Stop2 Mode
• Partial power down mode with typical IDD as low as
200-300 nA at 3V (no clocks to peripherals)
• Exit with wake-up pin (IRQ/RESET pin) or RTC

STOP2
Stop2 recovery is always through a system reset
► Advantages
• Lowest-power consumption mode for these devices
• RAM contents are maintained with I/O states latched
► Limitations
• Register values are reset, but values can be saved to
and restored from RAM
• Wake up latency from reset to code execution is ~5 us
+ 162 ICSOUT cycles. Since ICSOUT resets to ~ 8
MHz, the wake up time is ~29 usecs.
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
POWER
LIMIT
300
nA
TM
CPU Mode Comparison Chart
Typical CPU
Frequency
Set Up
Typical Idd 3V
Typical Idd 1.8V
Run
10 MHz
FEI mode, running from
flash, all peripherals off and
clocks disabled
4.6 mA
3.6 mA
n/a
n/a
Wait
10 MHz
FEI, enter from RAM, sll
peripherals off and clocks
disabled
1.5 mA
1.25 mA
Any interrupt
Instantly
LP Run
16 kHz
FBELP, all peripherals off
and clocks disabled
20 µA
11 µA
Clear LP bit or
interrupt with
LPWUI set
n/a
LP Run
16 kHz
FBELP, running from ram,
all peripherals off and
clocks disabled
5 µA
4 µA
Clear LP bit or
interrupt with
LPWUI set
n/a
LP Wait
16 kHz
FBELP, all peripherals off
and clocks disabled
3.3 µA
2.7 µA
Any interrupt
Instantly
6 µs
29 µs
Exit Sources
Stop 3
n/a
All modules disabled
275 nA
210 nA
RTC, LVD/LVW,
ADC, ACMP, IRQ,
SCI, KBI or
RESET
Stop 2
n/a
All modules disabled
200 nA
175 nA
RTC, IRQ or
RESET
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
Wake-up Time
TM
Typical Run Currents
Range: 25°C to 27°C
Voltage and Temperature
Test description
3 v @ 25°C
Idd
Units
2.4 v @ 25°C
2.1 v @ 25°C
1.8 v @ 25°C
Idd
Idd
Idd
Units
Units
Units
RUN Mode FEI: 10 MHz - all modules on
4.620
mA
4.628
mA
4.401
mA
3.600
mA
RUN Mode FEI: 10 MHz - all modules on except ADC
4.480
mA
4.480
mA
4.250
mA
3.450
mA
RUN Mode FEI: 10 MHz - all modules & clock gates off
3.489
mA
3.486
mA
3.308
mA
2.648
mA
RUN Mode FEI: 5 MHz - all modules on
2.740
mA
2.740
mA
2.634
mA
2.222
mA
RUN Mode FEI: 5 MHz - all modules on except ADC
2.580
mA
2.570
mA
2.470
mA
2.075
mA
RUN Mode FEI: 5 MHz - all modules & clock gates off
2.058
mA
2.056
mA
1.975
mA
1.658
mA
RUN Mode FEI: 1.25 MHz - all modules on
1.307
mA
1.301
mA
1.136
mA
1.001
mA
1.128
mA
1.125
mA
994.000
uA
862.600
uA
uA
871.700
uA
756.450
uA
RUN Mode FEI: 1.25 MHz - all modules on except ADC
RUN Mode FEI: 1.25 MHz - all modules & clock gates off
972.010
uA
968.000
Wait Mode FEI: 10 MHz - all modules on except ADC
2.594
mA
2.600
mA
2.490
mA
2.152
mA
Wait Mode FEI: 10 MHz - all modules & clock gates off
1.493
mA
1.490
mA
1.436
mA
1.254
mA
Wait Mode FEI: 5 MHz - all modules on except ADC
1.625
mA
1.623
mA
1.560
mA
1.364
mA
Wait Mode FEI: 5 MHz - all modules & clock gates off
1.040
mA
1.044
mA
933.700
uA
823.760
uA
Wait Mode FEI: 1.25 MHz - all modules on except ADC
877.000
uA
875.110
uA
804.640
uA
716.520
uA
Wait Mode FEI: 1.25 MHz - all modules & clock gates off
709.000
uA
708.000
uA
658.410
uA
590.230
uA
LP-Run Mode/FBELP: 16 kHz - all modules on
163.520
uA
160.840
uA
154.770
uA
143.740
uA
LP-Run Mode/FBELP: 16 kHz - all modules on except ADC
55.030
uA
54.394
uA
50.800
uA
44.150
uA
LP-Run Mode/FBELP: 16 kHz - all modules & clock gates off
20.355
uA
20.090
uA
17.423
uA
11.770
uA
LP-Wait Mode/FBELP: 16 kHz - all modules on except ADC
38.260
uA
37.860
uA
36.820
uA
35.333
uA
3.312
uA
3.294
uA
3.061
uA
2.705
uA
stop3: no clocks enabled
275.000
nA
256.000
nA
237.000
nA
210.000
nA
stop2: no clocks enabled
205.000
nA
196.200
nA
194.000
nA
173.000
nA
stop3: RTC running off LPO
374.000
nA
357.000
nA
335.000
nA
297.000
nA
1.582
uA
1.572
uA
1.487
uA
1.376
uA
stop3: ADC running(async clk, lowest power mode)
100.720
uA
98.990
uA
96.660
uA
91.580
uA
stop3, RTC, KBI, IRQ
384.000
nA
370.000
nA
336.000
nA
298.000
nA
stop2, RTC, IRQ
375.000
nA
358.000
nA
333.000
nA
298.000
nA
LP-Wait Mode/FBELP: 16 kHz - all modules & clock gates off
stop3: RTC running off 32kHz OSC
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product or service names are the property of their respective owners. © Freescale
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TM
Ultra-low Power Real-time Counter (RTC)
►Enhancement
from Real-Time Interrupt Module
►1 kHz internal low-power oscillator (LPO)
•
300 nA typical power consumption
No crystal required
Independent of internal bus clock source
•
•
►External
•
clock option for greater accuracy
550 nA typical power consumption with 32 kHz low
power oscillator
►Programmable
•
8-bit counter
15 selectable input clock prescalers
8-bit user programmable modulo value
•
•
►Can
wake-up intervals
be enabled in any mode
TIP
The internal LPO oscillator can be measured against the bus
clock. User software can adjust RTC timeout to compensate for
inaccurate LPO clock.
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product or service names are the property of their respective owners. © Freescale
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TM
Extending Battery Life—Clock Management
►Clock
•
•
management
Run fast when CPU performance is the critical
path
Run slow when waiting on peripherals

Use bus divider to reduce frequency without losing
FLL lock
 Instead of continuously reading a flag, use Wait
mode and interrupts
•
Use external clock option (FBELP) for lowest
power

Turns the FLL off
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product or service names are the property of their respective owners. © Freescale
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TM
System Clock Gating Registers
Peripherals are disabled on reset, but are clocked.
Users can save on power by gating clocking to unused
peripherals
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product or service names are the property of their respective owners. © Freescale
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1 - (default after reset) module is clocked
0 – module is not clocked
TM
uA saved through Clock Gating @ 10MHz bus in FEE mode on
MC9S08QE8
uA Saving through Clock Gating in Run
ADC
154
Flash
28
DBG
161
IIC1
140
RTC
119
IIC2
140
SCI1
112
SPI1
49
TPM1
133
Using the System Clock
Gating Registers
RUN IDD can be
reduced by up to ~30%
TPM2
126
CPU,SIM
ICS,PMC.LVD
Flash,RAM
IRQ
28
KBI
42
ACMP
112
The Rest
3535
Total Run IDD = 4.620mA
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product or service names are the property of their respective owners. © Freescale
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TM
Low Power Design Tips
► Always
have a pull-up or pull down on an input
► Powering
•
•
peripherals through I/O
uA level Icc for some analog functions
PFET transistor for higher momentary current
► Leakage
•
•
Capacitors (specially Aluminum electrolytics)
I/Os
► Dynamic
•
If the application is waiting for an I/O or peripheral, use the wait
instruction or reduce the clock of the MCU
► Battery
•
clock switching
technology
Peak current
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
QE8 Low Power Evaluation Platform
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. ©
Freescale Semiconductor, Inc. 2006.
TM
Future/Freescale Low Power Evaluation Paltform
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Easy-to-Use Development Tools and Training
► 9S08QE8BADGE
•
•
$199 Value, free to qualified customers
Low power demonstration kit including the QE8 card as
well as a built-in USB-BDM (with cable) for debugging
and programming. The tool includes a hardware lab that
demonstrates the ultra-low-power benefits and displays
the results in real time on a LCD.
► CodeWarrior
Development Studio for
Microcontrollers v6.1
•
•
FREE Special Edition with compiler sizes of 32K
Single tool suite that supports software development for
future migration opportunities for both 8-bit or 32-bit and
includes rapid application development tool, Processor
Expert



$4,995 Professional Edition
$2,495 Standard Edition
$995 C Compiler Upgrade
► Other
online training, webcast, technical
documentation and application notes available at
freescale.com/lowpower
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
What is CodeWarrior Development Studio 6?
•CodeWarrior
offers all the components needed
throughout the various stages of a project
Integrated Development Environment/Project Manager
Project
Wizard
• Device
• Language
• Default
Connection
• Add Files
• RAD
• C/C++
Options
Project
Creation
Important
Choices
are Made
Device
Knowledge
Database
Device
Initialization
Editor
Compiler
Debugger
Data
Visualization
Multi-Target
Interface
I/O Stimulation
Assembler
API
Processor
Expert
Linker
H/W-Specific
Code Generation
Application-Specific
Code Development
Shortened
Learning
Curve
User-Friendly
Performance
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
Simulator Multilink
Test/Debug
and Validation
Revision
Control
and
Configuration
Management
RTOS
Awareness
USB (e.g. inDart)
H/W–S/W
Integration
Multi-H/W Capable
Enhanced BDM
Flash Programming
Product Life
Support/Update
Revision Control
Quality Control
TM
What's New in Release V6.0
►
A project can be re-targeted in as few as 4 mouse clicks
1
3
2
4
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
MCU Change Wizard
►In
the background CodeWarrior reconfigures your project with…
►Correct
•
•
•
Build Tools ►Correct Supporting Files ►Updated derivative.h file ►Updated hidef.h file
Assembler
Compiler
Linker
•
•
•
•
Startup Code
Libraries
C header files
Porting Support file
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
•
•
New _Stop and _Wait
macros
Updated map file
•
New
EnableInterrupts and
DisableInterrupts
macros
TM
What's New in Release V6.0
►
Device Initialization Tool
•
Generates assembly code for RS08
derivatives
•
Generates C or assembly code for
HC08 and HCS08 derivatives
•
Generates C code for ColdFire V1
derivatives
•
Choice of adding code to
project or creating a text file
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
What's New in Release V6.0
► Processor
•
What is it?


► What
•
•
•
Expert
Hardware Abstraction Layer (HAL)
–
Low-level drivers with a known application programming
interface (API)
–
Eases migration between Freescale devices
Built-in knowledgebase immediately flags
resource conflicts and incorrect settings
is new?
ColdFire V1 Support
Improved timing interface
New Bean Selector Assistant
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Typical Low Power Application
Interrupt
Service
Routine
main() or
task()
main() or
task()
STOP3
RUN/IRQ
RUN Mode
STOP3
Power Consumption
Event occurs
STOP Mode
Waiting for RTI,
IRQ, or KBI
Waiting for RTI,
IRQ, or KBI
Time
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Approach 1: Average Current
► Keep
MCU running at low frequency with RTC providing 1 second
intervals to take ADC reading:
Average current = MCU run current at 16 kHz bus ADC off x % time
+ MCU run current at 16 kHz bus ADC on x % time
S08 = 22 uA x (5 sec – 5 x ADCLP conv time)/5 sec
+ 224 uA x (5 x ADCLP conv time)/5 sec
= 22.1 uA
(one ADCLP conversion time = 329 usec with 16 kHz bus)
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Approach 2: Average Current
► Use
crystal on MCU to provide accurate clock during Stop3. Use
RTC to wake every second for ADC measurement. Every 5th
measurement ramp frequency and process data:
Average current
S08
= MCU Stop3 current w RTC and xtal × %time
+ MCU Run current while ADC on × %time
+ MCU Run current while communicating × %time
= 920 nA × (5 sec - 5 x ADCHS conv time – processing time)/5 sec
+ 5.1 mA × (5 x ADCHS conv time)/5 sec
+ 12 mA × (processing time)/5 sec
= 0.92 uA + .018 uA + 0.192 uA = 1.13 uA
Notes: One ADCHS conversion time = 3.5 usec with 8 MHz bus. Assuming processing time of
2000 cycles for S08, 500 cycles for V1
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Approach 3: Average Current
► Use
LPO on MCU to provide clock during Stop2. Use RTC to wake
every second for ADC measurement. Every 5th measurement ramp
frequency and process data:
Average current
S08
= MCU Stop2 current w RTC and LPO× %time
+ MCU Run current while ADC on × %time
+ MCU Run current while communicating × %time
= 0.67 uA × (5 sec - 5 x ADCHS conv time – processing time)/5 sec
+ 5.1 mA × (5 x ADCHS conv time)/5 sec
+ 4.5 mA × (processing time)/5 sec
= 0.67 uA + .018 uA + 0.192 uA = 0.88 uA
Notes: One ADCHS conversion time = 3.5 usec with 8 MHz bus.
Assuming processing time of 2000 cycles for S08
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Battery Life vs. Average Current
Battery Life vs. Average Current
22
20
Approach 2
1.13 uA
18
Years
16
Approach 1
22.1 uA
14
12
10
Approach 3
0.88 uA
AA
AAA
CR2450
CR2430
8
6
4
2
0
0.1
1.0
10.0
100.0
1000.0
Average Current (uA)
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Typical Low Power Mode Usage
Run Mode
Power Consumption
Run Mode
High speed servicing is required:
Increase core speed up to 10 Mhz with
internal clock generator
Complete task, then back to Stop mode
External event triggers RUN mode
Fast startup self clock mode
Stop 2
Device times out, enter
standby power down
Stop 2
Standby power down
Time
Stop 3 w/ AWT Enabled
Run Mode
Internal 1Khz wakeup osc on
AWT triggers Run Mode
Check if high speed service necessary,
If not go back to Stop 3 with AWT enabled
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Average Current Computation
► The
longer the integration time,
the greater the accuracy
Average current
Power Consumption
Long term energy average over
user defined time period
Time
PRESS
START
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
PRESS
START
TM
Future QE8 Eval Board Diagram
USB
LCD
Debug
Interface
Power Control
Battery
Power Measurement
Select Matrix
Control MPU
QE8 MPU
SMD Proto Area
Power In
Power Measurement Circuit
(Integrating)
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
Low Power
Peripherals
TM
Power Routing
5V
USB
Power In
Power
Source
Select
Boost
circuit
Battery
2.0V to 3.3V
Regulator #1
Manual adjust
Measurement
Select
QE8 MPU
D.U.T.
SMD Proto
Area
Regulator #2
Low Power
Peripherals
Current Measurement
Circuit
Selects if each
zone has its
power measured
or not measured
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Basic board functionality
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
The LCD Display
► To
display time, current and voltage information
► 1 Second refresh rate
► Max integration time 9999 seconds
► Precision:
•
•
•
►
0.1uA to 100mA+
+/- 25mV on Voltage
Time +/- <1%
The LCD interface is
not available to the
Application processor
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Peripherals and Debug
adjust (2V – 3.3V)
► Debug Interface
► Voltage
•
IN/OUT BDM capable
► Power
Source Select
► Measurement Select
•
CPU
• Proto Area
• Peripherals
• Independently measured or not
► Peripherals
•
•
•
•
•
(w/ Power Enable)
LED
Button
Optical Sensor
8Mb Serial Flash and RAM
Serial Port
► Touch
Sensor
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Peripheral Power Distribution
► Each
peripherals can be individually
powered via DIP switch S2
•
•
•
•
•
•
•
Serial Port (user installed)
SPI RAM
Temperature Sensor
Optical Sensor
Variable resistor (10K)
SPI Flash (user installed)
Touch interface pull up
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
CPU and Proto Area
► Application
•
All I/Os are free to use
► Surface
•
•
•
CPU (Device Under test)
Mount Prototype Area
Used for user defined circuits
Local measured supply
 2.0-3.3V
Additional 5V
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Default Jumper Configuration
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Touch sensing Interface
► Compatible
with Freescale’s
Touch Sensing Technology
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Board Operational Notes
► Force
•
BDM mode
If processor is in sleep mode, jumper on BDM connector (pin 1-2) during
a power up will force the processor in BDM mode
► Calibration
•
Needed when the Control processor is reflashed or for component drift

Force calibration by pressing the CALIBRATE button on power up
► External
•
•
crystal
4 MHz yields a 250KHz minimum bus clock for FBE mode
Most application will use a 32KHz watch crystal
► Difference
•
in results
Largely depends when START button is used (in dynamic operation)
► Changing
•
procedure
voltage setting during an average calculation
Will provide erroneous results
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Lab: Create a simple
Processor ExpertTM Project
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. ©
Freescale Semiconductor, Inc. 2006.
TM
Exploring the QE8 low-power features
In this lab we examine:
► How the ICS contributes to low power operation
► How peripheral are used for clock gating
► How to configure the different operation modes and transition between them
► How much current each operation mode consumes
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Internal Clock Source - ICS
►
Six modes of operation
•
FBI: FLL bypassed, internal reference
•
FEI: FLL engaged, internal reference
•
FBE: FLL bypassed, external reference
•
FEE: FLL engaged, external reference
•
FBILP: FLL bypassed, internal reference, low power
•
FBELP: FLL bypassed, external reference, low
power
Ext.
OSC
Int.
OSC
FBE & FBELP*
FBI & FBILP
* FBELP is only valid clock mode for new
LPRun & LPWait modes
ICSOUT
►
Three modes require no external
components
► All modes are s/w selectable
•
►
►
User program can switch between modes
at any time
CPU frequency = ICSOUT
Bus frequency = ½ ICSOUT
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
DCO’s:
L,M,H
Filter
FEE
FEI
FLL
TM
Internal Clock Source - ICS
( CPU BUS CLOCK = ICSOUT /2)
Flexible Clocking module provides
Optimum MHz vs. mA operation.
FLL Input clock range 30-40KHz.
RDIV provides divide of ext clock
inputs.
BDIV provides /1/2/4/8 of FLL.
FEI
FEE
FBI
FBE
FBILP
FBELP
Mode
FLL Engaged Internal
FLL Engaged External
FLL Bypassed Internal
FLL Bypassed External
FBI Low Power
FBE Low Power
Freq. Range
1-25MHz
1KHz-25MHz
1.95-19.6KHz
dc-8MHz
1.95-19.6KHz
dc-100KHz
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
Input
RC osc
ext XTAL/OSC/clock
RC osc
ext XTAL/OSC/clock
RC osc
ext XTAL/OSC/clock
Additional internal 1kHz Low Power
Oscillator (LPO) optional clock source
for RTC and WDOG
TM
How does power relate to ICS?
►
Software-selectable bus frequency divider (BDIV)
•
•
•
►
Low-power or high-gain oscillator options
•
►
Low-power limits voltage swing on oscillator pins to minimize power
consumption
The external reference can be left enabled in stop mode
•
►
Available in all clock modes
Allows frequency changes without losing FLL Lock in FEI and FEE
Run fast only when needed
32 kHz crystal in low-power mode adds 250nA to stop IDD!
Stop mode currents are affected only by the references enabled in
stop mode, not the ICS mode before entering
•
Ex: if running FEE mode with ext oscillator enabled in stop mode, only
the ext oscillator will be enabled when stop is entered, the FLL will be
disabled automatically
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Internal Clock Source (ICS)
Register Definition
Name
ICS Control
Register 1
ICS Control
Register 2
ICS Trim
Register
ICS Status
and Control
7
6
5
4
3
2
1
0
IREFS
IRCLKEN
IREFSTE
N
EREFS
ERCLKEN
EREFSTE
N
R
ICSC1
CLKS
RDIV
W
R
ICSC2
BDIV
RANGE
HGO
LP
W
R
ICSTRM
TRIM
W
R
DRST
ICSSC
IREFST
CLKST
OSCINIT
DMX32
W
FTRIM
DRS
= Unimplemented or Reserved
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Internal Clock Source (ICS)
Register Definition
ICS Control Register 1 (ICSC1)
7
6
5
4
3
2
1
0
IREFS
IRCLKEN
IREFSTEN
1
0
0
R
CLKS
RDIV
W
Reset
0
0
0
0
0
7:6 CLKS Clock Source Select — Selects the clock source that controls the bus frequency.
• 00
Output of FLL is selected
• 01
Internal reference clock is selected
• 10
External reference clock is selected
• 11
Reserved, defaults to 00
5:3 RDIV Reference Divider — Selects the amount to divide down the external reference clock. Resulting
frequency must be in the range 31.25kHz to 39.0625kHz
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Internal Clock Source (ICS)
Register Definition
7
R
6
5
CLKS
4
3
RDIV
2
1
0
IREFS
IRCLKEN
IREFSTEN
1
0
0
W
Reset
0
0
0
0
0
2 IREFS Internal Reference Select — The IREFS bit selects the reference clock source for the FLL
• 1 Internal reference clock selected
• 0 External reference clock selected
1 IRCLKEN Internal Reference Clock Enable — The IRCLKEN bit enables the internal reference clock
for use as ICSIRCLK
• 1 ICSIRCLK active
• 0 ICSIRCLK inactive
0 IREFSTEN Internal Reference Stop Enable — The IREFSTEN bit controls whether or not the internal
reference clock remains enabled when the ICS enters stop mode
• 1 Internal reference clock stays enabled in stop if IRCLKEN is set before entering stop
• 0 Internal reference clock is disable in stop
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Internal Clock Source (ICS)
Register Definition
ICS Control Register 2 (ICSC2)
7
R
6
BDIV
5
4
3
2
1
0
RANGE
HGO
LP
EREFS
ERCLKEN
EREFSTEN
0
0
0
0
0
0
W
Reset
0
1
7:6 BDIV Bus Frequency Divider — Selects the amount to divide down the clock source selected by the
CLKS bits.
• 00 Encoding 0 – Divides selected clock by 1
• 01 Encoding 1 – Divides selected clock by 2 (reset default)
• 10 Encoding 2 – Divides selected clock by 4
• 11 Encoding 3 – Divides selected clock by 8
5 RANGE Frequency Range Select — Selects the frequency range for the external oscillator.
• 1 High frequency range selected for the external oscillator
• 0 Low frequency range selected for the external oscillator
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Internal Clock Source (ICS)
Register Definition
7
R
6
BDIV
5
4
3
2
1
0
RANGE
HGO
LP
EREFS
ERCLKEN
EREFSTEN
0
0
0
0
0
0
W
Reset
0
1
4 HGO High Gain Oscillator Select — The HGO bit controls the external oscillator mode of operation.
• 1 Configure external oscillator for high gain operation
• 0 Configure external oscillator for low power operation
3 LP Low Power Select — The LP bit controls whether the FLL is disable in FLL bypassed modes.
• 1 FLL is disable in bypass modes unless BDM is active
• 0 FLL is no disable in bypass modes
2 EREFS External Reference Select — The EREFS bit selects the source for the external reference
clock.
• 1 Oscillator requested
• 0 External Clock Source requested
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Internal Clock Source (ICS)
Register Definition
7
R
6
BDIV
5
4
3
2
1
0
RANGE
HGO
LP
EREFS
ERCLKEN
EREFSTEN
0
0
0
0
0
0
W
Reset
0
1
1 ERCLKEN External Reference Enable — The ERCLKEN bit enables the external reference clock for
use as ICSERCLK.
• 1 ICSERCLK active
• 0 ICSERCLK inactive
0 EREFSTEN External Reference Stop Enable — The EREFSTEN bit controls whether or not the
external reference clock remains enable when the ICS enters stop mode.
• 1 External reference clock stays enabled in stop if ERCLKEN is set before entering stop
• 0 External reference clock is disable in stop
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Internal Clock Source (ICS)
Register Definition
ICS Trim Register (ICSTRM)
7
6
5
R
4
3
2
1
0
TRIM
W
Reset
Note: TRIM values get uploaded with the Factory Programmed Trim values after any system reset
7:0 TRIM ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling
the internal reference clock period
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Internal Clock Source (ICS)
Register Definition
ICS Status and Control (ICSSC)
7
6
R
DRST
W
DRS
Reset
5
4
3
IREFST
2
CLKST
1
OSCINIT
DMX32
0
0
0
0
FTRIM
1
0
0
0
1
7 DRST DCO Range Status — The DRST read field indicates the current frequency range for the FLL
output, DCOOUT.
6 DRS DCO Range Select – The DRS field selects the frequency range for the FLL output, DCOOUT.
• 00
Low Range
• 01
Mid range
• 10
High range
• 11
Reserved
= Unimplemented or Reserved
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Internal Clock Source (ICS)
Register Definition
7
6
R
DRST
W
DRS
Reset
5
4
3
IREFST
2
CLKST
1
OSCINIT
DMX32
0
0
0
0
FTRIM
1
0
0
0
1
5 DMX32 DCO Maximum frequency with 32.768 kHz reference — The DMX32 bit controls whether or
not the DCO frequency range is narrowed to its maximum frequency with a 32.768 kHz reference.
• 0 DCO has default range of 25%
• 1 DCO is fined tuned for maximum frequency with 32.768 kHz reference.
4 IREFST Internal Reference Status – The IREFST bit indicates the current source for the reference
clock.
• 0 Source of reference clock is external clock.
• 1 Source of reference clock is internal clock.
= Unimplemented or Reserved
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Internal Clock Source (ICS)
Register Definition
7
6
R
DRST
W
DRS
Reset
5
4
3
IREFST
2
CLKST
1
OSCINIT
DMX32
0
0
0
0
FTRIM
1
0
0
0
1
3:2 CLKST Clock Mode Status — The CLKST bits indicate the current clock mode.
• 00
Output FLL is selected
• 01
FLL Bypassed, internal reference clock is selected
• 10
FLL Bypassed, external reference clock is selected
• 11
Reserved
1 OSCINIT OSC Initialization – If the external reference clock is selected by ERCLKEN or the ICS and if
EREFS is set, then this bit is set after the initialization cycles of the external oscillator clock have
completed.
0 FTRIM ICS Fine Trim – The FTRIM bit controls the smallest adjustment of the internal reference clock
frequency.
= Unimplemented or Reserved
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product or service names are the property of their respective owners. © Freescale
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TM
System Power Management Status and Control 1 Register
SPM Status and Control 1 (SPMSC1)
R
7
6
LVDF
0
4
3
2
LVDIE
LVDRE
LVDSE
LVDE
0
1
0
0
1
0
0
BGBE
LVDACK
W
Reset
5
0
0
0
1
7 LVDF Low Voltage Detect Flag — Provided LVDE =1, this read-only status bit indicates a low voltage
detect event
6 LVDACK Low Voltage Detect Acknowledge – This write only bit is used to acknowledge low voltage
detection errors (write 1 to clear LVDF). Reads always return a 0.
5 LVDIE Low Voltage Detect Interrupt Enable – This bit enables hardware interrupt requests for LVDF.
• 0 = Hardware interrupt disabled (use polling).
• 1 = Request a hardware interrupt when LVDF = 1.
4 LVDRE Low Voltage Detect Reset Enable – This write once bit enables LVDF events to generate a
hardware reset provided LVDE = 1.
• 0 = LVDF does not generate hardware reset
• 1 = Force an MCU reset when LVDF = 1.
= Unimplemented or Reserved
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product or service names are the property of their respective owners. © Freescale
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TM
System Power Management Status and Control 1 Register
R
7
6
LVDF
0
4
3
2
LVDIE
LVDRE
LVDSE
LVDE
0
1
0
0
1
0
0
BGBE
LVDACK
W
Reset
5
0
0
0
1
3 LVSE Low Voltage Detect STOP Enable — Provided LVDE =1, this read/write bit determines whether
the low voltage detect function operates when the MCU is in STOP mode.
• 0 = low voltage detect is DISABLED during STOP mode.
• 1 = low voltage detect is ENABLED during STOP mode.
2 LVDE Low Voltage Detect Enable – This write-once bit enables low voltage detect logic and qualifies
the operation of other bits in this register.
• 0 = LVD logic DISABLED
• 1 = LVD logic ENABLED
0 BGBE Bandgap Buffer Enable – This bit enables an internal buffer for the bandgap voltage reference
for use by the ADC module on one of it’s internal channels or as a voltage reference for the the ACMP
module.
• 0 = Bandgap buffer DISABLED.
= Unimplemented or Reserved
• 1 = Bandgap buffer ENABLED.
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product or service names are the property of their respective owners. © Freescale
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TM
System Power Management Status and Control 2 Register
SPM Status and Control 2 (SPMSC2)
7
R
W
6
5
4
LPRS
LPR
3
2
PPDF
0
LPWUI
1
0
PPDE
PPDC
PPDACK
Reset
0
0
0
0
0
0
0
0
Stop2 exit
0
0
u
0
1
0
1
1
7 LPR Low Power Regulator Control — The LPR bit controls entry into the low power and wait modes in
which the voltage regulator is put into standby. This bit cannot be set if PPDC=1. If PPDC and LPR are
set in a single write instruction, only PPDC will actually be set. Automatically cleared when LPWUI is set
and an interrupt occurs.
• 0 = Low Power run and wait modes are disabled
• 1 = Low Power run and wait modes are enabled
6 LPRS Low Power Regulator Status– This read only status bit indicates that the voltage regulator has
entered into standby for the low power run and wait mode.
• 0 = the voltage regulator is NOT in standby
• 1 = the voltage regulator is in standby
5 LPWUI Low Power Wake on Interrupt – The LPWUI bit controls whether or not the voltage regulator
exits standby when any active MCU interrupt occur.
• 0 = The voltage regulator will remain in standby on an interrupt.
• 1 = The voltage regulator will exit standby on an interrupt.
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product or service names are the property of their respective owners. © Freescale
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= Unimplemented or Reserved
TM
System Power Management Status and Control 2 Register
7
R
W
6
5
4
LPRS
LPR
3
2
PPDF
0
LPWUI
1
0
PPDE
PPDC
PPDACK
Reset
0
0
0
0
0
0
0
0
Stop2 exit
0
0
u
0
1
0
1
1
3 PPDF Partial Power Down Flag — This read-only status bit indicates the MCU has recovered from a
STOP2 mode.
• 0 = MCU has not recovered from a STOP2 mode
• 1 = MCU has recovered from a STOP2 mode
2 PPDACK Partial Power Down Acknowledge – Writing a 1 to this bit clears the PPDF bit
1 PPDE Partial Power Down Enable – The write-once PPDE bit is used to enable the partial power
down feature.
• 0 = Partial power down disabled.
• 1 = Partial power down enabled and controlled by the PPDC bit.
0 PPDC Partial Power Down Control – The PPDC bit controls which power down mode is selected. This
bit can not be set if LPR = 1.
• 0 = STOP mode 3 selected
• 1 = STOP mode 2 selected
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= Unimplemented or Reserved
TM
Power Mode Selection Table
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
►Here
is a summary of the project created:
•
Configured the PTC0 to output a value to LED1 using Device
Initialization
•
Configured the internal timer to generate an interrupt every 1 second
using Device Initialization
•
Created an interrupt service that turns on and off the LED every 1
second
•
Lower power consumption by reducing clock and enter wait modes
•
Program and run the project using the CodeWarrior debugger
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Click on Create
New Project
Note:
If you don’t see the Startup screen, go
to the File menu and select Startup
Dialog…
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Select the
MC9S08QE8
2
Select the Open
Source BDM
3
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product or service names are the property of their respective owners. © Freescale
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Click Next
TM
Lab: Device Initialization
1
Enter “Project_Dev_Init”
as the Project Name
2
Set the Location to the
Desktop
3 Click Next
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
Click Next
TM
Lab: Device Initialization
1
Select Device
Initialization
2
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
Click Finish
TM
Lab: Device Initialization
Click Select CPU
Package button
Select
MC9S08QE8CFM
1
2
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Double click on the
PTC peripheral field to
configure the port C
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Change the Port control
property in the Settings
group to the Individual
pins value
2
Enabled Pin0 by clicking
on the “loop” arrow
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Enable the Pin 0 and select its
direction to be the Output
2
Click the OK
button to confirm
the setup
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Double click on the
TPM1 peripheral
field to configure the
timer
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Change the Clock
source select to
Bus rate clock
2
Change the
Prescaler to 32
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Enable the
Overflow
Interrupt in the
Interrupts group
2
Write LEDTimer
as the ISR name
3
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product or service names are the property of their respective owners. © Freescale
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Click the OK button
to confirm the setup
TM
Lab: Device Initialization
1
Click on the
Generate Code
button
Note: Code will be
generated for modules
highlighted in blue
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
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product or service names are the property of their respective owners. © Freescale
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Click on the
“Generate Code”
button
TM
Lab: Device Initialization
1
Click “OK” button
If you selected the Device Initialization in the New Project Wizard,
the device initialization setup is automatically handled for you.
When you open Device Initialization in an Open Project, please
follow the steps outlined in dialogue box. The steps are also outlined
in the following slides.
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Open MCUint.c by double
clicking on the file in the
project manager
Please note: If you added the generated
code to the project, the files will appear in the
Generated Code folder.
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Type or paste the
following lines into a
generated body of the
LEDtimer ISR in the
MCUinit.c:
PTCD_PTCD0 = ~PTCD_PTCD0;
TPM1SC_TOF = 0;
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Click on the Make icon to
compile and link the project
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Click on Debug to begin
the debugging session
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Confirm the Flash
programming dialog by
clicking OK
Confirm that you want
to stop the previously
loaded program
2
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Device Initialization
1
Click the green arrow to
begin running the project
DONE …
The LED0 will start blinking in
the 0.5s intervals
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Power on a Budget
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All other product or service names are the property of their respective owners. ©
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TM
Low-power Lab
1.
Open CodeWarrior V6.0
2.
Open the project:
Start08.c
System and Peripheral
Initialization
LowPowerLab.mcp
(Folder Labs on the Desktop)
3.
Stop2 Recovery?
Open the main.c file and inspect the code
No
Stop2 Rec.
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product or service names are the property of their respective owners. © Freescale
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POR Boot
KBI
Interrupt
Buttons Switch
State
RTC
Interrupt
Led status
TM
Low Power Lab Usage
► SW1
to SW4 selects mode of
operation (led turn on for ~1sec)
•
SW1

•
SW2

•
Pressing SW2 will place the processor in LPRUN
mode running at 250 KHz
SW3

•
Pressing SW1 will place the processor in full speed
mode running at 10 MHz
Pressing SW3 will place the processor in STOP3
mode with RTC running with LPO
SW4

Pressing SW4 will place the processor in STOP2
mode with RTC disabled (lowest power mode)
Note: LEDs are very dim when operated at 2V.
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product or service names are the property of their respective owners. © Freescale
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TM
CPU Initialization
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Starting the Code Walkthrough
• Maximize the LowPowerLab.mcp CodeWarrior project file
• In the left pane, select main.c from the Sources folder to view the project code
• Project code will appear in the right pane of the CodeWarrior IDE
• The following code will be explained in detail in the upcoming slides
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product or service names are the property of their respective owners. © Freescale
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TM
Header Files & Function Declarations
#include <hidef.h>
#include "derivative.h”
• hide.h header file contains:
• EnableInterrupts Macro to unmask CPU interrupts
• derivative.h header file contains:
• STOP MACRO
• WAIT MACRO
• Connection to the MCU-specific header file that
contains labels for:
interrupt vectors
I/O
peripheral memory locations.
The main file uses these labels extensively to
access memory locations.
MC9S08QE8.h
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TM
Main Function
void main(void) {
MCU_Init();
if(!SPMSC2_PPDF)
POR_Boot();
else
PTCD = (byte)Unitialized_RAM[0];
Stop2Recovery();
State = PortSense(State);
for (;;){
switch (mode){
case 1:
LED1 on for 1 sec
break;
case 2:
LED2 on for 1 sec
break
case 4:
Enter_Stop();
LED3 on for 1 sec;
Wait1ms();
//RTCSC = 0x0F;
break;
case 8:
Unitialized_RAM[0] = PTCD;
RTCSC = 0x0F;
Wait1ms();
Enter_Stop();
default:
state=0;
break;
} } }
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product or service names are the property of their respective owners. © Freescale
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•
•
•
•
Enter Main Function
Calls MCU_Init() function to perform the following
tasks:
1. Set-up system options
2. Configure ports
3. Deactivate low voltage detect system
4. Set up the Real Time Counter to create an
interrupt every 1s.
Test PPDF flag to see if reset was from STOP2
And take appropriate action for recovery if needed
TM
Main Function
void main(void) {
MCU_Init();
if(!SPMSC2_PPDF)
POR_Boot();
else
PTCD = (byte)Unitialized_RAM[0];
Stop2Recovery();
State = PortSense(State);
for (;;){
switch (mode){
case 1:
LED1 on for 1 sec
break;
case 2:
LED2 on for 1 sec
break
case 4:
Enter_Stop();
LED3 on for 1 sec;
Wait1ms();
//RTCSC = 0x0F;
break;
case 8:
Unitialized_RAM[0] = PTCD;
RTCSC = 0x0F;
Wait1ms();
Enter_Stop();
default:
state=0;
break;
}
}
• Switch statement uses the State variable to determine
which case to enter
State
Variable
Operation
1
2
3
Enter Run Mode FEI with core at 10MHz, RTC 1sec
Enter LPRun Mode w/ peripherals off, RTC 1 sec
Enter STOP3 Mode with RTC 1 second
4
STOP2 Mode, no RTC
• PortSense() is used to update the button state information
}
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product or service names are the property of their respective owners. © Freescale
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TM
Main Function
byte PortSense(byte Current){
if(mode != Current) {
if (mode == 1) {
ICS_Run_Mode();
WaitNms(10);
SPMSC2 = RUN_SPMSC2;
return(mode);
}
else if (mode == 2) {
ICS_Low_Power();
WaitNms(10);
SPMSC2 = LP_RUN_SPMSC2;
return(mode);
}
else if (mode == 4) {
ICS_Run_Mode();
Wait1ms();
SPMSC2 = RUN_SPMSC2;
ICS_Run_Mode();
return(mode);
}
else if (mode == 8) {
ICS_Run_Mode();
Wait1ms();
SPMSC2 = STOP2_SPMSC2;
ICS_Run_Mode();
return(mode);
}
else {
mode = Current;
return(Current);
} } }
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product or service names are the property of their respective owners. © Freescale
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• Switch statement uses the State variable to determine
which case to enter
• This is where the clock is reconfigured
TM
Real Time Counter Interrupt Service Routine
• Found in MCU_Init.c
• After ~1s, RTC ISR is entered
• Flag is updated to notify main loop
• RTC Interrupt is acknowledged by writing to the
RTC interrupt flag bit.
• Program returns to Main function
__interrupt void isrVrtc(void)
{
RTC_Flag = True;
RTCSC_RTIF = 1;
}
RTC Status and Control Register (RTCSC)
Reset:
R
W
R
W
7
6
RTIF
5
RTICLKS
4
3
2
RTIE
1
0
RTCPS
7
6
5
4
3
2
1
0
1
0
0
1
0
0
1
0
RTIF – Bit 7
Writing a logic 1 clears the bit and the
real-time interrupt request.
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product or service names are the property of their respective owners. © Freescale
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TM
Real Time Counter Interrupt Service Routine
• Found in MCU_Init.c as well
• ISR is entered when key is depressed
• Flag is updated to notify main loop
• Mode variable is updated from key status (PTA port)
• KBI Interrupt is acknowledged by writing to the
RTC interrupt flag bit.
• Program returns to Main function
__interrupt void isrVkeyboard(void)
{
mode = (byte)((~PTAD)&0x0F);
KBISC_KBACK = 1;
firstflag = 1;
}
KBI Status and Control Register (KBISC)
7
6
5
4
R
W
R
W
3
2
1
0
KBF
KBACK
KBIE
KBIMOD
7
6
5
4
3
2
1
0
0
0
0
0
X
1
X
X
KBACK – Bit 2
Writing a logic 1 clears the bit and the
KBI interrupt request.
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product or service names are the property of their respective owners. © Freescale
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TM
Clock Configuration Function
void ICS_Config(unsigned char CTL1, unsigned char CTL2,byte TrimValue, byte CTL3)
{
if(CTL1 & IREFS_INTERNAL){
ICSC2_LP = 0;
ICSC1 = CTL1;
/* init ISC control register 1 */
while(!ICSSC_IREFST);
ICSC2 = CTL2;
/* init ISC control register 2 */
ICSTRM = (unsigned char)TrimValue;
ICSSC = CTL3;
/* init ISC control register 3 */
if(ICSC1_CLKS == 0b01){
while (ICSSC_CLKST != ICSC1_CLKS);
}
else {
while (ICSSC_CLKST != ICSC1_CLKS);
while ((ICSSC&ICSSC_DRST_DRS_MASK) != (CTL3&ICSSC_DRST_DRS_MASK) );
} }
else {
ICSC2
= CTL2;
/* init ISC control register 2 */
ICSC1
= CTL1;
/* init ISC control register 1 */
ICSSC
= CTL3;
if(ICSC1_CLKS == 0b10){
while (ICSSC_CLKST != ICSC1_CLKS);
}
else {
while (ICSSC_CLKST != ICSC1_CLKS);
while ((ICSSC&ICSSC_DRST_DRS_MASK) != (CTL3&ICSSC_DRST_DRS_MASK) );
} } }
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product or service names are the property of their respective owners. © Freescale
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TM
Configuring the ICS and SPMSC2
In the main.c file, configuration of the ICS for the different modes of operation is
done via a defined macro:
Also in main.c file we are configuring the
System Power Management Status and Control 2 Register
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TM
Running from RAM
► WAIT
and STOP instructions can be initiated from RAM instead of
FLASH
► This significantly reduce power
► How?
•
For FLASH: Declare a STOP or WAIT opcode followed by a RTS (return
from subroutine) opcode as const types
const unsigned char FlsStop[0x02] = {0x8E, 0x81};
•
For RAM: Declare a STOP or WAIT opcode followed by a RTS (return
from subroutine) opcode as constant types
static unsigned char RamStop[0x02]= {0x8E, 0x81};
► Then
•
call the subroutine (declared as macro)
#define Enter_Stop asm(jsr RamStop)
► Defined
in “target.h”
► Change the commented line and test the result!
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product or service names are the property of their respective owners. © Freescale
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TM
Lab: Proximity Sensing Project
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All other product or service names are the property of their respective owners. ©
Freescale Semiconductor, Inc. 2006.
TM
Enabling Next Generation Products
Gaming Controllers
Cellular Handsets
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
PC Peripherals
Home Appliances
Portable Media Devices
TM
LAB 3: Capacitive Sensing Techniques
► Changing
the response time of an I/O when the line capacitance is
influenced by an external body
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product or service names are the property of their respective owners. © Freescale
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TM
Touch sensing Interface
► Compatible
with Freescale’s Touch
Sensing Technology
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
LAB 3: Capacitive Proximity Sensing
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Proximity Sensing Lab setup
►
Open the project:
•
•
PROXIMITY.mcp
(Folder Labs on the Desktop)
►
Open the main.c file and inspect the code
►
Open the GPIO.c
•
Using the concept of Virtual I/O for portability
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Resources
www.freescale.com/lowpower
►Site
•
•
Application Notes for designing in low power
Battery Calculator—available now

•
•
includes:
Now Available Including QE128 devices
Designing for Low Power Tips and Tricks
Coming Soon: Video on QE8 Low Power Lab
►Low power technical presentation
• Online Training on Low Power through www.freescale.com/training
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Example Notes
► LPRun
and LPWait modes are most useful when a module that
cannot run in stop modes is needed all the time.
► LPRun
currents fall dramatically if code can be executed from RAM
instead of Flash.
► Stop3
mode can be entered directly from LPRun mode to save
additional current. Stop2 mode cannot.
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product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Resource: Battery Life Calculator
HCS08 Battery Life Calculator
featuring the QE128 devices:
• Available on web at
www.freescale.com/lowpower
• estimates battery life based
on system variables
• Select from variety of
standard battery sizes and
types or enter battery
characteristics directly
MC9S08QE8 calculations
in battery calculator are
coming soon!
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM
Lab Conclusion
The QE8/4 devices have industry leading ultra-low power
features and are very easy to use, while conserving the
processing power
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners. © Freescale
Semiconductor, Inc. 2006.
TM