Transcript L24-Crosstalk1

L24:Crosstalk-Concerned
Physical Design
1999. 10
Jun Dong Cho
Sungkyunkwan Univ. Dept. ECE
E-Mail : [email protected]
Homepage : vada.skku.ac.kr
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Agenda
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Characteristics of Crosstalk
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Basic Approaches in Crosstalk Avoidance
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Recent Approaches in Crosstalk Avoidance
Routing
Conclusion
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Characteristics of Crosstalk
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Introduction
Trends on Crosstalk Problem
What is Crosstalk in Signal Line?
Special Requirement for Crosstalk Avoidance
Crosstalk Avoidance in Low Power
Design Issues for Noise
Algorithmic Approaches Crosstalk Avoidance
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Introduction
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The state-of-the-art in digital integrated circuit is rapidly
approaching a point where conventional device signal models are
no longer effective in predicting the behavior of ICs. The challenge
of maintaining signal integrity is present in designs implemented in
deep sub-micron technology that operates at speeds quickly
approaching 1GHz and above.
Smaller devices, more condensed geometry and smaller signal
swing are used to achieve this high-speed performance.This highspeed approach has yielded a higher noise-coupling rate and a
lower noise margin as the side effects. Consequently, signal
integrity and interconnect modeling have become more critical than
ever.
In the scaling from 1.8 um to 0.9 um pitch, line-to-line
capacitance increases from 46% to 68% of full-loaded self
capacitance
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Trends on Crosstalk Problem
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Crosstalk is a well-known phenomenon at all levels of electronic packaging
from system level cables through wires on printed circuit board ,multi-chipmodules to chip level routing and inside of VLSI interconnection.
Crosstalk causes undesired signal noise to be coupled from an active line
(Aggressor) into a quiet line (Victim). Depending on its magnitude, the
induced noise onto the victim may influence the timing behavior of the victim
signal by increasing its setup time. It may even cause failure by inducing
false pulses or causing false signal levels which may be propagated through
the circuit.
With increasing integration density and reduced cycle times, these effects
become more visible and more destructive, so they need to be handled more
carefully. Crosstalk needs to be considered in particular on VLSI chips with
sub-micron structures and today’s large die size.
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What is Crosstalk in Signal Line?
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Crosstalk is a
capacitive and
inductive
interference
caused by the
noise voltage
developed on
signal lines when
nearby lines
change state
V aggressor
Ci
Li
aggressor
Rout
Cm
time
Lm
V victim
victim
Rout
Ci
(a)
coupled
noise
Li
time
(b)
It is a function of the separation between signal lines, the linear distance that
signals lines run parallel with each other. The faster edge rates of today's
logic devices greatly increase the possibility of coupling or crosstalk
between signals. To maximize speed, crosstalk must be reduced to levels
where no extra time is required for the signal to stabilize. Signals such as
clocks, that are highly sensitive to crosstalk should be isolated by reference
planes from signals on other layers and/or by extrawide line-to-line spacing.
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Special Requirement
for Crosstalk Avoidance
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Data buses : Crosstalk between buses tends to be data-patterns-sensitive and
it is worse when all addresses or data lines change in the same direction at the
same time. Signals common to a given bus can run next to other signals in the
bus, but not with other buses or signals.
Memory address and data signals : A data-to-address-line cross-coupling may
upset address lines sufficiently to cause write signals to incorrect memory
locations. Therefore, high-speed memory address and data signals need to be
isolated by reference planes and by extra-wide line-to-line spacing from other
signals, particularly other memory chip-selects, address line, and data buses.
Clock signals and Strobes : To meet crosstalk limits, clock signals must be
isolated and confined between reference layers. Other signals must not be
mixed with clocks. Clock signals on a given layer must have extra spacing
between lines. Clock signals of different frequencies must have extra-wide
spacing, as clock signals and other signals if they are to be mixed.
ECL and analog : ECL and analog signals require a high degree of isolation
from TTL-level or CMOS-level signals. They must be physically isolated in
separate board areas with separate ground and voltage planes that are isolated
from TTL or CMOS switching currents.
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Crosstalk Avoidance in Low Power
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The average dynamic power consumed by a CMOS gate is given below,
where Cl is the load capacity at the output of the node, V is the supply
dd
voltage, Tcycle is the global clock period, N is the number of transitions of the
gate output per clock cycle,
isCthe
load capacity due to input
g
capacitance of fanout gates, and C w is the load capacity due to the
interconnection tree formed between the driver and its fanout gates.
2
2
V
V
Pav  0.5 dd Cl N  0.5 dd (Cg  Cw ) N
Tcycle
Tcycle
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Logic synthesis for low power attempts to minimize  Cgi N,whereas
physical
i
i
design for low power tries to minimize  Cwi N i. Here Cwconsists
of two
i
i
terms Cxi  Csi , where Cxi is the capacitance
of net i due to its crosstalk, and
C si is the substrate capacitance of net i. For low power layout applications,
power dissipation due to crosstalk is minimized by ensuring that wires carrying
high activity signals are placed sufficiently far from the other wires. Similarly,
power dissipation due to substrate capacitance is proportional to the wire length
C
and its signal activity. In this paper, we aim to minimize
. xi  Csi
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Multi-layer of Lines
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Cross-coupling is very significant From above, below, left, or right
If left and right adjacent lines are transitioning at the same time that
the signal of interest transitions, we have an increased loading effect
(referred to as Miller multiplication)
Ctotal = Cdown + Cup + 2 Cleft + 2 Cright
Tdelay = 2.3 R0 (Cline+Cload) + Rline Cline +2.3 Rline Cload
Gate delay is decreasing with dimensional scaling
RC delay is increasing with
dimensional scaling
RC delay in long lines is proportional
to L square
For lines longer than “L”
Vnoise = (CLL/Ctotal) Vdd, CLL is
total simultaneous switching
coupling capacitance
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Ctotal = Cdown+Cup + Cleft + Cright
Cup
Cleft
Cright
Cdown
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Design Issues for Noise
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Reduce coupling noise
Increase driver strength
Increase spacing between wires or route signal lines alternately with power
or ground.
Constraint-driven routing
Reducing power supply noise
Ensure that power grid is sized correctly for the load it is serving to reduce
IR drop
Add on-chip decoupling capacitance to reduce delta-I noise. With
increasing use of dynamic circuits, there is less NWELL capacitance on-chip.
When employing cores, one must be sensitive to the quality of the
interconnects which will carry signals between cores and the ASIC portion of
the network
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Approaches to Crosstalk
Avoidance
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Analysis
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Efficient mode for filtering and driver for physical design
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Mixture of static/ dynamic analysis tools needed
Interconnect Planning
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Present routing methodology increasingly inadequate
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Mixture of planning & constrained synthesis needed
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Efficient Noise metrics
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Noise avoidance routing
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Clocking - managing skew, interconnect vs. device variability
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Buffer Insertion - needs to better integrated into design methodology
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Use of design guidelines necessary in practice
Noise/ SI problems are difficult and pervasive, but are TRACTABLE!!!
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Noise Avoidance
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Interference Graph
Node: nets/segments of nets
Undirected Edges: horizontal constraint
Directed Edges: Vertical Constraints
Edge Weights: Design Rules, Coupling Rules
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Transistor Sizing
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X is the set (vector) of transistor sizes
Minimize Area(X) subject to Delay(X) <= Tspec
Minimize Power(X) subject to Delay(X) <= Tspec
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Pdynamic  C LVdd f PT
Pshortckt   / 12 (Vdd  2VT ) 2  f PT ,
  transcondu ctance,   transitio n time
B
C
A
Less than 10 - 20% of total power in a well - designed circuit
Problem with interacting paths
(1) Better to size A than to size all of B,C and D
D
(2) If X-E is near-critical and A-D is critical,
size A (not D)
E
x
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Basic Approaches
in Crosstalk Avoidance
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Segregation / Spacing / Ground Shielding
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Net Ordering
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Layer Assignment
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Pattern Routing
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Segregation / Spacing
/ Ground Shielding (1)
Noisy
Region
Extra
space
Segregation
Quiet
Region
Spacing
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Segregation / Spacing
/ Ground Shielding (2)
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Segregation : Dividing many
(noisy) and less(quiet) signal
transition wire and merging group
by group.(use with shielding)
Spacing : the method that signal
wire to shun each other, when
signal net is close to each other
(routing channel is not wide)
Grounded
Shields
Shielding : blocking signal line
with ground line to minimize
signal interference to the other
wire.(ground bounce occurs and
must broaden the ground line)
Shielding
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Net Ordering
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Net ordering is used for minimize crosstalk-critical region between each
lines. When, long line and long line is close together, crosstalk between
them is more larger than long line and short line. So, we must change the
permutation of track for minimizing crosstalk.
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Left : Unordered
track permutation
S
S
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Right : Ordered
track permutation
for minimizing
crosstalk
L
L
L
L
S
L
S
S
L
S
L
L
L
S
L
S
L
L
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Layer Assignment
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When using more than 3 layer in channel routing, adjacent signal wire in same
layer results crosstalk. For example, left figure makes more crosstalk than right.
Layer assignment problem is solved by integer linear programming or dynamic
programming method.
Unodered net
Layer1
Layer2
Ordered net
Layer3
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Pattern Routing
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In global routing, global interconnection wires have more long and thick wire
than local interconnection wire.
Pattern routing method
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Make wire pattern satisfying design specification.
Choose corresponding wire pattern.
Minimize total crosstalk.
Q2
Q1
Q3
Q4
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