Transcript Lecture Slides

Hardware Description Languages
ECE 3450
M. A. Jupina, VU, 2014
Lecture Objective
A brief (very brief) discussion of VHDL and the future of
VHDL-AMS and mixed signal ICs.
References:
1. Fundamentals of Digital Logic, Sections 2.10 and 4.12
and Appendix A.
2. Document files at the course web site
ECE 3450
M. A. Jupina, VU, 2014
VHDL - VHSIC (Very High Speed
Integrated Circuit) Hardware
Description Language
• VHDL is code that is used to describe hardware
rather than a program to be executed on a
computer.
• For example, other HDLs: Verilog and AHDL
ECE 3450
M. A. Jupina, VU, 2014
VHDL for Combinational Logic
• VHDL is a language used for simulation and
synthesis of digital logic.
• A VHDL description of a digital system can be
transformed into a gate level implementation.
This process is known as synthesis.
ECE 3450
M. A. Jupina, VU, 2014
Logic Synthesis
Logic Synthesis: convert a description of a digital system in a
Hardware Description Language (HDL) to an implementation
technology.
HDL description
library ieee;
use ieee.std_logic_1164.all;
Gates
entity majority is
port (
A, B, C : in std_logic;
Y:
out std_logic
);
end majority;
Synthesis
ARCHITECTURE a of majority is
begin
Y <= (A and B) or (A and C) or (B and C);
end a;
ECE 3450
M. A. Jupina, VU, 2014
VHDL Statements
• VHDL has a reputation as a complex language (it is!)
• We will use a small subset of the language for our
purposes
• Some VHDL constructs:
– Signal Assignment: A <= B;
– Comparisons = (equal), > (greater than), < (less
than), etc.
– Boolean operations AND, OR, NOT, XOR
– Sequential statements (CASE, IF, FOR)
– Concurrent statements (when-else)
ECE 3450
M. A. Jupina, VU, 2014
VHDL Combinational Template
• Every VHDL model is composed of an entity
and at least one architecture .
• Entity describes the interface to the model
(inputs, outputs)
• Architecture describes the behavior of the
model
• Can have multiple architectures for one
entity (we will only use one in this class).
ECE 3450
M. A. Jupina, VU, 2014
A VHDL Template for Combinational Logic
entity model_name is
port (
list of inputs and outputs );
end model_name;
architecture arch_name of model_name is
begin
concurrent statement 1
concurrent statement 2
... concurrent statement N;
end arch_name;
All of the text not in italics are VHDL
keywords. VHDL is NOT case sensitive. (ENTITY is
same as entity is same as EnTiTy).
ECE 3450
M. A. Jupina, VU, 2014
A VHDL Example of an XOR Gate
Description
Implementation
library ieee;
use ieee.std_logic_1164.all;
entity example is
port ( A, B, C : in std_logic;
Y: out std_logic );
end example;
-- this is the architecture declaration, uses only
-- one concurrent statement.
ARCHITECTURE a of example is
begin
Y <= (A and B) or (A and C) or (B and C);
end a;
ECE 3450
M. A. Jupina, VU, 2014
VHDL References/Resources
• Brown and Vranesic textbook (Sections 2.10
and 4.12 and Appendix A)
• Course Website
 VHDL overview from Hamblen’s book
 Dr. Kresch’s VHDL overview
 VHDL Files from the textbook
ECE 3450
M. A. Jupina, VU, 2014
Analog and Mixed Signal VHDL
(VHDL-AMS)
• The IEEE 1076.1 language (VHDL-AMS) is a superset of
the IEEE Std 1076-1993 (VHDL) that provides capabilities
for describing and simulating analog and mixed-signal
systems.
• VHDL-AMS was developed to provide the industry with a
high-level design language to master future challenges in
both mixed digital and analog system design as well as
multi-physics applications.
• Currently, VHDL-AMS provides simulation only. Future
software could provide synthesis. For example, fieldprogrammable analog arrays (FPAA) are being developed.
A FPAA containing many (~20) analog function blocks
could be configured as DC level shifters, rectifiers,
amplifiers, filters, oscillators, comparators, equalizers, etc.
ECE 3450
M. A. Jupina, VU, 2014
FPAA Reconfiguration Example
While FPAA technology is very young, and still expensive,
it could someday be useful for creating communications
products that would work on any standard.
For instance, a cell phone with a re-programmable analog-to-digital
converter would search the entire communications band for a
signal, then grab the necessary program from memory to make
itself into a code-division multiple access (CDMA), time-division
multiple access (TDMA), or global system for mobile
communications (GSM) phone. Such a phone could be used in
Japan, Europe, or the US without modification.
ECE 3450
M. A. Jupina, VU, 2014
VHDL-AMS Code Example
-- VHDL-AMS model of an Analog Schmitt Trigger
-- Description
-- This Schmitt trigger uses a signal to model a simple hysteresis
-- loop. When the input voltage exceeds the high threshold, the internal
-- state switches to 5 Volts and when the input drops below the low threshold,
-- the state switches to 0 Volts.
-- The output is an ideal voltage source which contributes to the output
-- terminal OutTerminal.
-LIBRARY DISCIPLINES;
LIBRARY IEEE;
USE DISCIPLINES.ELECTROMAGNETIC_SYSTEM.ALL;
USE IEEE.MATH_REAL.ALL;
entity AnalogSchmitt is
end entity AnalogSchmitt;
architecture Hysteresis of AnalogSchmitt is
TERMINAL n1,n2 : ELECTRICAL;
ECE 3450
M. A. Jupina, VU, 2014
VHDL-AMS Example Continued
-- declare a signal to memorize the hysteresis state:
SIGNAL State : REAL := 0.0; -- initial state is low
QUANTITY vin ACROSS iin THROUGH n1;
-- declare a through branch for the output voltage source
quantity vout across iout through n2;
begin
-- the architecture consists of two architecture statements:
-- a conditional concurrent signal assignment to implement the hysteresis
-- a simultaneous statement to implement the equation for the output source
vin == 5.0 * sin(2.0 * math_pi*0.5E3*NOW);
-- hysteresis:
break State => 0.0 when Vin'above(1.0); -- trigger event when Vin > 1.0
break State => 5.0 when not Vin'above(2.4); -- trigger event when Vin < 2.4
-- output voltage source equation:
vout == State'Ramp(1.0e-9,1.0e-9); -- the use of ramp assures that when a discontinuity
-- in State arises, it is announced to the simulator
end architecture Hysteresis;
ECE 3450
M. A. Jupina, VU, 2014